================
@@ -399,6 +400,27 @@ static bool CC_RISCV_Impl(unsigned ValNo, MVT ValVT, MVT
LocVT,
}
}
+ if (ArgFlags.isSwiftSelf() || ArgFlags.isSwiftError() ||
+ ArgFlags.isSwiftAsync()) {
+ if (LocVT != XLenVT)
+ reportFatalUsageError(
+ "swiftself, swifterror, and swiftasync arguments must be "
+ "pointer-sized on RISC-V");
+ if (!IsEABI) {
+ MCRegister Reg = RISCV::NoRegister;
+ if (ArgFlags.isSwiftSelf())
+ Reg = State.AllocateReg(RISCV::X18);
+ else if (ArgFlags.isSwiftError())
+ Reg = State.AllocateReg(RISCV::X19);
+ else if (ArgFlags.isSwiftAsync())
+ Reg = State.AllocateReg(RISCV::X20);
+ if (Reg) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
----------------
lenary wrote:
How does this work when these registers are callee-saved?
Please have a reportFatalUsageError if `IsEABI`, or change `supportsSwiftError`
to exclude the `IsEABI` case.
https://github.com/llvm/llvm-project/pull/205469
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