================
@@ -368,9 +401,110 @@ void AMDGPUPromoteAllocaImpl::setFunctionLimits(const
Function &F) {
VGPRBudgetRatio = PromoteAllocaToVectorVGPRRatio;
}
-bool AMDGPUPromoteAllocaImpl::run(Function &F, bool PromoteToLDS) {
- if (DisablePromoteAllocaToLDS && DisablePromoteAllocaToVector)
+// A "VGPR as memory" object can only be realized in registers today when every
+// access is a constant-offset, dword-aligned, whole-dword-multiple (32, 64,
...
+// bit) load/store and its address never escapes. Sub-dword accesses, dynamic
+// indexing and escaping addresses are not yet supported; such objects fall
back
+// to scratch instead.
+//
+// TODO: Lower dynamically-indexed / escaping VGPR objects so this fallback is
no
+// longer needed.
+static bool isVGPRAllocaStaticallyLowerable(const AllocaInst &AI,
----------------
arsenm wrote:
The feature is broken if it requires this sort of not-structurally-guaranteed
analysis. The fundamentals need to always work, and not depend on the exact
uses. Sub-dword access needs to be lowered as RMW sequences, and escaping
addresses also need to work
https://github.com/llvm/llvm-project/pull/205435
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