llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) <details> <summary>Changes</summary> Move towards using the triple for representing incompatible ISA changes. Use the subarch field to represent the various incompatible cases. Previously we pretended a single triple arch was universally compatible, and only distinguished by function level subtargets. Move towards using distinct triples to enable more sophisticated toolchain handling in the future, like proper runtime library linking. Introduce a new subarch per unique ISA, but also introduce "major subarches" which are compatible by a set of covered minor ISA versions. These map to the existing generic targets. There are a few placeholder subarch entries, which currently have missing backing generic arches for codegen. This should be the preferred triple arch name going forward, but is treated as an alias of amdgcn. This does not yet change clang to emit the new triples. Part of #<!-- -->154925 --- Patch is 284.93 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/206480.diff 78 Files Affected: - (modified) clang/include/clang/Basic/Attr.td (+2-2) - (modified) clang/lib/Basic/OffloadArch.cpp (+1-2) - (modified) clang/lib/Basic/Targets.cpp (+1-1) - (modified) clang/lib/Basic/Targets/SPIR.cpp (+1-1) - (modified) clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp (+1-1) - (modified) clang/lib/CIR/CodeGen/CIRGenModule.cpp (+1-1) - (modified) clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp (+1-1) - (modified) clang/lib/CodeGen/CGBuiltin.cpp (+1-1) - (modified) clang/lib/CodeGen/CodeGenModule.cpp (+3-3) - (modified) clang/lib/Driver/Driver.cpp (+4-7) - (modified) clang/lib/Driver/ToolChain.cpp (+1-1) - (modified) clang/lib/Driver/ToolChains/CommonArgs.cpp (+3-3) - (modified) clang/lib/Driver/ToolChains/Darwin.cpp (+1-1) - (modified) clang/lib/Driver/ToolChains/Flang.cpp (+1-2) - (modified) clang/lib/Driver/ToolChains/Gnu.cpp (+1-1) - (modified) clang/lib/Sema/SemaAMDGPU.cpp (+1-1) - (modified) clang/lib/Sema/SemaChecking.cpp (+3-3) - (modified) clang/test/Driver/amdgpu-toolchain.c (+8) - (modified) clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp (+1-1) - (modified) flang/include/flang/Tools/TargetSetup.h (+1-1) - (modified) flang/lib/Optimizer/CodeGen/Target.cpp (+1-1) - (modified) lld/ELF/InputFiles.cpp (+1-1) - (modified) llvm/docs/AMDGPUUsage.rst (+575-461) - (modified) llvm/docs/ReleaseNotes.md (+3) - (modified) llvm/include/llvm/Object/ELFObjectFile.h (+1-1) - (modified) llvm/include/llvm/TargetParser/AMDGPUTargetParser.def (+62-62) - (modified) llvm/include/llvm/TargetParser/AMDGPUTargetParser.h (+48-2) - (modified) llvm/include/llvm/TargetParser/Triple.h (+92-3) - (modified) llvm/lib/Frontend/OpenMP/OMPContext.cpp (+2-2) - (modified) llvm/lib/Object/RelocationResolver.cpp (+1-1) - (modified) llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp (+2) - (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+46) - (modified) llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (+30-2) - (modified) llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (+4) - (modified) llvm/lib/Target/AMDGPU/GCNSubtarget.cpp (+41-2) - (modified) llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp (+5) - (modified) llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp (+20-12) - (modified) llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp (+1-1) - (modified) llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp (+18-2) - (modified) llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.h (+4) - (modified) llvm/lib/TargetParser/AMDGPUTargetParser.cpp (+241-11) - (modified) llvm/lib/TargetParser/TargetDataLayout.cpp (+1-1) - (modified) llvm/lib/TargetParser/Triple.cpp (+149-14) - (modified) llvm/lib/Transforms/IPO/ExpandVariadics.cpp (+2-2) - (modified) llvm/lib/Transforms/IPO/OpenMPOpt.cpp (+1-1) - (modified) llvm/lib/Transforms/Utils/CodeExtractor.cpp (+1-1) - (added) llvm/test/CodeGen/AMDGPU/amdgpu-triple.ll (+72) - (modified) llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/loop-prefetch.ll (+1-1) - (added) llvm/test/CodeGen/AMDGPU/march-amdgcn-legacy-arch-name.ll (+10) - (added) llvm/test/CodeGen/AMDGPU/target-id-from-triple.ll (+177) - (added) llvm/test/CodeGen/AMDGPU/validate-subtarget-subarch-empty-module.ll (+10) - (added) llvm/test/CodeGen/AMDGPU/validate-subtarget-subarch.ll (+47) - (modified) llvm/test/CodeGen/MIR/AMDGPU/init-whole.wave.ll (+2-2) - (added) llvm/test/Linker/Inputs/amdgpu-amdpal-no-subarch.ll (+5) - (added) llvm/test/Linker/Inputs/amdgpu-no-subarch.ll (+5) - (added) llvm/test/Linker/Inputs/amdgpu10-subarch.ll (+5) - (added) llvm/test/Linker/Inputs/amdgpu9.00-subarch.ll (+5) - (added) llvm/test/Linker/amdgpu-triple-os-mismatch.ll (+19) - (added) llvm/test/Linker/amdgpu-triple-subarch.ll (+42) - (modified) llvm/test/MC/AMDGPU/amd-amdgpu-isa-malformed-target-id.s (+1-1) - (added) llvm/test/MC/AMDGPU/amdgcn-target-directive-subarch-cpu-field.s (+58) - (modified) llvm/test/MC/AMDGPU/amdgcn-target-malformed-target-id.s (+1-1) - (modified) llvm/test/MC/AMDGPU/amdgcn_target_directive_from_eflags.s (+14-14) - (added) llvm/test/MC/AMDGPU/arch-amdgcn-legacy-arch-name.s (+7) - (modified) llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml (+1-1) - (modified) llvm/test/Object/AMDGPU/objdump.s (+1-1) - (added) llvm/test/tools/llvm-objdump/AMDGPU/arch-amdgcn-legacy-arch-name.s (+8) - (modified) llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s (+1-1) - (added) llvm/test/tools/llvm-objdump/ELF/AMDGPU/subarch-triple.s (+37) - (modified) llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll (+48-48) - (modified) llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test (+1-1) - (modified) llvm/tools/llvm-objdump/llvm-objdump.cpp (+2-2) - (modified) llvm/unittests/Object/ELFObjectFileTest.cpp (+1-1) - (modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+417) - (modified) llvm/unittests/TargetParser/TripleTest.cpp (+138-12) - (modified) llvm/utils/UpdateTestChecks/asm.py (+1) - (modified) offload/plugins-nextgen/amdgpu/src/rtl.cpp (+1-1) ``````````diff diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 3f57104d474a7..de3e0f7b563a7 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -477,7 +477,7 @@ class TargetArch<list<string> arches> : TargetSpec { } def TargetARM : TargetArch<["arm", "thumb", "armeb", "thumbeb"]>; def TargetAArch64 : TargetArch<["aarch64", "aarch64_be", "aarch64_32"]>; -def TargetAMDGPU : TargetArch<["amdgcn", "r600"]>; +def TargetAMDGPU : TargetArch<["amdgpu", "r600"]>; def TargetAnyArm : TargetArch<!listconcat(TargetARM.Arches, TargetAArch64.Arches)>; def TargetAVR : TargetArch<["avr"]>; def TargetBPF : TargetArch<["bpfel", "bpfeb"]>; @@ -512,7 +512,7 @@ def TargetMicrosoftCXXABI : TargetArch<["x86", "x86_64", "arm", "thumb", "aarch6 // environment on Windows 2. an offloading target e.g. amdgcn or nvptx with // a host target in MSVC environment on Windows. def TargetMicrosoftRecordLayout : TargetArch<["x86", "x86_64", "arm", "thumb", - "aarch64", "amdgcn", "nvptx", + "aarch64", "amdgpu", "nvptx", "nvptx64", "spirv", "spirv32", "spirv64"]> { let CustomCode = [{ Target.hasMicrosoftRecordLayout() }]; diff --git a/clang/lib/Basic/OffloadArch.cpp b/clang/lib/Basic/OffloadArch.cpp index 2a333662455e4..5d12f257f3680 100644 --- a/clang/lib/Basic/OffloadArch.cpp +++ b/clang/lib/Basic/OffloadArch.cpp @@ -173,8 +173,7 @@ llvm::Triple OffloadArchToTriple(const llvm::Triple &DefaultToolchainTriple, } if (IsAMDOffloadArch(ID)) - return llvm::Triple(llvm::Triple::amdgcn, llvm::Triple::NoSubArch, - llvm::Triple::AMD, llvm::Triple::AMDHSA); + return llvm::Triple("amdgcn-amd-amdhsa"); return {}; } diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp index ed88ae7173bad..8c01cfca8ccb4 100644 --- a/clang/lib/Basic/Targets.cpp +++ b/clang/lib/Basic/Targets.cpp @@ -434,7 +434,7 @@ std::unique_ptr<TargetInfo> AllocateTarget(const llvm::Triple &Triple, return std::make_unique<NVPTXTargetInfo>(Triple, Opts, /*TargetPointerWidth=*/64); - case llvm::Triple::amdgcn: + case llvm::Triple::amdgpu: case llvm::Triple::r600: return std::make_unique<AMDGPUTargetInfo>(Triple, Opts); diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp index 8fdb45acf381f..3eb62c9051b58 100644 --- a/clang/lib/Basic/Targets/SPIR.cpp +++ b/clang/lib/Basic/Targets/SPIR.cpp @@ -111,7 +111,7 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions &Opts, } static const AMDGPUTargetInfo - AMDGPUTI(llvm::Triple(llvm::Triple::amdgcn, llvm::Triple::NoSubArch, + AMDGPUTI(llvm::Triple(llvm::Triple::amdgpu, llvm::Triple::NoSubArch, llvm::Triple::AMD, llvm::Triple::AMDHSA), {}); diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp index 3b8149411e7c4..0dc686cbb3f99 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp @@ -2769,7 +2769,7 @@ emitTargetArchBuiltinExpr(CIRGenFunction *cgf, unsigned builtinID, // These are actually NYI, but that will be reported by emitBuiltinExpr. // At this point, we don't even know that the builtin is target-specific. return std::nullopt; - case llvm::Triple::amdgcn: + case llvm::Triple::amdgpu: return cgf->emitAMDGPUBuiltinExpr(builtinID, e); case llvm::Triple::systemz: return std::nullopt; diff --git a/clang/lib/CIR/CodeGen/CIRGenModule.cpp b/clang/lib/CIR/CodeGen/CIRGenModule.cpp index 69dfadf58aa49..796e7aaaff884 100644 --- a/clang/lib/CIR/CodeGen/CIRGenModule.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenModule.cpp @@ -310,7 +310,7 @@ const TargetCIRGenInfo &CIRGenModule::getTargetCIRGenInfo() { case llvm::Triple::nvptx64: theTargetCIRGenInfo = createNVPTXTargetCIRGenInfo(genTypes); return *theTargetCIRGenInfo; - case llvm::Triple::amdgcn: { + case llvm::Triple::amdgpu: { theTargetCIRGenInfo = createAMDGPUTargetCIRGenInfo(genTypes); return *theTargetCIRGenInfo; } diff --git a/clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp b/clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp index cccbfdde3bfdf..4061d3b2e58c7 100644 --- a/clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp +++ b/clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp @@ -48,7 +48,7 @@ createTargetLoweringInfo(LowerModule &lm) { const llvm::Triple &triple = lm.getTarget().getTriple(); switch (triple.getArch()) { - case llvm::Triple::amdgcn: + case llvm::Triple::amdgpu: return createAMDGPUTargetLoweringInfo(); case llvm::Triple::nvptx: case llvm::Triple::nvptx64: diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 475bfec6199fc..91080c2f5ec37 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -108,8 +108,8 @@ static Value *EmitTargetArchBuiltinExpr(CodeGenFunction *CGF, case llvm::Triple::ppc64: case llvm::Triple::ppc64le: return CGF->EmitPPCBuiltinExpr(BuiltinID, E); + case llvm::Triple::amdgpu: case llvm::Triple::r600: - case llvm::Triple::amdgcn: return CGF->EmitAMDGPUBuiltinExpr(BuiltinID, E); case llvm::Triple::systemz: return CGF->EmitSystemZBuiltinExpr(BuiltinID, E); diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index fec18acd46998..35fb3815fa18c 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -291,7 +291,7 @@ createTargetCodeGenInfo(CodeGenModule &CGM) { return createLanaiTargetCodeGenInfo(CGM); case llvm::Triple::r600: return createAMDGPUTargetCodeGenInfo(CGM); - case llvm::Triple::amdgcn: + case llvm::Triple::amdgpu: return createAMDGPUTargetCodeGenInfo(CGM); case llvm::Triple::sparc: return createSparcV8TargetCodeGenInfo(CGM); @@ -629,7 +629,7 @@ void CodeGenModule::createOpenMPRuntime() { switch (getTriple().getArch()) { case llvm::Triple::nvptx: case llvm::Triple::nvptx64: - case llvm::Triple::amdgcn: + case llvm::Triple::amdgpu: case llvm::Triple::spirv64: assert( getLangOpts().OpenMPIsTargetDevice && @@ -6208,7 +6208,7 @@ LangAS CodeGenModule::GetGlobalConstantAddressSpace() const { } // In address space agnostic languages, string literals are in default address -// space in AST. However, certain targets (e.g. amdgcn) request them to be +// space in AST. However, certain targets (e.g. amdgpu) request them to be // emitted in constant address space in LLVM IR. To be consistent with other // parts of AST, string literal global variables in constant address space // need to be casted to default address space before being put into address diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index 0b04a68417bbe..1d4e6ab50152c 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -941,10 +941,8 @@ static TripleSet inferOffloadToolchains(Compilation &C, for (llvm::StringRef Arch : Archs) { OffloadArch ID = StringToOffloadArch(Arch); if (ID == OffloadArch::Unknown) - ID = StringToOffloadArch(getProcessorFromTargetID( - llvm::Triple(llvm::Triple::amdgcn, llvm::Triple::NoSubArch, - llvm::Triple::AMD, llvm::Triple::AMDHSA), - Arch)); + ID = StringToOffloadArch( + getProcessorFromTargetID(llvm::Triple("amdgcn-amd-amdhsa"), Arch)); if (Kind == Action::OFK_HIP && !IsAMDOffloadArch(ID)) { C.getDriver().Diag(clang::diag::err_drv_offload_bad_gpu_arch) @@ -990,8 +988,7 @@ static TripleSet inferOffloadToolchains(Compilation &C, // Infer the default target triple if no specific architectures are given. if (Archs.empty() && Kind == Action::OFK_HIP) - Triples.insert(llvm::Triple(llvm::Triple::amdgcn, llvm::Triple::NoSubArch, - llvm::Triple::AMD, llvm::Triple::AMDHSA)); + Triples.insert(llvm::Triple("amdgcn-amd-amdhsa")); else if (Archs.empty() && Kind == Action::OFK_Cuda) { llvm::Triple::ArchType Arch = C.getDefaultToolChain().getTriple().isArch64Bit() @@ -7238,7 +7235,7 @@ const ToolChain &Driver::getToolChain(const ArgList &Args, case llvm::Triple::csky: TC = std::make_unique<toolchains::CSKYToolChain>(*this, Target, Args); break; - case llvm::Triple::amdgcn: + case llvm::Triple::amdgpu: case llvm::Triple::r600: TC = std::make_unique<toolchains::AMDGPUToolChain>(*this, Target, Args); break; diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp index 726c8a6ad229a..3f6049d83423f 100644 --- a/clang/lib/Driver/ToolChain.cpp +++ b/clang/lib/Driver/ToolChain.cpp @@ -1482,7 +1482,7 @@ std::string ToolChain::ComputeLLVMTriple(const ArgList &Args, BoundArch BA, } case llvm::Triple::aarch64_32: return getTripleString().str(); - case llvm::Triple::amdgcn: { + case llvm::Triple::amdgpu: { llvm::Triple Triple = getTriple(); tools::AMDGPU::setArchNameInTriple(getDriver(), Args, InputType, Triple); return Triple.getTriple(); diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index ba4341ed41f1a..65591a52e25fb 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -95,7 +95,7 @@ static bool useFramePointerForTargetByDefault(const llvm::opt::ArgList &Args, case llvm::Triple::sparc: case llvm::Triple::sparcel: case llvm::Triple::sparcv9: - case llvm::Triple::amdgcn: + case llvm::Triple::amdgpu: case llvm::Triple::r600: case llvm::Triple::csky: case llvm::Triple::loongarch32: @@ -817,8 +817,8 @@ std::string tools::getCPUName(const Driver &D, const ArgList &Args, case llvm::Triple::systemz: return systemz::getSystemZTargetCPU(Args, T); + case llvm::Triple::amdgpu: case llvm::Triple::r600: - case llvm::Triple::amdgcn: return getAMDGPUTargetGPU(T, Args); case llvm::Triple::wasm32: @@ -899,8 +899,8 @@ void tools::getTargetFeatures(const Driver &D, const llvm::Triple &Triple, case llvm::Triple::sparcv9: sparc::getSparcTargetFeatures(D, Triple, Args, Features); break; + case llvm::Triple::amdgpu: case llvm::Triple::r600: - case llvm::Triple::amdgcn: amdgpu::getAMDGPUTargetFeatures(D, Triple, Args, Features); break; case llvm::Triple::nvptx: diff --git a/clang/lib/Driver/ToolChains/Darwin.cpp b/clang/lib/Driver/ToolChains/Darwin.cpp index 64bc96a900f30..a729fb4fc1a4f 100644 --- a/clang/lib/Driver/ToolChains/Darwin.cpp +++ b/clang/lib/Driver/ToolChains/Darwin.cpp @@ -66,8 +66,8 @@ llvm::Triple::ArchType darwin::getArchTypeForMachOArchName(StringRef Str) { .Cases({"armv8m.base", "armv8m.main", "armv8.1m.main"}, llvm::Triple::arm) .Cases({"arm64", "arm64e"}, llvm::Triple::aarch64) .Case("arm64_32", llvm::Triple::aarch64_32) + .Cases({"amdgpu", "amdgcn"}, llvm::Triple::amdgpu) .Case("r600", llvm::Triple::r600) - .Case("amdgcn", llvm::Triple::amdgcn) .Case("nvptx", llvm::Triple::nvptx) .Case("nvptx64", llvm::Triple::nvptx64) .Case("amdil", llvm::Triple::amdil) diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp index ea4df1db38ec8..49330f7d4bd6a 100644 --- a/clang/lib/Driver/ToolChains/Flang.cpp +++ b/clang/lib/Driver/ToolChains/Flang.cpp @@ -603,9 +603,8 @@ void Flang::addTargetOptions(const ArgList &Args, ArgStringList &CmdArgs, getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false); AddAArch64TargetArgs(Args, CmdArgs); break; - + case llvm::Triple::amdgpu: case llvm::Triple::r600: - case llvm::Triple::amdgcn: getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false); AddAMDGPUTargetArgs(Args, CmdArgs, BA, DeviceOffloadKind); break; diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index b58c10145e7f3..24076d8814322 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -3067,7 +3067,7 @@ Generic_GCC::getDefaultUnwindTableLevel(const ArgList &Args) const { switch (getArch()) { case llvm::Triple::aarch64: case llvm::Triple::aarch64_be: - case llvm::Triple::amdgcn: + case llvm::Triple::amdgpu: case llvm::Triple::ppc: case llvm::Triple::ppcle: case llvm::Triple::ppc64: diff --git a/clang/lib/Sema/SemaAMDGPU.cpp b/clang/lib/Sema/SemaAMDGPU.cpp index bd9e7e7b71ed6..f1de44e3d2ed7 100644 --- a/clang/lib/Sema/SemaAMDGPU.cpp +++ b/clang/lib/Sema/SemaAMDGPU.cpp @@ -1034,7 +1034,7 @@ bool DiagnoseUnguardedBuiltins::VisitCallExpr(CallExpr *CE) { for (auto &&F : llvm::split(BInfo.getRequiredFeatures(GID), ',')) FeatureMap[F] = true; } else { - static const llvm::Triple AMDGCN(llvm::Triple::amdgcn, + static const llvm::Triple AMDGCN(llvm::Triple::amdgpu, llvm::Triple::NoSubArch, llvm::Triple::AMD, llvm::Triple::AMDHSA); llvm::AMDGPU::fillAMDGPUFeatureMap(CurrentGFXIP.back().second, AMDGCN, diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 2bbd880c0e068..df5e6586bc1b0 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -2242,7 +2242,7 @@ bool Sema::CheckTSBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, case llvm::Triple::ppc64: case llvm::Triple::ppc64le: return PPC().CheckPPCBuiltinFunctionCall(TI, BuiltinID, TheCall); - case llvm::Triple::amdgcn: + case llvm::Triple::amdgpu: return AMDGPU().CheckAMDGCNBuiltinFunctionCall(BuiltinID, TheCall); case llvm::Triple::riscv32: case llvm::Triple::riscv64: @@ -3088,7 +3088,7 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, if (CheckBuiltinTargetInSupported( *this, TheCall, {llvm::Triple::x86_64, llvm::Triple::arm, llvm::Triple::thumb, - llvm::Triple::aarch64, llvm::Triple::amdgcn})) + llvm::Triple::aarch64, llvm::Triple::amdgpu})) return ExprError(); break; @@ -3107,7 +3107,7 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, if (CheckBuiltinTargetInSupported( *this, TheCall, {llvm::Triple::x86, llvm::Triple::x86_64, llvm::Triple::arm, - llvm::Triple::thumb, llvm::Triple::aarch64, llvm::Triple::amdgcn, + llvm::Triple::thumb, llvm::Triple::aarch64, llvm::Triple::amdgpu, llvm::Triple::ppc, llvm::Triple::ppc64, llvm::Triple::ppcle, llvm::Triple::ppc64le})) return ExprError(); diff --git a/clang/test/Driver/amdgpu-toolchain.c b/clang/test/Driver/amdgpu-toolchain.c index 135129b739603..78b76aa8bc8c5 100644 --- a/clang/test/Driver/amdgpu-toolchain.c +++ b/clang/test/Driver/amdgpu-toolchain.c @@ -1,5 +1,9 @@ // RUN: %clang -### --target=amdgcn--amdhsa -x assembler -mcpu=kaveri %s 2>&1 | FileCheck -check-prefix=AS_LINK %s // RUN: %clang -### -g --target=amdgcn--amdhsa -mcpu=kaveri -nogpulib %s 2>&1 | FileCheck -check-prefix=DWARF_VER %s + +// RUN: %clang -### --target=amdgpu7--amdhsa -x assembler -mcpu=kaveri %s 2>&1 | FileCheck -check-prefix=AS_LINK %s +// RUN: %clang -### -g --target=amdgpu7--amdhsa -mcpu=kaveri -nogpulib %s 2>&1 | FileCheck -check-prefix=DWARF_VER %s + // RUN: %clang -### --target=amdgcn-amd-amdpal -x assembler -mcpu=kaveri %s 2>&1 | FileCheck -check-prefix=AS_LINK %s // RUN: %clang -### -g --target=amdgcn-amd-amdpal -mcpu=kaveri %s 2>&1 | FileCheck -check-prefix=DWARF_VER %s // RUN: %clang -### --target=amdgcn-mesa-mesa3d -x assembler -mcpu=kaveri %s 2>&1 | FileCheck -check-prefix=AS_LINK %s @@ -29,6 +33,10 @@ // RUN: %clang -### --target=amdgcn-amd-amdhsa -mcpu=gfx90a:xnack+:sramecc- -nogpulib \ // RUN: -L. -fconvergent-functions %s 2>&1 | FileCheck -check-prefix=MCPU %s + +// RUN: %clang -### --target=amdgpu9.0a-amd-amdhsa -mcpu=gfx90a:xnack+:sramecc- -nogpulib \ +// RUN: -L. -fconvergent-functions %s 2>&1 | FileCheck -check-prefix=MCPU %s + // MCPU: ld.lld{{.*}}"-plugin-opt=mcpu=gfx90a"{{.*}}"-plugin-opt=-mattr=+xnack,-sramecc"{{.*}} // RUN: %clang -### --target=amdgcn-amd-amdhsa -mcpu=gfx906 -nogpulib \ diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp index a4a67eed7d47f..75e92861ef4f7 100644 --- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp +++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp @@ -632,7 +632,7 @@ Expected<StringRef> linkDevice(ArrayRef<StringRef> InputFiles, switch (Triple.getArch()) { case Triple::nvptx: case Triple::nvptx64: - case Triple::amdgcn: + case Triple::amdgpu: case Triple::x86: case Triple::x86_64: case Triple::aarch64: diff --git a/flang/include/flang/Tools/TargetSetup.h b/flang/include/flang/Tools/TargetSetup.h index 002e82aa72484..3fc08ec5ae870 100644 --- a/flang/include/flang/Tools/TargetSetup.h +++ b/flang/include/flang/Tools/TargetSetup.h @@ -47,7 +47,7 @@ namespace Fortran::tools { } switch (targetTriple.getArch()) { - case llvm::Triple::ArchType::amdgcn: + case llvm::Triple::ArchType::amdgpu: case llvm::Triple::ArchType::x86_64: break; default: diff --git a/flang/lib/Optimizer/CodeGen/Target.cpp b/flang/lib/Optimizer/CodeGen/Target.cpp index 45311850e38df..2042b8b0c06fe 100644 --- a/flang/lib/Optimizer/CodeGen/Target.cpp +++ b/flang/lib/Optimizer/CodeGen/Target.cpp @@ -1950,7 +1950,7 @@ std::unique_ptr<fir::CodeGenSpecifics> fir::CodeGenSpecifics::get( return std::make_unique<TargetRISCV64>(ctx, std::move(trp), std::move(kindMap), targetCPU, targetFeatures, targetABI, dl); - case llvm::Triple::ArchType::amdgcn: + case llvm::Triple::ArchType::amdgpu: return std::make_unique<TargetAMDGPU>(ctx, std::move(trp), std::move(kindMap), targetCPU, targetFeatures, targetABI, dl); diff --git a/lld/ELF/InputFiles.cpp b/lld/ELF/InputFiles.cpp index 2f544f0fe0958..fede7cbbdd3a8 100644 --- a/lld/ELF/InputFiles.cpp +++ b/lld/ELF/InputFiles.cpp @@ -1744,7 +1744,7 @@ static uint16_t getBitcodeMachineKind(Ctx &ctx, StringRef path, case Triple::aarch64: case Triple::aarch64_be: return EM_AARCH64; - case Triple::amdgcn: + case Triple::amdgpu: case Triple::r600: return EM_AMDGPU; case Triple::arm: diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index 2b522395ee892..f78ffd295ecac 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -49,8 +49,10 @@ LLVM Target Triples -------------- -Use the Clang option ``--target=<Architecture>-<Vendor>-<OS>-<Environment>`` -to specify the target triple: +Use the Clang option ``--target=<Architecture><SubArch>-<Vendor>-<OS>-<Environment>`` +to specify the target triple. Historically, the single top-level +``amdgcn`` architecture was used for all devices and specific devices +by the subtarget. Currently a subarch should be specified. .. table:: AMDGPU Architectures :name: amdgpu-architecture-table @@ -59,7 +61,8 @@ to specify the target triple: Architecture Description ============ ============================================================== ``r600`` AMD GPUs HD2XXX-HD6XXX for graphics and compute shaders. - ``amdgcn`` AMD GPUs GCN GFX6 onwards for graphics and compute shaders. + ``amdgpu`` AMD GPUs GCN GFX6 onwards for graphics and compute shaders. + ``amdgcn`` Legacy alias for ``amdgpu``. ============ ============================================================== .. table:: AMDGPU Vendors @@ -105,6 +108,113 @@ to specify the target triple: *<empty>* Default. ============ ============================================================== +.. _amdgpu-subarch-compatibility: + +Subarchitecture Compatibility +----------------------------- + +For the ``amdgpu`` architecture the ISA version is encoded in t... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/206480 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
