================
@@ -4551,6 +4551,66 @@ static bool interp__builtin_ia32_vpdp(InterpState &S,
CodePtr OpPC,
return true;
}
+// Bit Matrix Multiply and Accumulate (AVX512BMM). Each 256-bit lane holds a
+// 16x16 bit matrix as 16 x i16 elements; element i is row i and bit j of that
+// element is entry [i][j]. The accumulator (third argument, src1 in the AMD
+// ISA) provides the initial value of each result bit, into which the
bit-matrix
+// product of the first two arguments (src2 * src3) is reduced with OR
(vbmacor)
+// or XOR (vbmacxor):
+// for i in 0..15, j in 0..15:
+// bit = C[16*i+j]
+// for k in 0..15: bit OP= A[16*i+k] & B[16*k+j]
+// dest[16*i+j] = bit
+static bool interp__builtin_ia32_bmac(InterpState &S, CodePtr OpPC,
+ const CallExpr *Call, bool IsXor) {
+ assert(Call->getNumArgs() == 3);
+ const Pointer &C = S.Stk.pop<Pointer>();
+ const Pointer &B = S.Stk.pop<Pointer>();
+ const Pointer &A = S.Stk.pop<Pointer>();
+ const Pointer &Dst = S.Stk.peek<Pointer>();
+
+ unsigned NumElems = A.getNumElems();
+ assert(NumElems % 16 == 0 && "BMM operates on 256-bit lanes of 16 x i16");
+ QualType ElemQT = getElemType(A);
+ OptPrimType ElemT = S.getContext().classify(ElemQT);
+ bool DstUnsigned = ElemQT->isUnsignedIntegerOrEnumerationType();
+
+ // Lanes are always 16-bit; gather them so the reduction below is untyped.
+ SmallVector<uint16_t> AVals(NumElems), BVals(NumElems), Acc(NumElems);
----------------
ganeshgit wrote:
No, I intend to mention the lane shape by "16 x i16" not the element
signedness. It represents 16 bits of data, nothing more. Should I reword that
to "16 x 16" instead?
https://github.com/llvm/llvm-project/pull/182556
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