YonahGoldberg wrote: > HINT_STCPH: Ensures that the memory write effect of the next instruction > occurs before any other effects from other threads.
Could you just confirm this is a performance hint? Should we interpret this that sequencing the next instruction before other memory accesses from other threads yields a performance benefit? And that programs cannot depend on the ordering for correctness. `mem.cache_hint` needs to be safe to drop. > Given that the hints described above are not strictly cache hints, would you > be open to renaming the cache hint to something more general, such as > mem.access_hint? Sure, that seems reasonable. Do you mind if I rename everything at once in a follow-up PR after https://github.com/llvm/llvm-project/pull/204067 goes in? I'd prefer discussion on the naming not block it. > I also noticed that atomics are not yet supported in your PR at the moment. I > just wanted to check whether this is something you are planning to add? Yup, this will go in a follow-up, as well as ISEL support for better retention during legalization. This latter point will benefit both of us. Do you mind reviewing my PR? I'm trying to push it along and your encouragement would be valuable :) https://github.com/llvm/llvm-project/pull/198316 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
