https://github.com/ChunyuLiao created https://github.com/llvm/llvm-project/pull/206868
spec: https://github.com/riscv/riscv-isa-manual/pull/3192 >From 10783c43b968acebf2adb097553f4c64bb7cdd6c Mon Sep 17 00:00:00 2001 From: Liao Chunyu <[email protected]> Date: Wed, 1 Jul 2026 01:30:46 +0000 Subject: [PATCH] [RISCV] Update Smpmpmt extension to 1.0 and remove experimental spec: https://github.com/riscv/riscv-isa-manual/pull/3192 --- clang/test/Driver/print-supported-extensions-riscv.c | 2 +- clang/test/Preprocessor/riscv-target-features.c | 10 +++++----- llvm/docs/RISCVUsage.rst | 3 --- llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +- llvm/test/CodeGen/RISCV/attributes.ll | 8 ++++---- llvm/test/CodeGen/RISCV/features-info.ll | 2 +- llvm/test/MC/RISCV/attribute-arch.s | 4 ++-- llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 2 +- 8 files changed, 15 insertions(+), 18 deletions(-) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 34c651891538d..4e4db8b7f7c9b 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -135,6 +135,7 @@ // CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection) // CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode) // CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode) +// CHECK-NEXT: smpmpmt 1.0 'Smpmpmt' (PMP-based Memory Types Extension) // CHECK-NEXT: smrnmi 1.0 'Smrnmi' (Resumable Non-Maskable Interrupts) // CHECK-NEXT: smstateen 1.0 'Smstateen' (Machine-mode view of the state-enable extension) // CHECK-NEXT: ssaia 1.0 'Ssaia' (Advanced Interrupt Architecture Supervisor Level) @@ -268,7 +269,6 @@ // CHECK-NEXT: zvvmtls 0.1 'Zvvmtls' (Matrix Tile Load/Store) // CHECK-NEXT: zvvmttls 0.1 'Zvvmttls' (Transposing Matrix Tile Load/Store) // CHECK-NEXT: zvzip 0.1 'Zvzip' (Vector Reordering Structured Data) -// CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension) // CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) // CHECK-NEXT: xqccmt 0.1 'Xqccmt' (Qualcomm 16-bit Table Jump) // CHECK-NEXT: xsfmclic 0.1 'XSfmclic' (SiFive CLIC Machine-mode CSRs) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 28031814da16a..aa5a6292147ca 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1387,13 +1387,13 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s // CHECK-SMEPMP-EXT: __riscv_smepmp 1000000{{$}} -// RUN: %clang --target=riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32ismpmpmt0p6 -x c -E -dM %s \ +// RUN: %clang --target=riscv32 \ +// RUN: -march=rv32ismpmpmt1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SMPMPMT %s -// RUN: %clang --target=riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64ismpmpmt0p6 -x c -E -dM %s \ +// RUN: %clang --target=riscv64 \ +// RUN: -march=rv64ismpmpmt1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SMPMPMT %s -// CHECK-SMPMPMT: __riscv_smpmpmt 6000{{$}} +// CHECK-SMPMPMT: __riscv_smpmpmt 1000000{{$}} // RUN: %clang --target=riscv32 \ // RUN: -march=rv32ismrnmi1p0 -E -dM %s \ diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 548f25ac2e596..7c5361b899964 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -361,9 +361,6 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zvqwdota8i``, ``experimental-zvqwdota16i``, ``experimental-zvfwdota16bf``, ``experimental-zvfqwdota8f`` LLVM implements the `0.2 draft specification <https://github.com/aswaterman/riscv-misc/blob/main/isa/ldot-bdot/ldot-bdot.adoc>`__. -``experimental-smpmpmt`` - LLVM implements the `0.6 draft specification <https://github.com/riscv/riscv-isa-manual/blob/smpmpmt/src/smpmpmt.adoc>`__. - ``experimental-zvabd`` LLVM implements the `0.7 draft specification <https://github.com/riscv/integer-vector-absolute-difference/releases/tag/v0.7>`__. diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 361be64352499..015915e3ba112 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1079,7 +1079,7 @@ def FeatureStdExtSmepmp : RISCVExtension<1, 0, "Enhanced Physical Memory Protection">; def FeatureStdExtSmpmpmt - : RISCVExperimentalExtension<0, 6, "PMP-based Memory Types Extension">; + : RISCVExtension<1, 0, "PMP-based Memory Types Extension">; def FeatureStdExtSmrnmi : RISCVExtension<1, 0, "Resumable Non-Maskable Interrupts">; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 26ffd8bb4ec89..fadadfdd48077 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -129,7 +129,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s ; RUN: llc -mtriple=riscv32 -mattr=+smcntrpmf %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCNTRPMF %s ; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-smpmpmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SMPMPMT %s +; RUN: llc -mtriple=riscv32 -mattr=+smpmpmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SMPMPMT %s ; RUN: llc -mtriple=riscv32 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV32SMRNMI %s ; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFA %s @@ -295,7 +295,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s ; RUN: llc -mtriple=riscv64 -mattr=+smcntrpmf %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCNTRPMF %s ; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-smpmpmt %s -o - | FileCheck --check-prefixes=CHECK,RV64SMPMPMT %s +; RUN: llc -mtriple=riscv64 -mattr=+smpmpmt %s -o - | FileCheck --check-prefixes=CHECK,RV64SMPMPMT %s ; RUN: llc -mtriple=riscv64 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV64SMRNMI %s ; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFA %s @@ -470,7 +470,7 @@ ; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0" ; RV32SMCNTRPMF: .attribute 5, "rv32i2p1_smcntrpmf1p0" ; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0" -; RV32SMPMPMT: .attribute 5, "rv32i2p1_smpmpmt0p6" +; RV32SMPMPMT: .attribute 5, "rv32i2p1_smpmpmt1p0" ; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0" ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0" ; RV32ZVFBFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfa0p1_zvl32b1p0" @@ -633,7 +633,7 @@ ; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0" ; RV64SMCNTRPMF: .attribute 5, "rv64i2p1_smcntrpmf1p0" ; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0" -; RV64SMPMPMT: .attribute 5, "rv64i2p1_smpmpmt0p6" +; RV64SMPMPMT: .attribute 5, "rv64i2p1_smpmpmt1p0" ; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0" ; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0" ; RV64ZVFBFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfa0p1_zvl32b1p0" diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 8abe64b8ecda4..14dde847fedbd 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -24,7 +24,6 @@ ; CHECK-NEXT: experimental - Experimental intrinsics. ; CHECK-NEXT: experimental-p - 'P' ('Base P' (Packed SIMD)). ; CHECK-NEXT: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile. -; CHECK-NEXT: experimental-smpmpmt - 'Smpmpmt' (PMP-based Memory Types Extension). ; CHECK-NEXT: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses). ; CHECK-NEXT: experimental-xqccmt - 'Xqccmt' (Qualcomm 16-bit Table Jump). ; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs). @@ -164,6 +163,7 @@ ; CHECK-NEXT: smepmp - 'Smepmp' (Enhanced Physical Memory Protection). ; CHECK-NEXT: smmpm - 'Smmpm' (Machine-level Pointer Masking for M-mode). ; CHECK-NEXT: smnpm - 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode). +; CHECK-NEXT: smpmpmt - 'Smpmpmt' (PMP-based Memory Types Extension). ; CHECK-NEXT: smrnmi - 'Smrnmi' (Resumable Non-Maskable Interrupts). ; CHECK-NEXT: smstateen - 'Smstateen' (Machine-mode view of the state-enable extension). ; CHECK-NEXT: ssaia - 'Ssaia' (Advanced Interrupt Architecture Supervisor Level). diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 367ec6f04d953..d06f36ad0c8ea 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -357,8 +357,8 @@ .attribute arch, "rv32i_smepmp1p0" # CHECK: attribute 5, "rv32i2p1_smepmp1p0" -.attribute arch, "rv32i_smpmpmt0p6" -# CHECK: attribute 5, "rv32i2p1_smpmpmt0p6" +.attribute arch, "rv32i_smpmpmt1p0" +# CHECK: attribute 5, "rv32i2p1_smpmpmt1p0" .attribute arch, "rv32i_smrnmi1p0" # CHECK: attribute 5, "rv32i2p1_smrnmi1p0" diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 851685d5f68d1..587c1d497572c 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1271,6 +1271,7 @@ R"(All available -march extensions for RISC-V smepmp 1.0 smmpm 1.0 smnpm 1.0 + smpmpmt 1.0 smrnmi 1.0 smstateen 1.0 ssaia 1.0 @@ -1404,7 +1405,6 @@ Experimental extensions zvvmtls 0.1 zvvmttls 0.1 zvzip 0.1 - smpmpmt 0.6 svukte 0.3 xqccmt 0.1 xsfmclic 0.1 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
