https://github.com/w2yehia updated https://github.com/llvm/llvm-project/pull/206786
>From 1141f97c89ee851c61c76205e52a601a8e8ab464 Mon Sep 17 00:00:00 2001 From: Wael Yehia <[email protected]> Date: Mon, 29 Jun 2026 17:28:53 +0000 Subject: [PATCH 1/3] proto 1 by bob add TODO in Sema/SemaPPC.cpp add Sema test add tests and remove isel from runtime-detected features since it's always available remove cmpb and fprnd from runtime-detected features since it's always available fix codegen for no-FEATURE documentation priority of features in powerXX should be between cpu=powerXX and cpu=power(XX+1) clang-format --- clang/include/clang/Basic/AttrDocs.td | 8 +- .../clang/Basic/DiagnosticSemaKinds.td | 4 + clang/include/clang/Basic/TargetInfo.h | 12 ++ clang/lib/AST/ASTContext.cpp | 7 +- clang/lib/Basic/Targets/PPC.cpp | 132 +++++++++++++++++- clang/lib/Basic/Targets/PPC.h | 11 ++ clang/lib/CodeGen/CodeGenFunction.cpp | 55 ++++++-- clang/lib/CodeGen/Targets/PPC.cpp | 28 +++- clang/lib/Sema/SemaPPC.cpp | 55 +++++++- .../CodeGen/PowerPC/attr-target-clones-mma.c | 16 +++ .../test/CodeGen/PowerPC/attr-target-clones.c | 89 ++++++++++++ clang/test/Sema/PowerPC/attr-target-clones.c | 99 ++++++++++++- clang/test/Sema/attr-target.c | 2 +- 13 files changed, 482 insertions(+), 36 deletions(-) create mode 100644 clang/test/CodeGen/PowerPC/attr-target-clones-mma.c diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index dab778d4047aa..5e543cb7ab51e 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -3407,8 +3407,12 @@ For backward compatibility with earlier Clang releases, a function alias with an ``.ifunc`` suffix is also emitted. The ``.ifunc`` suffixed symbol is a deprecated feature and support for it may be removed in the future. -For PowerPC targets, ``target_clones`` is supported on AIX only. Only CPU -(specified as ``cpu=CPU``) and ``default`` options are allowed. IFUNC is supported +For PowerPC targets, ``target_clones`` is supported on AIX only. The attribute +contains comma-separated strings of one of: +(a) ``default``, (b) ``cpu=CPU``, (c) ``FEATURE`` or ``no-FEATURE``. +The minimum CPU supported is ``pwr7`` (long spelling such as ``power7`` is accepted). +The list of target features is a subset of what's allowed on ``target``, limited +to what is detectable at runtime using ``__builtin_cpu_supports``. IFUNC is supported on AIX in Clang, so dispatch is implemented similar to other targets using IFUNC. An FMV function that is only declared in a translation unit is treated as a non-FMV. The resolver and the function clones are given internal linkage. diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index a3b575b7ee63a..13077b44c5c8a 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -11516,6 +11516,10 @@ def err_ppc_invalid_test_data_class_type : Error< "expected a 'float', 'double' or '__float128' for the first argument">; def err_ppc_invalid_arg_type : Error< "argument %0 must be of type %1">; +def err_ppc_feature_no_runtime_detection : Error< + "feature '%0' cannot be used with 'target_clones' because it has no " + "runtime detection; use 'target' attribute instead">; + def err_x86_builtin_invalid_rounding : Error< "invalid rounding argument">; def err_x86_builtin_invalid_scale : Error< diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index cc226403877e2..4b4154fdc22e2 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -1467,6 +1467,18 @@ class TargetInfo : public TransferrableTargetInfo, return true; } + /// Validate feature name for target_clones attribute (subset with runtime + /// detection) Default implementation delegates to isValidFeatureName + virtual bool isValidClonesFeatureName(StringRef Feature) const { + return isValidFeatureName(Feature); + } + + /// Get __builtin_cpu_supports() argument for a feature + /// Returns empty string if feature has no runtime detection + virtual StringRef getBuiltinCpuSupportsName(StringRef Feature) const { + return ""; + } + /// Returns true if feature has an impact on target code /// generation. virtual bool doesFeatureAffectCodeGen(StringRef Feature) const { diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index abf0cd5e18c2b..b1c2d57daf22f 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -15355,8 +15355,11 @@ void ASTContext::getFunctionFeatureMap(llvm::StringMap<bool> &FeatureMap, StringRef VersionStr = TC->getFeatureStr(GD.getMultiVersionIndex()); if (VersionStr.starts_with("cpu=")) TargetCPU = VersionStr.drop_front(sizeof("cpu=") - 1); - else - assert(VersionStr == "default"); + else if (VersionStr != "default") { + // Handle feature strings + ParsedTargetAttr ParsedAttr = Target->parseTargetAttr(VersionStr); + Features = ParsedAttr.Features; + } Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU, Features); } else { std::vector<std::string> Features; diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp index c9a41df806aff..4b1e78df86f67 100644 --- a/clang/lib/Basic/Targets/PPC.cpp +++ b/clang/lib/Basic/Targets/PPC.cpp @@ -719,17 +719,54 @@ llvm::APInt PPCTargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const { return llvm::APInt(32, 0); assert(Features.size() == 1 && "one feature/cpu per clone on PowerPC"); ParsedTargetAttr ParsedAttr = parseTargetAttr(Features[0]); + + // Priority scheme: Features requiring POWERXX are higher than cpu=pwrXX + // but lower than cpu=pwr(XX+1). This ensures proper version selection. + // Example: mma (POWER10 feature) > cpu=pwr10 > power9-vector (POWER9 feature) + if (!ParsedAttr.CPU.empty()) { int Priority = llvm::StringSwitch<int>(ParsedAttr.CPU) - .Case("pwr7", 1) - .Case("pwr8", 2) - .Case("pwr9", 3) - .Case("pwr10", 4) - .Case("pwr11", 5) + .Case("pwr7", 100) + .Case("pwr8", 200) + .Case("pwr9", 300) + .Case("pwr10", 400) + .Case("pwr11", 500) + .Default(0); + return llvm::APInt(32, Priority); + } + + // Feature strings: priority between cpu=pwrN and cpu=pwr(N+1) + if (!ParsedAttr.Features.empty()) { + StringRef Feature = ParsedAttr.Features[0]; + // Remove leading '+' or '-' + if (Feature.starts_with("+") || Feature.starts_with("-")) + Feature = Feature.drop_front(1); + + int Priority = llvm::StringSwitch<int>(Feature) + // POWER10 features (between pwr10=400 and pwr11=500) + .Case("mma", 419) + .Case("paired-vector-memops", 418) + .Case("pcrel", 417) + .Case("power10-vector", 416) + .Case("prefixed", 415) + // POWER9 features (between pwr9=300 and pwr10=400) + .Case("float128", 312) + .Case("power9-vector", 311) + // POWER8 features (between pwr8=200 and pwr9=300) + .Case("crypto", 214) + .Case("direct-move", 213) + .Case("power8-vector", 212) + .Case("htm", 211) + // POWER7 features (between pwr7=100 and pwr8=200) + .Case("popcntd", 112) + .Case("vsx", 111) + // Base features: 50-99 (below pwr7=100) + .Case("altivec", 50) .Default(0); + return llvm::APInt(32, Priority); } - assert(false && "unimplemented"); + return llvm::APInt(32, 0); } @@ -822,6 +859,89 @@ void PPCTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { llvm::PPC::fillValidCPUList(Values); } +bool PPCTargetInfo::isValidFeatureName(StringRef Name) const { + // All 28 PPC features valid for target attribute + return llvm::StringSwitch<bool>(Name) + // Features with runtime detection (valid for target_clones) + .Case("altivec", true) + .Case("htm", true) + .Case("mma", true) + .Case("vsx", true) + .Case("crypto", true) + .Case("direct-move", true) + .Case("float128", true) + .Case("paired-vector-memops", true) + .Case("pcrel", true) + .Case("popcntd", true) + .Case("power8-vector", true) + .Case("power9-vector", true) + .Case("power10-vector", true) + .Case("prefixed", true) + // Features without runtime checks (NOT valid for target_clones) + .Case("aix-shared-lib-tls-model-opt", true) + .Case("aix-small-local-dynamic-tls", true) + .Case("aix-small-local-exec-tls", true) + .Case("cmpb", true) + .Case("crbits", true) + .Case("fprnd", true) + .Case("invariant-function-descriptors", true) + .Case("isel", true) + .Case("longcall", true) + .Case("mfcrf", true) + .Case("mfocrf", true) + .Case("privileged", true) + .Case("rop-protect", true) + .Case("secure-plt", true) + .Default(false); +} + +bool PPCTargetInfo::isValidClonesFeatureName(StringRef Name) const { + // Only 14 features with runtime detection are valid for target_clones + return llvm::StringSwitch<bool>(Name) + // Direct mappings (4 features) + .Case("altivec", true) + .Case("htm", true) + .Case("mma", true) + .Case("vsx", true) + // ISA level mappings (10 features) + .Case("crypto", true) + .Case("direct-move", true) + .Case("float128", true) + .Case("paired-vector-memops", true) + .Case("pcrel", true) + .Case("popcntd", true) + .Case("power8-vector", true) + .Case("power9-vector", true) + .Case("power10-vector", true) + .Case("prefixed", true) + .Default(false); +} + +StringRef +PPCTargetInfo::getBuiltinCpuSupportsName(StringRef FeatureName) const { + // Map feature names to __builtin_cpu_supports() strings + // Only returns non-empty for features with runtime detection + return llvm::StringSwitch<StringRef>(FeatureName) + // Direct mappings (4 features) + .Case("altivec", "altivec") + .Case("htm", "htm") + .Case("mma", "mma") + .Case("vsx", "vsx") + // ISA level mappings (10 features) + .Case("popcntd", "arch_2_06") + .Case("crypto", "arch_2_07") + .Case("direct-move", "arch_2_07") + .Case("power8-vector", "arch_2_07") + .Case("float128", "arch_3_00") + .Case("power9-vector", "arch_3_00") + .Case("paired-vector-memops", "arch_3_1") + .Case("pcrel", "arch_3_1") + .Case("power10-vector", "arch_3_1") + .Case("prefixed", "arch_3_1") + // Features without runtime checks return empty string + .Default(""); +} + void PPCTargetInfo::adjust(DiagnosticsEngine &Diags, LangOptions &Opts, const TargetInfo *Aux) { if (HasAltivec) diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h index a9f49aa3aebe1..fe9ccbd754ace 100644 --- a/clang/lib/Basic/Targets/PPC.h +++ b/clang/lib/Basic/Targets/PPC.h @@ -98,6 +98,17 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { bool isValidCPUName(StringRef Name) const override; void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; + // Validate feature name for target attribute (all 28 features) + bool isValidFeatureName(StringRef Name) const override; + + // Validate feature name for target_clones (only 17 features with runtime + // detection) + bool isValidClonesFeatureName(StringRef Name) const; + + // Get __builtin_cpu_supports() argument for a feature (returns empty string + // if no runtime check) + StringRef getBuiltinCpuSupportsName(StringRef FeatureName) const; + bool setCPU(const std::string &Name) override { bool CPUKnown = isValidCPUName(Name); if (CPUKnown) { diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp index b920266b59808..535bd93b3e4de 100644 --- a/clang/lib/CodeGen/CodeGenFunction.cpp +++ b/clang/lib/CodeGen/CodeGenFunction.cpp @@ -3133,18 +3133,49 @@ void CodeGenFunction::EmitPPCAIXMultiVersionResolver( assert(RO.Features.size() == 1 && "for now one feature requirement per version"); - assert(RO.Features[0].starts_with("cpu=")); - StringRef CPU = RO.Features[0].split("=").second.trim(); - StringRef Feature = llvm::StringSwitch<StringRef>(CPU) - .Case("pwr7", "arch_2_06") - .Case("pwr8", "arch_2_07") - .Case("pwr9", "arch_3_00") - .Case("pwr10", "arch_3_1") - .Case("pwr11", "arch_3_1") - .Default("error"); - - llvm::Value *Condition = EmitPPCBuiltinCpu( - Builtin::BI__builtin_cpu_supports, Builder.getInt1Ty(), Feature); + StringRef FeatureStr = RO.Features[0]; + StringRef BuiltinCpuSupportsArg; + bool IsNegated = false; + + if (FeatureStr.starts_with("cpu=")) { + // CPU specification - map to ISA level + StringRef CPU = FeatureStr.split("=").second.trim(); + BuiltinCpuSupportsArg = llvm::StringSwitch<StringRef>(CPU) + .Case("pwr7", "arch_2_06") + .Case("pwr8", "arch_2_07") + .Case("pwr9", "arch_3_00") + .Case("pwr10", "arch_3_1") + .Case("pwr11", "arch_3_1") + .Default("error"); + } else { + // Feature string - check for "no-" negation prefix + StringRef BaseFeature = FeatureStr; + + // Feature strings arrive here already normalized: + // - Positive features: just the name (e.g., "altivec") + // - Negated features: "no-" prefix (e.g., "no-altivec") + if (BaseFeature.starts_with("no-")) { + IsNegated = true; + BaseFeature = BaseFeature.drop_front(3); + } + + BuiltinCpuSupportsArg = + getTarget().getBuiltinCpuSupportsName(BaseFeature); + + // All features in target_clones must have runtime detection + assert(!BuiltinCpuSupportsArg.empty() && + "feature without runtime detection should have been rejected in " + "Sema"); + } + + llvm::Value *Condition = + EmitPPCBuiltinCpu(Builtin::BI__builtin_cpu_supports, + Builder.getInt1Ty(), BuiltinCpuSupportsArg); + + // Negate the condition if this is a negated feature + if (IsNegated) { + Condition = Builder.CreateNot(Condition, "neg"); + } llvm::BasicBlock *ThenBlock = createBasicBlock("if.version", Resolver); CurBlock = createBasicBlock("if.else", Resolver); diff --git a/clang/lib/CodeGen/Targets/PPC.cpp b/clang/lib/CodeGen/Targets/PPC.cpp index ab069bfbd1b51..f0c1237f8588c 100644 --- a/clang/lib/CodeGen/Targets/PPC.cpp +++ b/clang/lib/CodeGen/Targets/PPC.cpp @@ -157,7 +157,33 @@ void AIXABIInfo::appendAttributeMangling(StringRef AttrStr, return; } - assert(0 && "specifying target features on an FMV is unsupported on AIX"); + // Handle feature strings + if (!Info.Features.empty()) { + assert(Info.Features.size() == 1 && "one feature per version for now"); + StringRef Feature = Info.Features[0]; + std::string MangledFeature; + + // Handle negation prefix "no-" specially - convert to "no_" + if (Feature.starts_with("no-")) { + MangledFeature = "no_"; + Feature = Feature.drop_front(3); + } else if (Feature.starts_with("+")) { + // Remove leading '+' for positive features + Feature = Feature.drop_front(1); + } else if (Feature.starts_with("-")) { + // Leading '-' means negation, convert to "no_" + MangledFeature = "no_"; + Feature = Feature.drop_front(1); + } + + // Append the base feature name and replace hyphens with underscores + MangledFeature += Feature.str(); + std::replace(MangledFeature.begin(), MangledFeature.end(), '-', '_'); + Out << "." << MangledFeature; + return; + } + + llvm_unreachable("Invalid target_clones parameter"); } class AIXTargetCodeGenInfo : public TargetCodeGenInfo { diff --git a/clang/lib/Sema/SemaPPC.cpp b/clang/lib/Sema/SemaPPC.cpp index 8a594fc86dea6..be76bac5de6c8 100644 --- a/clang/lib/Sema/SemaPPC.cpp +++ b/clang/lib/Sema/SemaPPC.cpp @@ -618,21 +618,32 @@ bool SemaPPC::checkTargetClonesAttr(const SmallVectorImpl<StringRef> &Params, const StringRef Param = Params[I].trim(); const SourceLocation &Loc = Locs[I]; - if (Param.empty() || Param.ends_with(',')) - return Diag(Loc, diag::warn_unsupported_target_attribute) - << Unsupported << None << "" << TargetClones; - if (Param.contains(',')) HasComma = true; StringRef LHS; StringRef RHS = Param; + // TODO: simplify the logic to diagnose empty strings + bool checkTrailingEmpty = false; do { std::tie(LHS, RHS) = RHS.split(','); LHS = LHS.trim(); + + // After processing last non-empty item, check if we need to process + // trailing empty + if (RHS.empty() && !LHS.empty() && Param.ends_with(',')) { + checkTrailingEmpty = true; + } + const SourceLocation &CurLoc = Loc.getLocWithOffset(LHS.data() - Param.data()); + // Check for empty string (from trailing comma, leading comma, or ",,") + if (LHS.empty()) { + return Diag(CurLoc, diag::warn_unsupported_target_attribute) + << Unknown << None << "" << TargetClones; + } + if (LHS.starts_with("cpu=")) { StringRef CPUStr = LHS.drop_front(sizeof("cpu=") - 1); if (!TargetInfo.isValidCPUName(CPUStr)) @@ -644,9 +655,30 @@ bool SemaPPC::checkTargetClonesAttr(const SmallVectorImpl<StringRef> &Params, } else if (LHS == "default") { HasDefault = true; } else { - // it's a feature string, but not supported yet. - return Diag(CurLoc, diag::warn_unsupported_target_attribute) - << Unsupported << None << LHS << TargetClones; + // Handle feature strings + StringRef FeatureName = LHS; + bool IsNegated = false; + + // Check for negation prefix + if (FeatureName.starts_with("no-")) { + IsNegated = true; + FeatureName = FeatureName.drop_front(3); + } + + // First check if it's a valid feature name at all + if (!TargetInfo.isValidFeatureName(FeatureName)) { + return Diag(CurLoc, diag::warn_unsupported_target_attribute) + << Unknown << None << LHS << TargetClones; + } + + // Check if feature is valid for target_clones (has runtime detection) + // Use virtual method that defaults to isValidFeatureName for non-PPC + // targets + if (!TargetInfo.isValidClonesFeatureName(FeatureName)) { + // Feature is valid for target attribute but not target_clones + return Diag(CurLoc, diag::err_ppc_feature_no_runtime_detection) + << FeatureName; + } } SmallString<64> CPU; if (LHS.starts_with("cpu=")) { @@ -660,6 +692,15 @@ bool SemaPPC::checkTargetClonesAttr(const SmallVectorImpl<StringRef> &Params, continue; } NewParams.push_back(LHS); + + // If we just processed the last item and there's a trailing comma, + // do one more iteration to catch the empty string + if (checkTrailingEmpty) { + LHS = ""; + const SourceLocation &EmptyCurLoc = Loc.getLocWithOffset(Param.size()); + return Diag(EmptyCurLoc, diag::warn_unsupported_target_attribute) + << Unknown << None << "" << TargetClones; + } } while (!RHS.empty()); } if (HasComma && Params.size() > 1) diff --git a/clang/test/CodeGen/PowerPC/attr-target-clones-mma.c b/clang/test/CodeGen/PowerPC/attr-target-clones-mma.c new file mode 100644 index 0000000000000..8e069eb17d64c --- /dev/null +++ b/clang/test/CodeGen/PowerPC/attr-target-clones-mma.c @@ -0,0 +1,16 @@ +// RUN: %clang_cc1 -triple powerpc-ibm-aix-xcoff -target-cpu pwr10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -target-cpu pwr10 -emit-llvm %s -o - | FileCheck %s + +// Test MMA feature which requires pwr10 +int __attribute__((target_clones("mma", "default"))) +foo_mma(void) { return 0; } +// CHECK: define internal {{.*}}i32 @foo_mma.mma() +// CHECK: define internal {{.*}}i32 @foo_mma.default() +// CHECK: define internal ptr @foo_mma.resolver() +// if (__builtin_cpu_supports("mma")) return &foo_mma.mma; +// CHECK: %[[#MMA:]] = call i64 @getsystemcfg(i32 62) +// CHECK-NEXT: icmp ugt i64 %[[#MMA]], 0 +// CHECK: ret ptr @foo_mma.mma +// CHECK: ret ptr @foo_mma.default + +// CHECK: declare i64 @getsystemcfg(i32) diff --git a/clang/test/CodeGen/PowerPC/attr-target-clones.c b/clang/test/CodeGen/PowerPC/attr-target-clones.c index c8cc9f2204b65..40f5a31f693e2 100644 --- a/clang/test/CodeGen/PowerPC/attr-target-clones.c +++ b/clang/test/CodeGen/PowerPC/attr-target-clones.c @@ -134,6 +134,95 @@ foo_priority(int x) { return x & (x - 1); } // CHECK: ret ptr @foo_priority.default +// Test feature-based target_clones +int __attribute__((target_clones("altivec", "default"))) +foo_altivec(void) { return 0; } +// CHECK: define internal {{.*}}i32 @foo_altivec.altivec() +// CHECK: define internal {{.*}}i32 @foo_altivec.default() +// CHECK: define internal ptr @foo_altivec.resolver() +// if (__builtin_cpu_supports("altivec")) return &foo_altivec.altivec; +// CHECK: %[[#ALTIVEC:]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @_system_configuration, {{i32|i64}} 204) +// CHECK-NEXT: icmp ugt i32 %[[#ALTIVEC]], 0 +// CHECK: ret ptr @foo_altivec.altivec +// CHECK: ret ptr @foo_altivec.default + +int __attribute__((target_clones("vsx", "default"))) +foo_vsx(void) { return 0; } +// CHECK: define internal {{.*}}i32 @foo_vsx.vsx() +// CHECK: define internal {{.*}}i32 @foo_vsx.default() +// CHECK: define internal ptr @foo_vsx.resolver() +// if (__builtin_cpu_supports("vsx")) return &foo_vsx.vsx; +// CHECK: %[[#VSX:]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @_system_configuration, {{i32|i64}} 204) +// CHECK-NEXT: icmp ugt i32 %[[#VSX]], 1 +// CHECK: ret ptr @foo_vsx.vsx +// CHECK: ret ptr @foo_vsx.default + +int __attribute__((target_clones("htm", "default"))) +foo_htm(void) { return 0; } +// CHECK: define internal {{.*}}i32 @foo_htm.htm() +// CHECK: define internal {{.*}}i32 @foo_htm.default() +// CHECK: define internal ptr @foo_htm.resolver() +// if (__builtin_cpu_supports("htm")) return &foo_htm.htm; +// CHECK: %[[#HTM:]] = call i64 @getsystemcfg(i32 59) +// CHECK-NEXT: icmp ugt i64 %[[#HTM]], 0 +// CHECK: ret ptr @foo_htm.htm +// CHECK: ret ptr @foo_htm.default + + + +// Test multiple features with priority ordering (random source order) +// Source order: altivec, power8-vector, cpu=pwr11, vsx, power9-vector, default +// Resolver order by priority: cpu=pwr11 (500) > power9-vector (311) > power8-vector (212) > vsx (111) > altivec (50) > default (0) +int __attribute__((target_clones("altivec", "power8-vector", "cpu=pwr11", "vsx", "power9-vector", "default"))) +foo_multi_features(void) { return 0; } +// CHECK: define internal {{.*}}i32 @foo_multi_features.altivec() +// CHECK: define internal {{.*}}i32 @foo_multi_features.power8_vector() +// CHECK: define internal {{.*}}i32 @foo_multi_features.cpu_pwr11() #[[#ATTR_P11]] +// CHECK: define internal {{.*}}i32 @foo_multi_features.vsx() +// CHECK: define internal {{.*}}i32 @foo_multi_features.power9_vector() +// CHECK: define internal {{.*}}i32 @foo_multi_features.default() +// CHECK: define internal ptr @foo_multi_features.resolver() +// Resolver checks in priority order (highest first): +// if (__builtin_cpu_supports("arch_3_1")) return &foo_multi_features.cpu_pwr11; +// CHECK: load i32, ptr getelementptr inbounds nuw (i8, ptr @_system_configuration, {{i32|i64}} 4) +// CHECK-NEXT: icmp uge i32 {{.*}}, 262144 +// CHECK: ret ptr @foo_multi_features.cpu_pwr11 +// if (__builtin_cpu_supports("arch_3_00")) return &foo_multi_features.power9_vector; +// CHECK: load i32, ptr getelementptr inbounds nuw (i8, ptr @_system_configuration, {{i32|i64}} 4) +// CHECK-NEXT: icmp uge i32 {{.*}}, 131072 +// CHECK: ret ptr @foo_multi_features.power9_vector +// if (__builtin_cpu_supports("arch_2_07")) return &foo_multi_features.power8_vector; +// CHECK: load i32, ptr getelementptr inbounds nuw (i8, ptr @_system_configuration, {{i32|i64}} 4) +// CHECK-NEXT: icmp uge i32 {{.*}}, 65536 +// CHECK: ret ptr @foo_multi_features.power8_vector +// if (__builtin_cpu_supports("vsx")) return &foo_multi_features.vsx; +// CHECK: %[[#VSX2:]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @_system_configuration, {{i32|i64}} 204) +// CHECK-NEXT: icmp ugt i32 %[[#VSX2]], 1 +// CHECK: ret ptr @foo_multi_features.vsx +// if (__builtin_cpu_supports("altivec")) return &foo_multi_features.altivec; +// CHECK: %[[#ALTIVEC2:]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @_system_configuration, {{i32|i64}} 204) +// CHECK-NEXT: icmp ugt i32 %[[#ALTIVEC2]], 0 +// CHECK: ret ptr @foo_multi_features.altivec +// CHECK: ret ptr @foo_multi_features.default + +// Test negated feature (no-altivec) - should negate the condition +int __attribute__((target_clones("no-altivec", "default"))) +foo_no_altivec(void) { return 0; } +// CHECK: define internal {{.*}}i32 @foo_no_altivec.no_altivec() +// CHECK: define internal {{.*}}i32 @foo_no_altivec.default() +// CHECK: define internal ptr @foo_no_altivec.resolver() +// if (!__builtin_cpu_supports("altivec")) return &foo_no_altivec.no_altivec; +// CHECK: load i32, ptr getelementptr inbounds nuw (i8, ptr @_system_configuration, {{i32|i64}} 204) +// CHECK-NEXT: icmp ugt i32 +// CHECK-NEXT: %neg = xor i1 {{.*}}, true +// CHECK-NEXT: br i1 %neg, label %if.version, label %if.else +// CHECK: if.version: +// CHECK-NEXT: ret ptr @foo_no_altivec.no_altivec +// CHECK: if.else: +// CHECK-NEXT: ret ptr @foo_no_altivec.default + +// CHECK: declare i64 @getsystemcfg(i32) + // CHECK: attributes #[[#ATTR_P7]] = {{.*}} "target-cpu"="pwr7" // CHECK: attributes #[[#ATTR_P10]] = {{.*}} "target-cpu"="pwr10" // CHECK: attributes #[[#ATTR_P11]] = {{.*}} "target-cpu"="pwr11" diff --git a/clang/test/Sema/PowerPC/attr-target-clones.c b/clang/test/Sema/PowerPC/attr-target-clones.c index 96acc974320b0..0f078fa2e805c 100644 --- a/clang/test/Sema/PowerPC/attr-target-clones.c +++ b/clang/test/Sema/PowerPC/attr-target-clones.c @@ -42,20 +42,20 @@ int __attribute__((target_clones("cpu=pwr9,default"))) redef3(void) { return 1; int __attribute__((target_clones("cpu=pwr9,cpu=power9", "cpu=power9, default"))) dupes(void) { return 1; } -// expected-warning@+1 {{unsupported '' in the 'target_clones' attribute string;}} +// expected-warning@+1 {{unknown '' in the 'target_clones' attribute string;}} void __attribute__((target_clones(""))) empty_target_1(void); -// expected-warning@+1 {{unsupported '' in the 'target_clones' attribute string;}} +// expected-warning@+1 {{unknown '' in the 'target_clones' attribute string;}} void __attribute__((target_clones(",default"))) empty_target_2(void); -// expected-warning@+1 {{unsupported '' in the 'target_clones' attribute string;}} +// expected-warning@+1 {{unknown '' in the 'target_clones' attribute string;}} void __attribute__((target_clones("default,"))) empty_target_3(void); -// expected-warning@+1 {{unsupported '' in the 'target_clones' attribute string;}} +// expected-warning@+1 {{unknown '' in the 'target_clones' attribute string;}} void __attribute__((target_clones("default, ,cpu=pwr7"))) empty_target_4(void); -// expected-warning@+1 {{unsupported '' in the 'target_clones' attribute string;}} +// expected-warning@+1 {{unknown '' in the 'target_clones' attribute string;}} void __attribute__((target_clones("default,cpu=pwr7", ""))) empty_target_5(void); @@ -130,3 +130,92 @@ gh173684_empty_attribute_args(void); // expected-error@+1 {{'target_clones' multiversioning requires a default target}} void __attribute__((target_clones)) gh173684_empty_attribute_args_2(void); + +// TODO: Consider combining some of these tests into fewer test cases with multiple features +// e.g., target_clones("feature1", "feature2", "feature3", ..., "default") to test +// feature1, feature2, feature3 all in one declaration instead of separate functions + +// Test that all valid feature names are accepted (no diagnostics expected) +void __attribute__((target_clones("altivec", "default"))) +valid_feature_altivec(void); + +void __attribute__((target_clones("vsx", "default"))) +valid_feature_vsx(void); + +void __attribute__((target_clones("crypto", "default"))) +valid_feature_crypto(void); + +void __attribute__((target_clones("power8-vector", "default"))) +valid_feature_power8_vector(void); + +void __attribute__((target_clones("power9-vector", "default"))) +valid_feature_power9_vector(void); + +void __attribute__((target_clones("power10-vector", "default"))) +valid_feature_power10_vector(void); + +void __attribute__((target_clones("mma", "default"))) +valid_feature_mma(void); + +void __attribute__((target_clones("htm", "default"))) +valid_feature_htm(void); + +// isel is always available on AIX (no runtime check), so it's not valid for target_clones +// expected-error@+1 {{feature 'isel' cannot be used with 'target_clones' because it has no runtime detection; use 'target' attribute instead}} +void __attribute__((target_clones("isel", "default"))) +invalid_feature_isel(void); + +// expected-error@+1 {{feature 'isel' cannot be used with 'target_clones' because it has no runtime detection; use 'target' attribute instead}} +void __attribute__((target_clones("no-isel", "default"))) +invalid_feature_no_isel(void); + +// Test that negated valid feature names are accepted (no diagnostics expected) +void __attribute__((target_clones("no-altivec", "default"))) +valid_feature_no_altivec(void); + +void __attribute__((target_clones("no-vsx", "default"))) +valid_feature_no_vsx(void); + +void __attribute__((target_clones("no-crypto", "default"))) +valid_feature_no_crypto(void); + +void __attribute__((target_clones("no-power8-vector", "default"))) +valid_feature_no_power8_vector(void); + +void __attribute__((target_clones("no-power9-vector", "default"))) +valid_feature_no_power9_vector(void); + +void __attribute__((target_clones("no-power10-vector", "default"))) +valid_feature_no_power10_vector(void); + +void __attribute__((target_clones("no-mma", "default"))) +valid_feature_no_mma(void); + +void __attribute__((target_clones("no-htm", "default"))) +valid_feature_no_htm(void); + +// Test multiple valid features together (one example with mixing warning) +// expected-warning@+1 {{mixing 'target_clones' specifier mechanisms is permitted for GCC compatibility}} +void __attribute__((target_clones("altivec,vsx", "default"))) +valid_multiple_features_1(void); + +// Use separate string literals to avoid mixing warning +void __attribute__((target_clones("vsx", "crypto", "htm", "default"))) +valid_multiple_features_2(void); + +void __attribute__((target_clones("power9-vector", "mma", "default"))) +valid_multiple_features_3(void); + +// Test mix of features and negations +void __attribute__((target_clones("altivec", "no-vsx", "default"))) +valid_mixed_features_1(void); + +void __attribute__((target_clones("vsx", "no-crypto", "default"))) +valid_mixed_features_2(void); + +// Test features with CPU specifications +void __attribute__((target_clones("altivec", "cpu=pwr8", "default"))) +valid_feature_with_cpu_1(void); + +void __attribute__((target_clones("vsx", "crypto", "cpu=pwr9", "default"))) +valid_feature_with_cpu_2(void); diff --git a/clang/test/Sema/attr-target.c b/clang/test/Sema/attr-target.c index ddf6654632187..4426ce96d774d 100644 --- a/clang/test/Sema/attr-target.c +++ b/clang/test/Sema/attr-target.c @@ -67,7 +67,7 @@ int __attribute__((target("branch-protection=none"))) birch_tree(void) { return #elifdef __powerpc__ -int __attribute__((target("float128,arch=pwr9"))) foo(void) { return 4; } +int __attribute__((target("float128,cpu=pwr9"))) foo(void) { return 4; } //expected-error@+1 {{'target' attribute takes one argument}} int __attribute__((target())) bar(void) { return 4; } // no warning, tune is supported for PPC >From b416c8ed7c786216a1262ad110fef0553a0d68bb Mon Sep 17 00:00:00 2001 From: Wael Yehia <[email protected]> Date: Wed, 1 Jul 2026 02:37:23 +0000 Subject: [PATCH 2/3] pcrel is not supported on AIX, reject it from target/target_clones --- clang/lib/Basic/Targets/PPC.cpp | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp index 4b1e78df86f67..df68e16f310dd 100644 --- a/clang/lib/Basic/Targets/PPC.cpp +++ b/clang/lib/Basic/Targets/PPC.cpp @@ -746,7 +746,6 @@ llvm::APInt PPCTargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const { // POWER10 features (between pwr10=400 and pwr11=500) .Case("mma", 419) .Case("paired-vector-memops", 418) - .Case("pcrel", 417) .Case("power10-vector", 416) .Case("prefixed", 415) // POWER9 features (between pwr9=300 and pwr10=400) @@ -860,9 +859,9 @@ void PPCTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { } bool PPCTargetInfo::isValidFeatureName(StringRef Name) const { - // All 28 PPC features valid for target attribute + if (!getTriple().isOSAIX()) + return TargetInfo::isValidFeatureName(Name); return llvm::StringSwitch<bool>(Name) - // Features with runtime detection (valid for target_clones) .Case("altivec", true) .Case("htm", true) .Case("mma", true) @@ -871,13 +870,11 @@ bool PPCTargetInfo::isValidFeatureName(StringRef Name) const { .Case("direct-move", true) .Case("float128", true) .Case("paired-vector-memops", true) - .Case("pcrel", true) .Case("popcntd", true) .Case("power8-vector", true) .Case("power9-vector", true) .Case("power10-vector", true) .Case("prefixed", true) - // Features without runtime checks (NOT valid for target_clones) .Case("aix-shared-lib-tls-model-opt", true) .Case("aix-small-local-dynamic-tls", true) .Case("aix-small-local-exec-tls", true) @@ -908,7 +905,6 @@ bool PPCTargetInfo::isValidClonesFeatureName(StringRef Name) const { .Case("direct-move", true) .Case("float128", true) .Case("paired-vector-memops", true) - .Case("pcrel", true) .Case("popcntd", true) .Case("power8-vector", true) .Case("power9-vector", true) @@ -935,7 +931,6 @@ PPCTargetInfo::getBuiltinCpuSupportsName(StringRef FeatureName) const { .Case("float128", "arch_3_00") .Case("power9-vector", "arch_3_00") .Case("paired-vector-memops", "arch_3_1") - .Case("pcrel", "arch_3_1") .Case("power10-vector", "arch_3_1") .Case("prefixed", "arch_3_1") // Features without runtime checks return empty string >From 38ff48d0290577359ea92be4e45257c45a24cee4 Mon Sep 17 00:00:00 2001 From: Wael Yehia <[email protected]> Date: Wed, 1 Jul 2026 03:01:53 +0000 Subject: [PATCH 3/3] merge attr-target-clones-mma.c into attr-target-clones.c --- .../CodeGen/PowerPC/attr-target-clones-mma.c | 16 ---------------- clang/test/CodeGen/PowerPC/attr-target-clones.c | 14 +++++++++++++- 2 files changed, 13 insertions(+), 17 deletions(-) delete mode 100644 clang/test/CodeGen/PowerPC/attr-target-clones-mma.c diff --git a/clang/test/CodeGen/PowerPC/attr-target-clones-mma.c b/clang/test/CodeGen/PowerPC/attr-target-clones-mma.c deleted file mode 100644 index 8e069eb17d64c..0000000000000 --- a/clang/test/CodeGen/PowerPC/attr-target-clones-mma.c +++ /dev/null @@ -1,16 +0,0 @@ -// RUN: %clang_cc1 -triple powerpc-ibm-aix-xcoff -target-cpu pwr10 -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -target-cpu pwr10 -emit-llvm %s -o - | FileCheck %s - -// Test MMA feature which requires pwr10 -int __attribute__((target_clones("mma", "default"))) -foo_mma(void) { return 0; } -// CHECK: define internal {{.*}}i32 @foo_mma.mma() -// CHECK: define internal {{.*}}i32 @foo_mma.default() -// CHECK: define internal ptr @foo_mma.resolver() -// if (__builtin_cpu_supports("mma")) return &foo_mma.mma; -// CHECK: %[[#MMA:]] = call i64 @getsystemcfg(i32 62) -// CHECK-NEXT: icmp ugt i64 %[[#MMA]], 0 -// CHECK: ret ptr @foo_mma.mma -// CHECK: ret ptr @foo_mma.default - -// CHECK: declare i64 @getsystemcfg(i32) diff --git a/clang/test/CodeGen/PowerPC/attr-target-clones.c b/clang/test/CodeGen/PowerPC/attr-target-clones.c index 40f5a31f693e2..48557660929b1 100644 --- a/clang/test/CodeGen/PowerPC/attr-target-clones.c +++ b/clang/test/CodeGen/PowerPC/attr-target-clones.c @@ -1,5 +1,6 @@ // RUN: %clang_cc1 -triple powerpc-ibm-aix-xcoff -target-cpu pwr7 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -target-cpu pwr7 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -target-cpu pwr10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-P10 // CHECK: @internal = internal ifunc i32 (), ptr @internal.resolver // CHECK: @foo = ifunc i32 (), ptr @foo.resolver @@ -168,7 +169,18 @@ foo_htm(void) { return 0; } // CHECK: ret ptr @foo_htm.htm // CHECK: ret ptr @foo_htm.default - +#ifdef _ARCH_PWR10 +int __attribute__((target_clones("mma", "default"))) +foo_mma(void) { return 0; } +#endif +// CHECK-P10: define internal {{.*}}i32 @foo_mma.mma() +// CHECK-P10: define internal {{.*}}i32 @foo_mma.default() +// CHECK-P10: define internal ptr @foo_mma.resolver() +// if (__builtin_cpu_supports("mma")) return &foo_mma.mma; +// CHECK-P10: %[[#MMA:]] = call i64 @getsystemcfg(i32 62) +// CHECK-P10-NEXT: icmp ugt i64 %[[#MMA]], 0 +// CHECK-P10: ret ptr @foo_mma.mma +// CHECK-P10: ret ptr @foo_mma.default // Test multiple features with priority ordering (random source order) // Source order: altivec, power8-vector, cpu=pwr11, vsx, power9-vector, default _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
