Author: AbdallahRashed Date: 2026-07-05T10:58:46+01:00 New Revision: f26f3e659f4a4292f8cf311f351bcc231dc59c71
URL: https://github.com/llvm/llvm-project/commit/f26f3e659f4a4292f8cf311f351bcc231dc59c71 DIFF: https://github.com/llvm/llvm-project/commit/f26f3e659f4a4292f8cf311f351bcc231dc59c71.diff LOG: [clang][CIR] Add lowering for Neon rounding builtins (#195021) This PR adds CIR lowering for AArch64 NEON rounding builtins: - vrnd (trunc), vrnda (round), vrndi (nearbyint), vrndm (floor), vrndn (roundeven), vrndp (ceil), vrndx (rint) - vrnd32x, vrnd32z, vrnd64x, vrnd64z (v8.5-a FRINT variants) The standard rounding builtins lower to the corresponding CIR ops (cir.trunc, cir.round, etc.). The vrndi_v/vrndiq_v cases are handled in the common NEON switch since they enter via AArch64SIMDIntrinsicMap (NEONMAP0). The vrnd32/64 builtins use NEONMAP1 entries with their aarch64.neon.frint* intrinsic names. The lowering follows the existing implementation in CodeGen/TargetBuiltins/ARM.cpp. Prior to this patch, the original neon-intrinsics.c had zero f32 standard rounding tests : I had added 15 test cases to cover f32 standard rounding tests (vrnd_f32, vrnda_f32, etc.) in clang/test/CodeGen/AArch64/neon/intrinsics.c For this reasons, 30 num-of-new-tests > 15 num-of-deleted-tests. Part of https://github.com/llvm/llvm-project/issues/185382. Added: clang/test/CodeGen/AArch64/neon/rounding-v8.5.c Modified: clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp clang/test/CodeGen/AArch64/neon-intrinsics.c clang/test/CodeGen/AArch64/neon/intrinsics.c clang/test/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c Removed: ################################################################################ diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index e3418d561df34..36e205577a1ff 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -962,12 +962,15 @@ static mlir::Value emitCommonNeonBuiltinExpr( case NEON::BI__builtin_neon_vrecpeq_v: case NEON::BI__builtin_neon_vrsqrte_v: case NEON::BI__builtin_neon_vrsqrteq_v: - case NEON::BI__builtin_neon_vrndi_v: - case NEON::BI__builtin_neon_vrndiq_v: cgf.cgm.errorNYI(expr->getSourceRange(), std::string("unimplemented AArch64 builtin call: ") + ctx.BuiltinInfo.getName(builtinID)); return mlir::Value{}; + case NEON::BI__builtin_neon_vrndi_v: + case NEON::BI__builtin_neon_vrndiq_v: + assert(!cir::MissingFeatures::emitConstrainedFPCall()); + return emitNeonCallToOp<cir::NearbyintOp>(cgf.cgm, cgf.getBuilder(), {ty}, + ops, std::nullopt, ty, loc); case NEON::BI__builtin_neon_vrshr_n_v: case NEON::BI__builtin_neon_vrshrq_n_v: { llvm::StringRef intrName = @@ -1092,6 +1095,30 @@ static mlir::Value emitCommonNeonBuiltinExpr( std::string("unimplemented AArch64 builtin call: ") + cgf.getContext().BuiltinInfo.getName(builtinID)); break; + case NEON::BI__builtin_neon_vrnd32x_f32: + case NEON::BI__builtin_neon_vrnd32xq_f32: + case NEON::BI__builtin_neon_vrnd32x_f64: + case NEON::BI__builtin_neon_vrnd32xq_f64: + case NEON::BI__builtin_neon_vrnd32z_f32: + case NEON::BI__builtin_neon_vrnd32zq_f32: + case NEON::BI__builtin_neon_vrnd32z_f64: + case NEON::BI__builtin_neon_vrnd32zq_f64: + case NEON::BI__builtin_neon_vrnd64x_f32: + case NEON::BI__builtin_neon_vrnd64xq_f32: + case NEON::BI__builtin_neon_vrnd64x_f64: + case NEON::BI__builtin_neon_vrnd64xq_f64: + case NEON::BI__builtin_neon_vrnd64z_f32: + case NEON::BI__builtin_neon_vrnd64zq_f32: + case NEON::BI__builtin_neon_vrnd64z_f64: + case NEON::BI__builtin_neon_vrnd64zq_f64: { + llvm::StringRef llvmIntrName = getLLVMIntrNameNoPrefix( + static_cast<llvm::Intrinsic::ID>(llvmIntrinsic)); + mlir::Value result = + emitNeonCall(cgf.cgm, cgf.getBuilder(), /*argTypes=*/{vTy}, ops, + llvmIntrName, /*funcResTy=*/vTy, loc); + mlir::Type resultType = cgf.convertType(expr->getType()); + return cgf.getBuilder().createBitcast(result, resultType); + } case NEON::BI__builtin_neon_vhadd_v: case NEON::BI__builtin_neon_vhaddq_v: case NEON::BI__builtin_neon_vrhadd_v: @@ -2907,45 +2934,61 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, loc); } case NEON::BI__builtin_neon_vrndah_f16: + assert(!cir::MissingFeatures::emitConstrainedFPCall()); + return cir::RoundOp::create(builder, loc, ops[0]); case NEON::BI__builtin_neon_vrnda_v: case NEON::BI__builtin_neon_vrndaq_v: + assert(!cir::MissingFeatures::emitConstrainedFPCall()); + return emitNeonCallToOp<cir::RoundOp>(cgm, builder, {ty}, ops, std::nullopt, + ty, loc); case NEON::BI__builtin_neon_vrndih_f16: + assert(!cir::MissingFeatures::emitConstrainedFPCall()); + return cir::NearbyintOp::create(builder, loc, ops[0]); case NEON::BI__builtin_neon_vrndmh_f16: + assert(!cir::MissingFeatures::emitConstrainedFPCall()); + return cir::FloorOp::create(builder, loc, ops[0]); case NEON::BI__builtin_neon_vrndm_v: case NEON::BI__builtin_neon_vrndmq_v: + assert(!cir::MissingFeatures::emitConstrainedFPCall()); + return emitNeonCallToOp<cir::FloorOp>(cgm, builder, {ty}, ops, std::nullopt, + ty, loc); case NEON::BI__builtin_neon_vrndnh_f16: + assert(!cir::MissingFeatures::emitConstrainedFPCall()); + return cir::RoundEvenOp::create(builder, loc, ops[0]); case NEON::BI__builtin_neon_vrndn_v: case NEON::BI__builtin_neon_vrndnq_v: - case NEON::BI__builtin_neon_vrndns_f32: + assert(!cir::MissingFeatures::emitConstrainedFPCall()); + return emitNeonCallToOp<cir::RoundEvenOp>(cgm, builder, {ty}, ops, + std::nullopt, ty, loc); + case NEON::BI__builtin_neon_vrndns_f32: { + assert(!cir::MissingFeatures::emitConstrainedFPCall()); + mlir::Value arg0 = emitScalarExpr(expr->getArg(0)); + return cir::RoundEvenOp::create(builder, getLoc(expr->getExprLoc()), arg0); + } case NEON::BI__builtin_neon_vrndph_f16: + assert(!cir::MissingFeatures::emitConstrainedFPCall()); + return cir::CeilOp::create(builder, loc, ops[0]); case NEON::BI__builtin_neon_vrndp_v: case NEON::BI__builtin_neon_vrndpq_v: + assert(!cir::MissingFeatures::emitConstrainedFPCall()); + return emitNeonCallToOp<cir::CeilOp>(cgm, builder, {ty}, ops, std::nullopt, + ty, loc); case NEON::BI__builtin_neon_vrndxh_f16: + assert(!cir::MissingFeatures::emitConstrainedFPCall()); + return cir::RintOp::create(builder, loc, ops[0]); case NEON::BI__builtin_neon_vrndx_v: case NEON::BI__builtin_neon_vrndxq_v: + assert(!cir::MissingFeatures::emitConstrainedFPCall()); + return emitNeonCallToOp<cir::RintOp>(cgm, builder, {ty}, ops, std::nullopt, + ty, loc); case NEON::BI__builtin_neon_vrndh_f16: - case NEON::BI__builtin_neon_vrnd32x_f32: - case NEON::BI__builtin_neon_vrnd32xq_f32: - case NEON::BI__builtin_neon_vrnd32x_f64: - case NEON::BI__builtin_neon_vrnd32xq_f64: - case NEON::BI__builtin_neon_vrnd32z_f32: - case NEON::BI__builtin_neon_vrnd32zq_f32: - case NEON::BI__builtin_neon_vrnd32z_f64: - case NEON::BI__builtin_neon_vrnd32zq_f64: - case NEON::BI__builtin_neon_vrnd64x_f32: - case NEON::BI__builtin_neon_vrnd64xq_f32: - case NEON::BI__builtin_neon_vrnd64x_f64: - case NEON::BI__builtin_neon_vrnd64xq_f64: - case NEON::BI__builtin_neon_vrnd64z_f32: - case NEON::BI__builtin_neon_vrnd64zq_f32: - case NEON::BI__builtin_neon_vrnd64z_f64: - case NEON::BI__builtin_neon_vrnd64zq_f64: + assert(!cir::MissingFeatures::emitConstrainedFPCall()); + return cir::TruncOp::create(builder, loc, ops[0]); case NEON::BI__builtin_neon_vrnd_v: case NEON::BI__builtin_neon_vrndq_v: - cgm.errorNYI(expr->getSourceRange(), - std::string("unimplemented AArch64 builtin call: ") + - getContext().BuiltinInfo.getName(builtinID)); - return mlir::Value{}; + assert(!cir::MissingFeatures::emitConstrainedFPCall()); + return emitNeonCallToOp<cir::TruncOp>(cgm, builder, {ty}, ops, std::nullopt, + ty, loc); case NEON::BI__builtin_neon_vcvt_f64_v: case NEON::BI__builtin_neon_vcvtq_f64_v: ops[0] = builder.createBitcast(ops[0], ty); diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index d956ed754c45a..10df86ae410d6 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -16671,105 +16671,6 @@ float64x1_t test_vcvt_f64_u64(uint64x1_t a) { return vcvt_f64_u64(a); } - -// CHECK-LABEL: define dso_local <1 x double> @test_vrndn_f64( -// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64 -// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 0 -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8> -// CHECK-NEXT: [[VRNDN_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double> -// CHECK-NEXT: [[VRNDN1_I:%.*]] = call <1 x double> @llvm.roundeven.v1f64(<1 x double> [[VRNDN_I]]) -// CHECK-NEXT: ret <1 x double> [[VRNDN1_I]] -// -float64x1_t test_vrndn_f64(float64x1_t a) { - return vrndn_f64(a); -} - -// CHECK-LABEL: define dso_local <1 x double> @test_vrnda_f64( -// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64 -// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 0 -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8> -// CHECK-NEXT: [[VRNDA_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double> -// CHECK-NEXT: [[VRNDA1_I:%.*]] = call <1 x double> @llvm.round.v1f64(<1 x double> [[VRNDA_I]]) -// CHECK-NEXT: ret <1 x double> [[VRNDA1_I]] -// -float64x1_t test_vrnda_f64(float64x1_t a) { - return vrnda_f64(a); -} - -// CHECK-LABEL: define dso_local <1 x double> @test_vrndp_f64( -// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64 -// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 0 -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8> -// CHECK-NEXT: [[VRNDP_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double> -// CHECK-NEXT: [[VRNDP1_I:%.*]] = call <1 x double> @llvm.ceil.v1f64(<1 x double> [[VRNDP_I]]) -// CHECK-NEXT: ret <1 x double> [[VRNDP1_I]] -// -float64x1_t test_vrndp_f64(float64x1_t a) { - return vrndp_f64(a); -} - -// CHECK-LABEL: define dso_local <1 x double> @test_vrndm_f64( -// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64 -// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 0 -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8> -// CHECK-NEXT: [[VRNDM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double> -// CHECK-NEXT: [[VRNDM1_I:%.*]] = call <1 x double> @llvm.floor.v1f64(<1 x double> [[VRNDM_I]]) -// CHECK-NEXT: ret <1 x double> [[VRNDM1_I]] -// -float64x1_t test_vrndm_f64(float64x1_t a) { - return vrndm_f64(a); -} - -// CHECK-LABEL: define dso_local <1 x double> @test_vrndx_f64( -// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64 -// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 0 -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8> -// CHECK-NEXT: [[VRNDX_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double> -// CHECK-NEXT: [[VRNDX1_I:%.*]] = call <1 x double> @llvm.rint.v1f64(<1 x double> [[VRNDX_I]]) -// CHECK-NEXT: ret <1 x double> [[VRNDX1_I]] -// -float64x1_t test_vrndx_f64(float64x1_t a) { - return vrndx_f64(a); -} - -// CHECK-LABEL: define dso_local <1 x double> @test_vrnd_f64( -// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64 -// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 0 -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8> -// CHECK-NEXT: [[VRNDZ_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double> -// CHECK-NEXT: [[VRNDZ1_I:%.*]] = call <1 x double> @llvm.trunc.v1f64(<1 x double> [[VRNDZ_I]]) -// CHECK-NEXT: ret <1 x double> [[VRNDZ1_I]] -// -float64x1_t test_vrnd_f64(float64x1_t a) { - return vrnd_f64(a); -} - -// CHECK-LABEL: define dso_local <1 x double> @test_vrndi_f64( -// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64 -// CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 0 -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__P0_ADDR_I_SROA_0_0_VEC_INSERT]] to <8 x i8> -// CHECK-NEXT: [[VRNDI_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double> -// CHECK-NEXT: [[VRNDI_V1_I:%.*]] = call <1 x double> @llvm.nearbyint.v1f64(<1 x double> [[VRNDI_V_I]]) -// CHECK-NEXT: ret <1 x double> [[VRNDI_V1_I]] -// -float64x1_t test_vrndi_f64(float64x1_t a) { - return vrndi_f64(a); -} - // CHECK-LABEL: define dso_local <1 x double> @test_vrsqrte_f64( // CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index 3f309f7359084..7f4ef381e6e5d 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -7068,3 +7068,476 @@ uint64x2_t test_vshll_high_n_u32(uint32x4_t a) { // LLVM: ret <2 x i64> [[VSHLL_N]] return vshll_high_n_u32(a, 19); } + +//===------------------------------------------------------===// +// 2.1.1.9. Rounding +//https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#rounding +//===------------------------------------------------------===// + +// LLVM-LABEL: @test_vrnd_f32( +// CIR-LABEL: @vrnd_f32( +float32x2_t test_vrnd_f32(float32x2_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float> +// CIR: cir.trunc [[CAST]] : !cir.vector<2 x !cir.float> + +// LLVM-SAME: <2 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8> +// LLVM: [[VRND_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> +// LLVM: [[VRND1_I:%.*]] = call <2 x float> @llvm.trunc.v2f32(<2 x float> [[VRND_I]]) +// LLVM: ret <2 x float> [[VRND1_I]] + return vrnd_f32(a); +} + +// LLVM-LABEL: @test_vrndq_f32( +// CIR-LABEL: @vrndq_f32( +float32x4_t test_vrndq_f32(float32x4_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float> +// CIR: cir.trunc [[CAST]] : !cir.vector<4 x !cir.float> + +// LLVM-SAME: <4 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// LLVM: [[VRND_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> +// LLVM: [[VRND1_I:%.*]] = call <4 x float> @llvm.trunc.v4f32(<4 x float> [[VRND_I]]) +// LLVM: ret <4 x float> [[VRND1_I]] + return vrndq_f32(a); +} + +// LLVM-LABEL: @test_vrnd_f64( +// CIR-LABEL: @vrnd_f64( +float64x1_t test_vrnd_f64(float64x1_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double> +// CIR: cir.trunc [[CAST]] : !cir.vector<1 x !cir.double> + +// LLVM-SAME: <1 x double> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64 +// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 0 +// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8> +// LLVM: [[VRND_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double> +// LLVM: [[VRND1_I:%.*]] = call <1 x double> @llvm.trunc.v1f64(<1 x double> [[VRND_I]]) +// LLVM: ret <1 x double> [[VRND1_I]] + return vrnd_f64(a); +} + +// LLVM-LABEL: @test_vrndq_f64( +// CIR-LABEL: @vrndq_f64( +float64x2_t test_vrndq_f64(float64x2_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double> +// CIR: cir.trunc [[CAST]] : !cir.vector<2 x !cir.double> + +// LLVM-SAME: <2 x double> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> +// LLVM: [[VRND_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> +// LLVM: [[VRND1_I:%.*]] = call <2 x double> @llvm.trunc.v2f64(<2 x double> [[VRND_I]]) +// LLVM: ret <2 x double> [[VRND1_I]] + return vrndq_f64(a); +} + +// LLVM-LABEL: @test_vrndn_f32( +// CIR-LABEL: @vrndn_f32( +float32x2_t test_vrndn_f32(float32x2_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float> +// CIR: cir.roundeven [[CAST]] : !cir.vector<2 x !cir.float> + +// LLVM-SAME: <2 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8> +// LLVM: [[VRNDN_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> +// LLVM: [[VRNDN1_I:%.*]] = call <2 x float> @llvm.roundeven.v2f32(<2 x float> [[VRNDN_I]]) +// LLVM: ret <2 x float> [[VRNDN1_I]] + return vrndn_f32(a); +} + +// LLVM-LABEL: @test_vrndnq_f32( +// CIR-LABEL: @vrndnq_f32( +float32x4_t test_vrndnq_f32(float32x4_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float> +// CIR: cir.roundeven [[CAST]] : !cir.vector<4 x !cir.float> + +// LLVM-SAME: <4 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// LLVM: [[VRNDN_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> +// LLVM: [[VRNDN1_I:%.*]] = call <4 x float> @llvm.roundeven.v4f32(<4 x float> [[VRNDN_I]]) +// LLVM: ret <4 x float> [[VRNDN1_I]] + return vrndnq_f32(a); +} + +// LLVM-LABEL: @test_vrndn_f64( +// CIR-LABEL: @vrndn_f64( +float64x1_t test_vrndn_f64(float64x1_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double> +// CIR: cir.roundeven [[CAST]] : !cir.vector<1 x !cir.double> + +// LLVM-SAME: <1 x double> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64 +// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 0 +// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8> +// LLVM: [[VRNDN_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double> +// LLVM: [[VRNDN1_I:%.*]] = call <1 x double> @llvm.roundeven.v1f64(<1 x double> [[VRNDN_I]]) +// LLVM: ret <1 x double> [[VRNDN1_I]] + return vrndn_f64(a); +} + +// LLVM-LABEL: @test_vrndnq_f64( +// CIR-LABEL: @vrndnq_f64( +float64x2_t test_vrndnq_f64(float64x2_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double> +// CIR: cir.roundeven [[CAST]] : !cir.vector<2 x !cir.double> + +// LLVM-SAME: <2 x double> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> +// LLVM: [[VRNDN_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> +// LLVM: [[VRNDN1_I:%.*]] = call <2 x double> @llvm.roundeven.v2f64(<2 x double> [[VRNDN_I]]) +// LLVM: ret <2 x double> [[VRNDN1_I]] + return vrndnq_f64(a); +} + +// LLVM-LABEL: @test_vrndns_f32( +// CIR-LABEL: @vrndns_f32( +float32_t test_vrndns_f32(float32_t a) { +// CIR: cir.load {{.*}} : !cir.ptr<!cir.float>, !cir.float +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.float>, !cir.float +// CIR: cir.roundeven [[LOAD]] : !cir.float + +// LLVM-SAME: float noundef [[A:%.*]]) +// LLVM: [[VRNDN_I:%.*]] = call float @llvm.roundeven.f32(float [[A]]) +// LLVM: ret float [[VRNDN_I]] + return vrndns_f32(a); +} + +// LLVM-LABEL: @test_vrndm_f32( +// CIR-LABEL: @vrndm_f32( +float32x2_t test_vrndm_f32(float32x2_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float> +// CIR: cir.floor [[CAST]] : !cir.vector<2 x !cir.float> + +// LLVM-SAME: <2 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8> +// LLVM: [[VRNDM_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> +// LLVM: [[VRNDM1_I:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[VRNDM_I]]) +// LLVM: ret <2 x float> [[VRNDM1_I]] + return vrndm_f32(a); +} + +// LLVM-LABEL: @test_vrndmq_f32( +// CIR-LABEL: @vrndmq_f32( +float32x4_t test_vrndmq_f32(float32x4_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float> +// CIR: cir.floor [[CAST]] : !cir.vector<4 x !cir.float> + +// LLVM-SAME: <4 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// LLVM: [[VRNDM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> +// LLVM: [[VRNDM1_I:%.*]] = call <4 x float> @llvm.floor.v4f32(<4 x float> [[VRNDM_I]]) +// LLVM: ret <4 x float> [[VRNDM1_I]] + return vrndmq_f32(a); +} + +// LLVM-LABEL: @test_vrndm_f64( +// CIR-LABEL: @vrndm_f64( +float64x1_t test_vrndm_f64(float64x1_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double> +// CIR: cir.floor [[CAST]] : !cir.vector<1 x !cir.double> + +// LLVM-SAME: <1 x double> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64 +// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 0 +// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8> +// LLVM: [[VRNDM_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double> +// LLVM: [[VRNDM1_I:%.*]] = call <1 x double> @llvm.floor.v1f64(<1 x double> [[VRNDM_I]]) +// LLVM: ret <1 x double> [[VRNDM1_I]] + return vrndm_f64(a); +} + +// LLVM-LABEL: @test_vrndmq_f64( +// CIR-LABEL: @vrndmq_f64( +float64x2_t test_vrndmq_f64(float64x2_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double> +// CIR: cir.floor [[CAST]] : !cir.vector<2 x !cir.double> + +// LLVM-SAME: <2 x double> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> +// LLVM: [[VRNDM_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> +// LLVM: [[VRNDM1_I:%.*]] = call <2 x double> @llvm.floor.v2f64(<2 x double> [[VRNDM_I]]) +// LLVM: ret <2 x double> [[VRNDM1_I]] + return vrndmq_f64(a); +} + +// LLVM-LABEL: @test_vrndp_f32( +// CIR-LABEL: @vrndp_f32( +float32x2_t test_vrndp_f32(float32x2_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float> +// CIR: cir.ceil [[CAST]] : !cir.vector<2 x !cir.float> + +// LLVM-SAME: <2 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8> +// LLVM: [[VRNDP_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> +// LLVM: [[VRNDP1_I:%.*]] = call <2 x float> @llvm.ceil.v2f32(<2 x float> [[VRNDP_I]]) +// LLVM: ret <2 x float> [[VRNDP1_I]] + return vrndp_f32(a); +} + +// LLVM-LABEL: @test_vrndpq_f32( +// CIR-LABEL: @vrndpq_f32( +float32x4_t test_vrndpq_f32(float32x4_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float> +// CIR: cir.ceil [[CAST]] : !cir.vector<4 x !cir.float> + +// LLVM-SAME: <4 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// LLVM: [[VRNDP_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> +// LLVM: [[VRNDP1_I:%.*]] = call <4 x float> @llvm.ceil.v4f32(<4 x float> [[VRNDP_I]]) +// LLVM: ret <4 x float> [[VRNDP1_I]] + return vrndpq_f32(a); +} + +// LLVM-LABEL: @test_vrndp_f64( +// CIR-LABEL: @vrndp_f64( +float64x1_t test_vrndp_f64(float64x1_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double> +// CIR: cir.ceil [[CAST]] : !cir.vector<1 x !cir.double> + +// LLVM-SAME: <1 x double> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64 +// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 0 +// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8> +// LLVM: [[VRNDP_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double> +// LLVM: [[VRNDP1_I:%.*]] = call <1 x double> @llvm.ceil.v1f64(<1 x double> [[VRNDP_I]]) +// LLVM: ret <1 x double> [[VRNDP1_I]] + return vrndp_f64(a); +} + +// LLVM-LABEL: @test_vrndpq_f64( +// CIR-LABEL: @vrndpq_f64( +float64x2_t test_vrndpq_f64(float64x2_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double> +// CIR: cir.ceil [[CAST]] : !cir.vector<2 x !cir.double> + +// LLVM-SAME: <2 x double> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> +// LLVM: [[VRNDP_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> +// LLVM: [[VRNDP1_I:%.*]] = call <2 x double> @llvm.ceil.v2f64(<2 x double> [[VRNDP_I]]) +// LLVM: ret <2 x double> [[VRNDP1_I]] + return vrndpq_f64(a); +} + +// LLVM-LABEL: @test_vrnda_f32( +// CIR-LABEL: @vrnda_f32( +float32x2_t test_vrnda_f32(float32x2_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float> +// CIR: cir.round [[CAST]] : !cir.vector<2 x !cir.float> + +// LLVM-SAME: <2 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8> +// LLVM: [[VRNDA_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> +// LLVM: [[VRNDA1_I:%.*]] = call <2 x float> @llvm.round.v2f32(<2 x float> [[VRNDA_I]]) +// LLVM: ret <2 x float> [[VRNDA1_I]] + return vrnda_f32(a); +} + +// LLVM-LABEL: @test_vrndaq_f32( +// CIR-LABEL: @vrndaq_f32( +float32x4_t test_vrndaq_f32(float32x4_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float> +// CIR: cir.round [[CAST]] : !cir.vector<4 x !cir.float> + +// LLVM-SAME: <4 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// LLVM: [[VRNDA_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> +// LLVM: [[VRNDA1_I:%.*]] = call <4 x float> @llvm.round.v4f32(<4 x float> [[VRNDA_I]]) +// LLVM: ret <4 x float> [[VRNDA1_I]] + return vrndaq_f32(a); +} + +// LLVM-LABEL: @test_vrnda_f64( +// CIR-LABEL: @vrnda_f64( +float64x1_t test_vrnda_f64(float64x1_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double> +// CIR: cir.round [[CAST]] : !cir.vector<1 x !cir.double> + +// LLVM-SAME: <1 x double> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64 +// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 0 +// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8> +// LLVM: [[VRNDA_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double> +// LLVM: [[VRNDA1_I:%.*]] = call <1 x double> @llvm.round.v1f64(<1 x double> [[VRNDA_I]]) +// LLVM: ret <1 x double> [[VRNDA1_I]] + return vrnda_f64(a); +} + +// LLVM-LABEL: @test_vrndaq_f64( +// CIR-LABEL: @vrndaq_f64( +float64x2_t test_vrndaq_f64(float64x2_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double> +// CIR: cir.round [[CAST]] : !cir.vector<2 x !cir.double> + +// LLVM-SAME: <2 x double> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> +// LLVM: [[VRNDA_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> +// LLVM: [[VRNDA1_I:%.*]] = call <2 x double> @llvm.round.v2f64(<2 x double> [[VRNDA_I]]) +// LLVM: ret <2 x double> [[VRNDA1_I]] + return vrndaq_f64(a); +} + +// LLVM-LABEL: @test_vrndi_f32( +// CIR-LABEL: @vrndi_f32( +float32x2_t test_vrndi_f32(float32x2_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float> +// CIR: cir.nearbyint [[CAST]] : !cir.vector<2 x !cir.float> + +// LLVM-SAME: <2 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8> +// LLVM: [[VRNDI_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> +// LLVM: [[VRNDI_V1_I:%.*]] = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> [[VRNDI_V_I]]) +// LLVM: ret <2 x float> [[VRNDI_V1_I]] + return vrndi_f32(a); +} + +// LLVM-LABEL: @test_vrndiq_f32( +// CIR-LABEL: @vrndiq_f32( +float32x4_t test_vrndiq_f32(float32x4_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float> +// CIR: cir.nearbyint [[CAST]] : !cir.vector<4 x !cir.float> + +// LLVM-SAME: <4 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// LLVM: [[VRNDIQ_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> +// LLVM: [[VRNDIQ_V1_I:%.*]] = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> [[VRNDIQ_V_I]]) +// LLVM: ret <4 x float> [[VRNDIQ_V1_I]] + return vrndiq_f32(a); +} + +// LLVM-LABEL: @test_vrndi_f64( +// CIR-LABEL: @vrndi_f64( +float64x1_t test_vrndi_f64(float64x1_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double> +// CIR: cir.nearbyint [[CAST]] : !cir.vector<1 x !cir.double> + +// LLVM-SAME: <1 x double> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64 +// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 0 +// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8> +// LLVM: [[VRNDI_V_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double> +// LLVM: [[VRNDI_V1_I:%.*]] = call <1 x double> @llvm.nearbyint.v1f64(<1 x double> [[VRNDI_V_I]]) +// LLVM: ret <1 x double> [[VRNDI_V1_I]] + return vrndi_f64(a); +} + +// LLVM-LABEL: @test_vrndiq_f64( +// CIR-LABEL: @vrndiq_f64( +float64x2_t test_vrndiq_f64(float64x2_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double> +// CIR: cir.nearbyint [[CAST]] : !cir.vector<2 x !cir.double> + +// LLVM-SAME: <2 x double> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> +// LLVM: [[VRNDI_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> +// LLVM: [[VRNDI_V1_I:%.*]] = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> [[VRNDI_V_I]]) +// LLVM: ret <2 x double> [[VRNDI_V1_I]] + return vrndiq_f64(a); +} + +// LLVM-LABEL: @test_vrndx_f32( +// CIR-LABEL: @vrndx_f32( +float32x2_t test_vrndx_f32(float32x2_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float> +// CIR: cir.rint [[CAST]] : !cir.vector<2 x !cir.float> + +// LLVM-SAME: <2 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8> +// LLVM: [[VRNDX_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> +// LLVM: [[VRNDX1_I:%.*]] = call <2 x float> @llvm.rint.v2f32(<2 x float> [[VRNDX_I]]) +// LLVM: ret <2 x float> [[VRNDX1_I]] + return vrndx_f32(a); +} + +// LLVM-LABEL: @test_vrndxq_f32( +// CIR-LABEL: @vrndxq_f32( +float32x4_t test_vrndxq_f32(float32x4_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float> +// CIR: cir.rint [[CAST]] : !cir.vector<4 x !cir.float> + +// LLVM-SAME: <4 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// LLVM: [[VRNDX_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> +// LLVM: [[VRNDX1_I:%.*]] = call <4 x float> @llvm.rint.v4f32(<4 x float> [[VRNDX_I]]) +// LLVM: ret <4 x float> [[VRNDX1_I]] + return vrndxq_f32(a); +} + +// LLVM-LABEL: @test_vrndx_f64( +// CIR-LABEL: @vrndx_f64( +float64x1_t test_vrndx_f64(float64x1_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<1 x !cir.double> +// CIR: cir.rint [[CAST]] : !cir.vector<1 x !cir.double> + +// LLVM-SAME: <1 x double> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64 +// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 0 +// LLVM: [[TMP2:%.*]] = bitcast <1 x i64> [[TMP1]] to <8 x i8> +// LLVM: [[VRNDX_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double> +// LLVM: [[VRNDX1_I:%.*]] = call <1 x double> @llvm.rint.v1f64(<1 x double> [[VRNDX_I]]) +// LLVM: ret <1 x double> [[VRNDX1_I]] + return vrndx_f64(a); +} + +// LLVM-LABEL: @test_vrndxq_f64( +// CIR-LABEL: @vrndxq_f64( +float64x2_t test_vrndxq_f64(float64x2_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !cir.double> +// CIR: cir.rint [[CAST]] : !cir.vector<2 x !cir.double> + +// LLVM-SAME: <2 x double> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x double> [[A]] to <2 x i64> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> +// LLVM: [[VRNDX_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> +// LLVM: [[VRNDX1_I:%.*]] = call <2 x double> @llvm.rint.v2f64(<2 x double> [[VRNDX_I]]) +// LLVM: ret <2 x double> [[VRNDX1_I]] + return vrndxq_f64(a); +} \ No newline at end of file diff --git a/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c b/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c new file mode 100644 index 0000000000000..b95c63c1e611e --- /dev/null +++ b/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c @@ -0,0 +1,132 @@ +// REQUIRES: aarch64-registered-target + +// RUN: %clang_cc1_cg_arm64_neon -target-feature +v8.5a -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=LLVM +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -target-feature +v8.5a -fclangir -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -target-feature +v8.5a -fclangir -emit-cir %s -disable-O0-optnone | FileCheck %s --check-prefixes=CIR %} + +#include <arm_neon.h> + +//===------------------------------------------------------===// +// 2.12.1.1. Rounding +//https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#rounding-3 +//===------------------------------------------------------===// + +// LLVM-LABEL: @test_vrnd32x_f32( +// CIR-LABEL: @vrnd32x_f32( +float32x2_t test_vrnd32x_f32(float32x2_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float> +// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint32x" [[CAST]] : (!cir.vector<2 x !cir.float>) -> !cir.vector<2 x !cir.float> + +// LLVM-SAME: <2 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8> +// LLVM: [[VRND32X_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> +// LLVM: [[VRND32X1_I:%.*]] = call <2 x float> @llvm.aarch64.neon.frint32x.v2f32(<2 x float> [[VRND32X_I]]) + return vrnd32x_f32(a); +} + +// LLVM-LABEL: @test_vrnd32xq_f32( +// CIR-LABEL: @vrnd32xq_f32( +float32x4_t test_vrnd32xq_f32(float32x4_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float> +// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint32x" [[CAST]] : (!cir.vector<4 x !cir.float>) -> !cir.vector<4 x !cir.float> + +// LLVM-SAME: <4 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// LLVM: [[VRND32XQ_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> +// LLVM: [[VRND32XQ1_I:%.*]] = call <4 x float> @llvm.aarch64.neon.frint32x.v4f32(<4 x float> [[VRND32XQ_I]]) + return vrnd32xq_f32(a); +} + +// LLVM-LABEL: @test_vrnd32z_f32( +// CIR-LABEL: @vrnd32z_f32( +float32x2_t test_vrnd32z_f32(float32x2_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float> +// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint32z" [[CAST]] : (!cir.vector<2 x !cir.float>) -> !cir.vector<2 x !cir.float> + +// LLVM-SAME: <2 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8> +// LLVM: [[VRND32Z_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> +// LLVM: [[VRND32Z1_I:%.*]] = call <2 x float> @llvm.aarch64.neon.frint32z.v2f32(<2 x float> [[VRND32Z_I]]) + return vrnd32z_f32(a); +} + +// LLVM-LABEL: @test_vrnd32zq_f32( +// CIR-LABEL: @vrnd32zq_f32( +float32x4_t test_vrnd32zq_f32(float32x4_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float> +// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint32z" [[CAST]] : (!cir.vector<4 x !cir.float>) -> !cir.vector<4 x !cir.float> + +// LLVM-SAME: <4 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// LLVM: [[VRND32ZQ_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> +// LLVM: [[VRND32ZQ1_I:%.*]] = call <4 x float> @llvm.aarch64.neon.frint32z.v4f32(<4 x float> [[VRND32ZQ_I]]) + return vrnd32zq_f32(a); +} + +// LLVM-LABEL: @test_vrnd64x_f32( +// CIR-LABEL: @vrnd64x_f32( +float32x2_t test_vrnd64x_f32(float32x2_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float> +// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint64x" [[CAST]] : (!cir.vector<2 x !cir.float>) -> !cir.vector<2 x !cir.float> + +// LLVM-SAME: <2 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8> +// LLVM: [[VRND64X_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> +// LLVM: [[VRND64X1_I:%.*]] = call <2 x float> @llvm.aarch64.neon.frint64x.v2f32(<2 x float> [[VRND64X_I]]) + return vrnd64x_f32(a); +} + +// LLVM-LABEL: @test_vrnd64xq_f32( +// CIR-LABEL: @vrnd64xq_f32( +float32x4_t test_vrnd64xq_f32(float32x4_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float> +// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint64x" [[CAST]] : (!cir.vector<4 x !cir.float>) -> !cir.vector<4 x !cir.float> + +// LLVM-SAME: <4 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// LLVM: [[VRND64XQ_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> +// LLVM: [[VRND64XQ1_I:%.*]] = call <4 x float> @llvm.aarch64.neon.frint64x.v4f32(<4 x float> [[VRND64XQ_I]]) + return vrnd64xq_f32(a); +} + +// LLVM-LABEL: @test_vrnd64z_f32( +// CIR-LABEL: @vrnd64z_f32( +float32x2_t test_vrnd64z_f32(float32x2_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<8 x !s8i> -> !cir.vector<2 x !cir.float> +// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint64z" [[CAST]] : (!cir.vector<2 x !cir.float>) -> !cir.vector<2 x !cir.float> + +// LLVM-SAME: <2 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8> +// LLVM: [[VRND64Z_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> +// LLVM: [[VRND64Z1_I:%.*]] = call <2 x float> @llvm.aarch64.neon.frint64z.v2f32(<2 x float> [[VRND64Z_I]]) + return vrnd64z_f32(a); +} + +// LLVM-LABEL: @test_vrnd64zq_f32( +// CIR-LABEL: @vrnd64zq_f32( +float32x4_t test_vrnd64zq_f32(float32x4_t a) { +// CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> +// CIR: [[CAST:%.*]] = cir.cast bitcast [[LOAD]] : !cir.vector<16 x !s8i> -> !cir.vector<4 x !cir.float> +// CIR: cir.call_llvm_intrinsic "aarch64.neon.frint64z" [[CAST]] : (!cir.vector<4 x !cir.float>) -> !cir.vector<4 x !cir.float> + +// LLVM-SAME: <4 x float> noundef [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> +// LLVM: [[VRND64ZQ_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> +// LLVM: [[VRND64ZQ1_I:%.*]] = call <4 x float> @llvm.aarch64.neon.frint64z.v4f32(<4 x float> [[VRND64ZQ_I]]) + return vrnd64zq_f32(a); +} diff --git a/clang/test/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c b/clang/test/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c index 0138fad1a7792..418e01079fb43 100644 --- a/clang/test/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c +++ b/clang/test/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c @@ -8,136 +8,8 @@ #include <arm_neon.h> -// CHECK-LABEL: define dso_local <2 x float> @test_vrnd32x_f32( -// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8> -// CHECK-NEXT: [[VRND32X_F32_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> -// CHECK-NEXT: [[VRND32X_F321_I:%.*]] = call <2 x float> @llvm.aarch64.neon.frint32x.v2f32(<2 x float> [[VRND32X_F32_I]]) -// CHECK-NEXT: [[VRND32X_F322_I:%.*]] = bitcast <2 x float> [[VRND32X_F321_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRND32X_F322_I]] to <2 x i32> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <2 x float> -// CHECK-NEXT: ret <2 x float> [[TMP3]] -// -float32x2_t test_vrnd32x_f32(float32x2_t a) { - return vrnd32x_f32(a); -} - -// CHECK-LABEL: define dso_local <4 x float> @test_vrnd32xq_f32( -// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> -// CHECK-NEXT: [[VRND32XQ_F32_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> -// CHECK-NEXT: [[VRND32XQ_F321_I:%.*]] = call <4 x float> @llvm.aarch64.neon.frint32x.v4f32(<4 x float> [[VRND32XQ_F32_I]]) -// CHECK-NEXT: [[VRND32XQ_F322_I:%.*]] = bitcast <4 x float> [[VRND32XQ_F321_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRND32XQ_F322_I]] to <4 x i32> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to <4 x float> -// CHECK-NEXT: ret <4 x float> [[TMP3]] -// -float32x4_t test_vrnd32xq_f32(float32x4_t a) { - return vrnd32xq_f32(a); -} - -// CHECK-LABEL: define dso_local <2 x float> @test_vrnd32z_f32( -// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8> -// CHECK-NEXT: [[VRND32Z_F32_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> -// CHECK-NEXT: [[VRND32Z_F321_I:%.*]] = call <2 x float> @llvm.aarch64.neon.frint32z.v2f32(<2 x float> [[VRND32Z_F32_I]]) -// CHECK-NEXT: [[VRND32Z_F322_I:%.*]] = bitcast <2 x float> [[VRND32Z_F321_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRND32Z_F322_I]] to <2 x i32> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <2 x float> -// CHECK-NEXT: ret <2 x float> [[TMP3]] -// -float32x2_t test_vrnd32z_f32(float32x2_t a) { - return vrnd32z_f32(a); -} - -// CHECK-LABEL: define dso_local <4 x float> @test_vrnd32zq_f32( -// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> -// CHECK-NEXT: [[VRND32ZQ_F32_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> -// CHECK-NEXT: [[VRND32ZQ_F321_I:%.*]] = call <4 x float> @llvm.aarch64.neon.frint32z.v4f32(<4 x float> [[VRND32ZQ_F32_I]]) -// CHECK-NEXT: [[VRND32ZQ_F322_I:%.*]] = bitcast <4 x float> [[VRND32ZQ_F321_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRND32ZQ_F322_I]] to <4 x i32> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to <4 x float> -// CHECK-NEXT: ret <4 x float> [[TMP3]] -// -float32x4_t test_vrnd32zq_f32(float32x4_t a) { - return vrnd32zq_f32(a); -} - -// CHECK-LABEL: define dso_local <2 x float> @test_vrnd64x_f32( -// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8> -// CHECK-NEXT: [[VRND64X_F32_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> -// CHECK-NEXT: [[VRND64X_F321_I:%.*]] = call <2 x float> @llvm.aarch64.neon.frint64x.v2f32(<2 x float> [[VRND64X_F32_I]]) -// CHECK-NEXT: [[VRND64X_F322_I:%.*]] = bitcast <2 x float> [[VRND64X_F321_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRND64X_F322_I]] to <2 x i32> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <2 x float> -// CHECK-NEXT: ret <2 x float> [[TMP3]] -// -float32x2_t test_vrnd64x_f32(float32x2_t a) { - return vrnd64x_f32(a); -} - -// CHECK-LABEL: define dso_local <4 x float> @test_vrnd64xq_f32( -// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> -// CHECK-NEXT: [[VRND64XQ_F32_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> -// CHECK-NEXT: [[VRND64XQ_F321_I:%.*]] = call <4 x float> @llvm.aarch64.neon.frint64x.v4f32(<4 x float> [[VRND64XQ_F32_I]]) -// CHECK-NEXT: [[VRND64XQ_F322_I:%.*]] = bitcast <4 x float> [[VRND64XQ_F321_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRND64XQ_F322_I]] to <4 x i32> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to <4 x float> -// CHECK-NEXT: ret <4 x float> [[TMP3]] -// -float32x4_t test_vrnd64xq_f32(float32x4_t a) { - return vrnd64xq_f32(a); -} - -// CHECK-LABEL: define dso_local <2 x float> @test_vrnd64z_f32( -// CHECK-SAME: <2 x float> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8> -// CHECK-NEXT: [[VRND64Z_F32_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> -// CHECK-NEXT: [[VRND64Z_F321_I:%.*]] = call <2 x float> @llvm.aarch64.neon.frint64z.v2f32(<2 x float> [[VRND64Z_F32_I]]) -// CHECK-NEXT: [[VRND64Z_F322_I:%.*]] = bitcast <2 x float> [[VRND64Z_F321_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRND64Z_F322_I]] to <2 x i32> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <2 x float> -// CHECK-NEXT: ret <2 x float> [[TMP3]] -// -float32x2_t test_vrnd64z_f32(float32x2_t a) { - return vrnd64z_f32(a); -} - -// CHECK-LABEL: define dso_local <4 x float> @test_vrnd64zq_f32( -// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> -// CHECK-NEXT: [[VRND64ZQ_F32_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> -// CHECK-NEXT: [[VRND64ZQ_F321_I:%.*]] = call <4 x float> @llvm.aarch64.neon.frint64z.v4f32(<4 x float> [[VRND64ZQ_F32_I]]) -// CHECK-NEXT: [[VRND64ZQ_F322_I:%.*]] = bitcast <4 x float> [[VRND64ZQ_F321_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRND64ZQ_F322_I]] to <4 x i32> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to <4 x float> -// CHECK-NEXT: ret <4 x float> [[TMP3]] -// -float32x4_t test_vrnd64zq_f32(float32x4_t a) { - return vrnd64zq_f32(a); -} - // CHECK-LABEL: define dso_local <1 x double> @test_vrnd32x_f64( -// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-SAME: <1 x double> noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[A]] to i64 // CHECK-NEXT: [[__P0_ADDR_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i32 0 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
