[clang] [llvm] [RISCV] Add support for vector registers with -fzero-call-used-regs (PR #206206)

[Luke Lau via cfe-commits]

================
@@ -6069,6 +6069,11 @@ foreach lmul = MxList in {
   }
 }
 
+// Used by -fzero-call-used-regs to zero out registers.
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def PseudoClearVR : Pseudo<(outs VR:$vd), (ins), []>,
+                    PseudoInstExpansion<(VMV_V_I VR:$vd, 0)>;
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lukel97 wrote:

Thanks for the explanation, avoiding DCE makes sense. Probably better to have 
the pseudo to be consistent with the other register classes anyway.

https://github.com/llvm/llvm-project/pull/206206
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