https://github.com/doru1004 updated https://github.com/llvm/llvm-project/pull/208557
>From b99852cc62e65a9f50b7745f71f4680fca7b5828 Mon Sep 17 00:00:00 2001 From: Gheorghe-Teodor Bercea <[email protected]> Date: Thu, 9 Jul 2026 15:46:01 -0500 Subject: [PATCH] Introduce address space 13 for VGPR as memory --- clang/test/CodeGen/target-data.c | 4 +- clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl | 2 +- llvm/docs/AMDGPUUsage.rst | 19 ++++- llvm/include/llvm/Support/AMDGPUAddrSpace.h | 5 ++ llvm/lib/IR/AutoUpgrade.cpp | 4 + llvm/lib/IR/VerifierAMDGPU.cpp | 12 ++- llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 1 + llvm/lib/TargetParser/TargetDataLayout.cpp | 3 +- llvm/test/Verifier/AMDGPU/alloca.ll | 75 ++++++++++++------- .../Bitcode/DataLayoutUpgradeTest.cpp | 38 +++++----- 10 files changed, 110 insertions(+), 53 deletions(-) diff --git a/clang/test/CodeGen/target-data.c b/clang/test/CodeGen/target-data.c index a5e0b814c7042..f03aaba8b53dd 100644 --- a/clang/test/CodeGen/target-data.c +++ b/clang/test/CodeGen/target-data.c @@ -160,12 +160,12 @@ // RUN: %clang_cc1 -triple amdgcn-unknown -target-cpu hawaii -o - -emit-llvm %s \ // RUN: | FileCheck %s -check-prefix=R600SI -// R600SI: target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" +// R600SI: target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p13:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" // Test default -target-cpu // RUN: %clang_cc1 -triple amdgcn-unknown -o - -emit-llvm %s \ // RUN: | FileCheck %s -check-prefix=R600SIDefault -// R600SIDefault: target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" +// R600SIDefault: target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p13:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" // RUN: %clang_cc1 -triple arm64-unknown -o - -emit-llvm %s | \ // RUN: FileCheck %s -check-prefix=AARCH64 diff --git a/clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl b/clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl index 72ce72644b8ea..f120db1aaf6cd 100644 --- a/clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl +++ b/clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl @@ -1,5 +1,5 @@ // RUN: %clang_cc1 %s -O0 -triple amdgcn -emit-llvm -o - | FileCheck %s // RUN: %clang_cc1 %s -O0 -triple amdgcn---opencl -emit-llvm -o - | FileCheck %s -// CHECK: target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" +// CHECK: target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p13:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" void foo(void) {} diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index cbe9d15074457..a055f72fdfded 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -1118,7 +1118,7 @@ supported for the ``amdgcn`` target. *reserved for future use* 10 *reserved for future use* 11 *reserved for downstream use (LLPC)* 12 - *reserved for future use* 13 + VGPR 13 N/A VGPR 32 0xFFFFFFFF *reserved for future use* 14 *reserved for future use* 16 Streamout Registers 128 N/A GS_REGS @@ -1333,6 +1333,23 @@ supported for the ``amdgcn`` target. a buffer strided pointer, this means that the base pointer is ``align(4)``, that the offset is a multiple of 4 bytes, and that the stride is a multiple of 4. +**VGPR** + The VGPR address space presents a memory view of the wave's vector registers. + The 32-bit address is a byte address into the thread's view of vector + registers. For example, loading 4 bytes from address ``12`` reads the contents + of ``v3``. Storing 8 bytes to address ``32`` overwrites the contents of + ``v[8:9]``. + + Use of this address space by frontends is strongly discouraged. It has unusual + and subtle lifetime rules due to the potential for interaction with normal + register allocation. It exists primarily for internal purposes of the backend, + such as promoting ``alloca`` instructions from the private address space into + VGPRs. + + In particular, memory in this address space that was allocated by an + ``alloca`` is not visible while in a called function. Attempting to dereference + a pointer to such memory in a called function is undefined behavior. + **Streamout Registers** Dedicated registers used by the GS NGG Streamout Instructions. The register file is modelled as a memory in a distinct address space because it is indexed diff --git a/llvm/include/llvm/Support/AMDGPUAddrSpace.h b/llvm/include/llvm/Support/AMDGPUAddrSpace.h index 01b1510524d0f..b1af8047ce580 100644 --- a/llvm/include/llvm/Support/AMDGPUAddrSpace.h +++ b/llvm/include/llvm/Support/AMDGPUAddrSpace.h @@ -47,6 +47,11 @@ enum : unsigned { BUFFER_STRIDED_POINTER = 9, ///< Address space for 192-bit fat buffer ///< pointers with an additional index. + VGPR = 13, ///< Address space for VGPRs. The 32-bit address is a byte offset + ///< into the wave's view of its vector registers. Note this shares + ///< its numeric value with CONSTANT_BUFFER_5, which is only used + ///< by the (graphics) R600 path. + RESERVED_ADDRESS_SPACE_16 = 16, ///< Reserved for downstream use. /// Internal address spaces. Can be freely renumbered. diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp index 880350a1b159b..932b7c79789b6 100644 --- a/llvm/lib/IR/AutoUpgrade.cpp +++ b/llvm/lib/IR/AutoUpgrade.cpp @@ -7075,6 +7075,10 @@ std::string llvm::UpgradeDataLayoutString(StringRef DL, StringRef TT) { Res.replace(Res.find(OldP8), OldP8.size(), "-p8:128:128:128:48-"); if (!DL.contains("-p9") && !DL.starts_with("p9")) Res.append("-p9:192:256:256:32"); + // Add sizing for the VGPR address space (32-bit byte offset into the + // wave's vector registers). + if (!DL.contains("-p13") && !DL.starts_with("p13")) + Res.append("-p13:32:32"); } // Upgrade the ELF mangling mode. diff --git a/llvm/lib/IR/VerifierAMDGPU.cpp b/llvm/lib/IR/VerifierAMDGPU.cpp index 04cb214ef2520..a9cbdc20ace35 100644 --- a/llvm/lib/IR/VerifierAMDGPU.cpp +++ b/llvm/lib/IR/VerifierAMDGPU.cpp @@ -122,8 +122,16 @@ void llvm::verifyAMDGPUAlloca(VerifierSupport &VS, const AllocaInst &AI) { if (!VS.TT.isAMDGPU()) return; - if (AI.getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) - VS.CheckFailed("alloca on amdgpu must be in addrspace(5)", &AI); + if (AI.getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS && + AI.getAddressSpace() != AMDGPUAS::VGPR) + VS.CheckFailed("alloca on amdgpu must be in addrspace(5) or addrspace(13)", + &AI); + + // Only static allocas can live in VGPRs; a dynamically sized one has no + // register-file representation. (Other address spaces are already rejected + // above, so this only adds the more specific diagnostic for addrspace(13).) + if (!AI.isStaticAlloca() && AI.getAddressSpace() == AMDGPUAS::VGPR) + VS.CheckFailed("dynamic alloca on amdgpu must be in addrspace(5)", &AI); } bool llvm::isAMDGPUCallBrIntrinsic(Intrinsic::ID ID) { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td index 2387afe1cd362..aa06e49c68e03 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td @@ -19,6 +19,7 @@ def AddrSpaces { int Constant = 4; int Private = 5; int Constant32Bit = 6; + int VGPR = 13; } diff --git a/llvm/lib/TargetParser/TargetDataLayout.cpp b/llvm/lib/TargetParser/TargetDataLayout.cpp index 18f0c13907e52..e11f65f6cd4bd 100644 --- a/llvm/lib/TargetParser/TargetDataLayout.cpp +++ b/llvm/lib/TargetParser/TargetDataLayout.cpp @@ -274,7 +274,8 @@ static std::string computeAMDDataLayout(const Triple &TT) { // space 8) which cannot be non-trivilally accessed by LLVM memory operations // like getelementptr. return "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32" - "-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-" + "-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p13:32:32-" + "i64:64-" "v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-" "v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"; } diff --git a/llvm/test/Verifier/AMDGPU/alloca.ll b/llvm/test/Verifier/AMDGPU/alloca.ll index f31d6228d7936..24b422a37bd7d 100644 --- a/llvm/test/Verifier/AMDGPU/alloca.ll +++ b/llvm/test/Verifier/AMDGPU/alloca.ll @@ -2,23 +2,25 @@ target triple = "amdgcn-amd-amdhsa" -; CHECK: alloca on amdgpu must be in addrspace(5) +; A static alloca is allowed in addrspace(5) (private) and addrspace(13) (VGPR); +; any other address space is rejected. +; CHECK: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.0 = alloca i32, align 4 -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.1 = alloca i32, align 4, addrspace(1) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.2 = alloca i32, align 4, addrspace(2) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.3 = alloca i32, align 4, addrspace(3) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.4 = alloca i32, align 4, addrspace(4) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.6 = alloca i32, align 4, addrspace(6) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.7 = alloca i32, align 4, addrspace(7) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.8 = alloca i32, align 4, addrspace(8) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.9 = alloca i32, align 4, addrspace(9) define void @static_alloca() { entry: @@ -32,27 +34,32 @@ entry: %alloca.7 = alloca i32, align 4, addrspace(7) %alloca.8 = alloca i32, align 4, addrspace(8) %alloca.9 = alloca i32, align 4, addrspace(9) + %alloca.13 = alloca i32, align 4, addrspace(13) ret void } -; CHECK: alloca on amdgpu must be in addrspace(5) +; A dynamically sized alloca is only allowed in addrspace(5); addrspace(13) is +; rejected because it has no register-file representation. +; CHECK: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.0 = alloca i32, i32 %n, align 4 -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.1 = alloca i32, i32 %n, align 4, addrspace(1) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.2 = alloca i32, i32 %n, align 4, addrspace(2) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.3 = alloca i32, i32 %n, align 4, addrspace(3) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.4 = alloca i32, i32 %n, align 4, addrspace(4) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.6 = alloca i32, i32 %n, align 4, addrspace(6) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.7 = alloca i32, i32 %n, align 4, addrspace(7) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.8 = alloca i32, i32 %n, align 4, addrspace(8) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.9 = alloca i32, i32 %n, align 4, addrspace(9) +; CHECK-NEXT: dynamic alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: %alloca.13 = alloca i32, i32 %n, align 4, addrspace(13) define void @dynamic_alloca_i32(i32 %n) { entry: %alloca.0 = alloca i32, i32 %n, align 4 @@ -65,26 +72,27 @@ entry: %alloca.7 = alloca i32, i32 %n, align 4, addrspace(7) %alloca.8 = alloca i32, i32 %n, align 4, addrspace(8) %alloca.9 = alloca i32, i32 %n, align 4, addrspace(9) + %alloca.13 = alloca i32, i32 %n, align 4, addrspace(13) ret void } -; CHECK: alloca on amdgpu must be in addrspace(5) +; CHECK: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.0 = alloca i32, i64 %n, align 4 -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.1 = alloca i32, i64 %n, align 4, addrspace(1) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.2 = alloca i32, i64 %n, align 4, addrspace(2) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.3 = alloca i32, i64 %n, align 4, addrspace(3) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.4 = alloca i32, i64 %n, align 4, addrspace(4) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.6 = alloca i32, i64 %n, align 4, addrspace(6) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.7 = alloca i32, i64 %n, align 4, addrspace(7) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.8 = alloca i32, i64 %n, align 4, addrspace(8) -; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: alloca on amdgpu must be in addrspace(5) or addrspace(13) ; CHECK-NEXT: %alloca.9 = alloca i32, i64 %n, align 4, addrspace(9) define void @dynamic_alloca_i64(i64 %n) { entry: @@ -100,3 +108,16 @@ entry: %alloca.9 = alloca i32, i64 %n, align 4, addrspace(9) ret void } + +; A static alloca that is not in the entry block is treated as dynamic, so +; addrspace(13) is rejected there too. +; CHECK: dynamic alloca on amdgpu must be in addrspace(5) +; CHECK-NEXT: %alloca.13 = alloca i32, align 4, addrspace(13) +define void @nonentry_alloca() { +entry: + br label %nonentry + +nonentry: + %alloca.13 = alloca i32, align 4, addrspace(13) + ret void +} diff --git a/llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp b/llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp index a082adbf6565e..0ec3c753c10f1 100644 --- a/llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp +++ b/llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp @@ -43,14 +43,14 @@ TEST(DataLayoutUpgradeTest, ValidDataLayoutUpgrade) { // and that ANDGCN adds p7 and p8 as well. EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64", "amdgcn"), "m:e-e-p:64:64-G1-ni:7:8:9-p7:160:256:256:32-p8:128:128:128:48-p9:" - "192:256:256:32"); + "192:256:256:32-p13:32:32"); EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64-G1", "amdgcn"), "m:e-e-p:64:64-G1-ni:7:8:9-p7:160:256:256:32-p8:128:128:128:48-p9:" - "192:256:256:32"); + "192:256:256:32-p13:32:32"); // Check that the old AMDGCN p8:128:128 definition is upgraded EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64-p8:128:128-G1", "amdgcn"), "m:e-e-p:64:64-p8:128:128:128:48-G1-ni:7:8:9-p7:160:256:256:32-p9:" - "192:256:256:32"); + "192:256:256:32-p13:32:32"); // but that r600 does not. EXPECT_EQ(UpgradeDataLayoutString("e-p:32:32-G1", "r600"), "m:e-e-p:32:32-G1"); @@ -66,7 +66,7 @@ TEST(DataLayoutUpgradeTest, ValidDataLayoutUpgrade) { "m:e-e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:" "64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:" "1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9-p7:160:256:256:32-p8:128:128:" - "128:48-p9:192:256:256:32"); + "128:48-p9:192:256:256:32-p13:32:32"); // Check that SystemZ adds -S64 if needed. EXPECT_EQ(UpgradeDataLayoutString( @@ -158,24 +158,24 @@ TEST(DataLayoutUpgradeTest, NoDataLayoutUpgrade) { EXPECT_EQ(UpgradeDataLayoutString("G2", "r600"), "m:e-G2"); EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64-G2", "amdgcn"), "m:e-e-p:64:64-G2-ni:7:8:9-p7:160:256:256:32-p8:128:128:128:48-p9:" - "192:256:256:32"); + "192:256:256:32-p13:32:32"); EXPECT_EQ(UpgradeDataLayoutString("G2-e-p:64:64", "amdgcn"), "m:e-G2-e-p:64:64-ni:7:8:9-p7:160:256:256:32-p8:128:128:128:48-p9:" - "192:256:256:32"); + "192:256:256:32-p13:32:32"); EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64-G0", "amdgcn"), "m:e-e-p:64:64-G0-ni:7:8:9-p7:160:256:256:32-p8:128:128:128:48-p9:" - "192:256:256:32"); + "192:256:256:32-p13:32:32"); // Check that AMDGCN targets don't add already declared address space 7. - EXPECT_EQ( - UpgradeDataLayoutString("e-p:64:64-p7:64:64", "amdgcn"), - "m:e-e-p:64:64-p7:64:64-G1-ni:7:8:9-p8:128:128:128:48-p9:192:256:256:32"); - EXPECT_EQ( - UpgradeDataLayoutString("p7:64:64-G2-e-p:64:64", "amdgcn"), - "m:e-p7:64:64-G2-e-p:64:64-ni:7:8:9-p8:128:128:128:48-p9:192:256:256:32"); - EXPECT_EQ( - UpgradeDataLayoutString("e-p:64:64-p7:64:64-G1", "amdgcn"), - "m:e-e-p:64:64-p7:64:64-G1-ni:7:8:9-p8:128:128:128:48-p9:192:256:256:32"); + EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64-p7:64:64", "amdgcn"), + "m:e-e-p:64:64-p7:64:64-G1-ni:7:8:9-p8:128:128:128:48-p9:192:256:" + "256:32-p13:32:32"); + EXPECT_EQ(UpgradeDataLayoutString("p7:64:64-G2-e-p:64:64", "amdgcn"), + "m:e-p7:64:64-G2-e-p:64:64-ni:7:8:9-p8:128:128:128:48-p9:192:256:" + "256:32-p13:32:32"); + EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64-p7:64:64-G1", "amdgcn"), + "m:e-e-p:64:64-p7:64:64-G1-ni:7:8:9-p8:128:128:128:48-p9:192:256:" + "256:32-p13:32:32"); // Check that SPIR & SPIRV targets don't add -G1 if there is already a -G // flag. @@ -216,9 +216,9 @@ TEST(DataLayoutUpgradeTest, EmptyDataLayout) { // Check that AMDGPU targets add G1 if it's not present. EXPECT_EQ(UpgradeDataLayoutString("", "r600"), "m:e-G1"); - EXPECT_EQ( - UpgradeDataLayoutString("", "amdgcn"), - "m:e-G1-ni:7:8:9-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32"); + EXPECT_EQ(UpgradeDataLayoutString("", "amdgcn"), + "m:e-G1-ni:7:8:9-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:" + "256:32-p13:32:32"); // Check that SPIR & SPIRV targets add G1 if it's not present. EXPECT_EQ(UpgradeDataLayoutString("", "spir"), "G1"); _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
