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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
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<details>
<summary>
You can test this locally with the following command:
</summary>
``````````bash
git-clang-format --diff origin/main HEAD --extensions h,cpp --
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp
llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
llvm/lib/Target/SPIRV/SPIRVUtils.cpp llvm/lib/Target/SPIRV/SPIRVUtils.h
--diff_from_common_commit
``````````
:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:
</details>
<details>
<summary>
View the diff from clang-format here.
</summary>
``````````diff
diff --git a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
index 792214b54..8f8d22574 100644
--- a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
@@ -1351,9 +1351,9 @@ bool
SPIRVEmitIntrinsics::deduceOperandElementTypeFunctionRet(
continue;
if (CallInst *AssignCI = GR->findAssignPtrTypeInstr(CI)) {
if (Type *PrevElemTy = GR->findDeducedElementType(CI)) {
- GR->updateAssignType(AssignCI, CI,
- getNormalizedPoisonValue(OpElemTy,
- CanUseAnyVectorRank));
+ GR->updateAssignType(
+ AssignCI, CI,
+ getNormalizedPoisonValue(OpElemTy, CanUseAnyVectorRank));
propagateElemType(CI, PrevElemTy, VisitedSubst);
}
}
@@ -1547,8 +1547,8 @@ void SPIRVEmitIntrinsics::deduceOperandElementType(
if (Op->hasUseList() && !WouldClobberPtrWithNonPtr &&
(!Ty || AskTy || isUntypedPointerTy(Ty) || isTodoType(Op))) {
Type *PrevElemTy = GR->findDeducedElementType(Op);
- GR->addDeducedElementType(Op, normalizeType(KnownElemTy,
- CanUseAnyVectorRank));
+ GR->addDeducedElementType(
+ Op, normalizeType(KnownElemTy, CanUseAnyVectorRank));
// check if KnownElemTy is complete
if (!Incomplete)
eraseTodoType(Op);
@@ -2165,8 +2165,8 @@ void
SPIRVEmitIntrinsics::replacePointerOperandWithPtrCast(
return;
setInsertPointSkippingPhis(B, I);
- Value *ExpectedElementVal = getNormalizedPoisonValue(ExpectedElementType,
- CanUseAnyVectorRank);
+ Value *ExpectedElementVal =
+ getNormalizedPoisonValue(ExpectedElementType, CanUseAnyVectorRank);
MetadataAsValue *VMD = buildMD(ExpectedElementVal);
unsigned AddressSpace = getPointerAddressSpace(Pointer->getType());
bool FirstPtrCastOrAssignPtrType = true;
@@ -2931,11 +2931,10 @@ void
SPIRVEmitIntrinsics::insertAssignTypeIntrs(Instruction *I,
// types are handled in `processInstrAfterVisit`
OpTyVal = getNormalizedPoisonValue(OpTy, CanUseAnyVectorRank);
}
- CallInst *AssignCI =
- buildIntrWithMD(Intrinsic::spv_assign_type, {OpTy},
- getNormalizedPoisonValue(OpTy,
- CanUseAnyVectorRank),
- OpTyVal, {}, B);
+ CallInst *AssignCI = buildIntrWithMD(
+ Intrinsic::spv_assign_type, {OpTy},
+ getNormalizedPoisonValue(OpTy, CanUseAnyVectorRank), OpTyVal, {},
+ B);
GR->addAssignPtrTypeInstr(OpTyVal, AssignCI);
}
}
@@ -3479,8 +3478,8 @@ bool SPIRVEmitIntrinsics::processFunctionPointers(Module
&M) {
for (Function *F : Worklist) {
SmallVector<Value *> Args;
for (const auto &Arg : F->args())
- Args.push_back(getNormalizedPoisonValue(Arg.getType(),
- CanUseAnyVectorRank));
+ Args.push_back(
+ getNormalizedPoisonValue(Arg.getType(), CanUseAnyVectorRank));
IRB.CreateCall(F, Args);
}
IRB.CreateRetVoid();
@@ -3514,8 +3513,8 @@ void
SPIRVEmitIntrinsics::applyDemangledPtrArgTypes(IRBuilder<> &B) {
replaceUsesOfWithSpvPtrcast(
Param, normalizeType(ElemTy, CanUseAnyVectorRank), CI, Ptrcasts);
} else if (isa<Instruction>(Param)) {
- GR->addDeducedElementType(Param, normalizeType(ElemTy,
- CanUseAnyVectorRank));
+ GR->addDeducedElementType(Param,
+ normalizeType(ElemTy,
CanUseAnyVectorRank));
// insertAssignTypeIntrs() will complete buildAssignPtr()
} else {
B.SetInsertPoint(CI->getParent()
@@ -3658,8 +3657,8 @@ bool SPIRVEmitIntrinsics::runOnFunction(Function &Func) {
if (SGEP) {
GR->addDeducedElementType(
- SGEP, normalizeType(SGEP->getResultElementType(),
- CanUseAnyVectorRank));
+ SGEP,
+ normalizeType(SGEP->getResultElementType(), CanUseAnyVectorRank));
continue;
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index 11166a3d6..ec961ed4d 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -324,10 +324,9 @@ const MachineInstr
*SPIRVGlobalRegistry::createConstOrTypeAtFunctionEntry(
return ConstOrType;
}
-SPIRVTypeInst
-SPIRVGlobalRegistry::getOpTypeVectorImpl(
- uint32_t NumElems, SPIRVTypeInst ElemType,
- MachineIRBuilder &MIRBuilder, bool IsLongVector) {
+SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeVectorImpl(
+ uint32_t NumElems, SPIRVTypeInst ElemType, MachineIRBuilder &MIRBuilder,
+ bool IsLongVector) {
auto EleOpc = ElemType->getOpcode();
if (EleOpc == SPIRV::OpTypePointer) {
if (!cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget())
@@ -348,8 +347,9 @@ SPIRVGlobalRegistry::getOpTypeVectorImpl(
return createConstOrTypeAtFunctionEntry(
MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
- return MIRBuilder.buildInstr(IsLongVector ? SPIRV::OpTypeVectorIdEXT
- : SPIRV::OpTypeVector)
+ return MIRBuilder
+ .buildInstr(IsLongVector ? SPIRV::OpTypeVectorIdEXT
+ : SPIRV::OpTypeVector)
.addDef(createTypeVReg(MIRBuilder))
.addUse(getSPIRVTypeID(ElemType))
.addImm(NumElems);
@@ -363,8 +363,7 @@ SPIRVGlobalRegistry::getOpTypeVector(uint32_t NumElems,
SPIRVTypeInst ElemType,
return getOpTypeVectorImpl(NumElems, ElemType, MIRBuilder);
}
-SPIRVTypeInst
-SPIRVGlobalRegistry::getOpTypeVectorIdEXT(
+SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeVectorIdEXT(
uint32_t NumElems, SPIRVTypeInst ElemType, MachineIRBuilder &MIRBuilder) {
assert((NumElems < 2 || NumElems > 16 ||
(NumElems != 3 && NumElems != 4 && NumElems != 8)) &&
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 93e56ebab..1e0522973 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -1239,13 +1239,13 @@ bool SPIRVInstructionSelector::spvSelect(Register
ResVReg,
return selectFrexp(ResVReg, ResType, I);
case TargetOpcode::G_UADDO:
- return selectOverflowArith(ResVReg, ResType, I, isVectorType(ResType)
- ? SPIRV::OpIAddCarryV
- : SPIRV::OpIAddCarryS);
+ return selectOverflowArith(ResVReg, ResType, I,
+ isVectorType(ResType) ? SPIRV::OpIAddCarryV
+ : SPIRV::OpIAddCarryS);
case TargetOpcode::G_USUBO:
- return selectOverflowArith(ResVReg, ResType, I, isVectorType(ResType)
- ? SPIRV::OpISubBorrowV
- :
SPIRV::OpISubBorrowS);
+ return selectOverflowArith(ResVReg, ResType, I,
+ isVectorType(ResType) ? SPIRV::OpISubBorrowV
+ : SPIRV::OpISubBorrowS);
case TargetOpcode::G_UMULO:
return selectOverflowArith(ResVReg, ResType, I, SPIRV::OpUMulExtended);
case TargetOpcode::G_SMULO:
@@ -2681,9 +2681,8 @@ bool
SPIRVInstructionSelector::selectOverflowArith(Register ResVReg,
assert(I.getNumDefs() > 1 && "Not enought operands");
SPIRVTypeInst BoolType = GR.getOrCreateSPIRVBoolType(I, TII);
unsigned N = GR.getScalarOrVectorComponentCount(ResType);
- if (N > 1 ||
- (isVectorType(ResType) &&
- STI.canUseExtension(SPIRV::Extension::SPV_EXT_long_vector)))
+ if (N > 1 || (isVectorType(ResType) &&
+ STI.canUseExtension(SPIRV::Extension::SPV_EXT_long_vector)))
BoolType = GR.getOrCreateSPIRVVectorType(BoolType, N, I, TII);
Register BoolTypeReg = GR.getSPIRVTypeID(BoolType);
Register ZeroReg = buildZerosVal(ResType, I);
@@ -3191,7 +3190,7 @@ bool SPIRVInstructionSelector::selectFloatDot(Register
ResVReg,
assert((VecType->getOpcode() == SPIRV::OpTypeVector &&
GR.getScalarOrVectorComponentCount(VecType) > 1) ||
VecType->getOpcode() == SPIRV::OpTypeVectorIdEXT &&
- "dot product requires a vector of at least 2 components");
+ "dot product requires a vector of at least 2 components");
[[maybe_unused]] SPIRVTypeInst EltType =
GR.getScalarOrVectorComponentType(VecType);
@@ -3252,7 +3251,7 @@ bool SPIRVInstructionSelector::selectIntegerDotExpansion(
assert((VecType->getOpcode() == SPIRV::OpTypeVector &&
GR.getScalarOrVectorComponentCount(VecType) > 1) ||
VecType->getOpcode() == SPIRV::OpTypeVectorIdEXT &&
- "dot product requires a vector of at least 2 components");
+ "dot product requires a vector of at least 2 components");
Register Res = MRI->createVirtualRegister(GR.getRegClass(ResType));
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
@@ -3609,8 +3608,8 @@ bool
SPIRVInstructionSelector::selectWaveActiveAllEqual(Register ResVReg,
// Determine if input is vector
unsigned NumElems = GR.getScalarOrVectorComponentCount(InputType);
bool IsVector = NumElems > 1 ||
- (InputType->getOpcode() == SPIRV::OpTypeVectorIdEXT &&
- STI.canUseExtension(SPIRV::Extension::SPV_EXT_long_vector));
+ (InputType->getOpcode() == SPIRV::OpTypeVectorIdEXT &&
+ STI.canUseExtension(SPIRV::Extension::SPV_EXT_long_vector));
// Determine element types
SPIRVTypeInst ElemInputType = GR.getScalarOrVectorComponentType(InputType);
@@ -3901,9 +3900,8 @@ bool
SPIRVInstructionSelector::selectBitreverseViaI32(Register ResVReg,
? SPIRV::OpSConvert
: SPIRV::OpUConvert;
- if (N > 1 ||
- (ResType->getOpcode() == SPIRV::OpTypeVectorIdEXT &&
- STI.canUseExtension(SPIRV::Extension::SPV_EXT_long_vector))) {
+ if (N > 1 || (ResType->getOpcode() == SPIRV::OpTypeVectorIdEXT &&
+ STI.canUseExtension(SPIRV::Extension::SPV_EXT_long_vector))) {
Int32Type = GR.getOrCreateSPIRVVectorType(Int32Type, N, I, TII);
ShiftOp = SPIRV::OpShiftRightLogicalV;
@@ -4110,9 +4108,8 @@ bool SPIRVInstructionSelector::selectBitreverse(Register
ResVReg,
unsigned OrOp = SPIRV::OpBitwiseOrS;
unsigned ShlOp = SPIRV::OpShiftLeftLogicalS;
unsigned ShrOp = SPIRV::OpShiftRightLogicalS;
- if (N > 1 ||
- (ResType->getOpcode() == SPIRV::OpTypeVectorIdEXT &&
- STI.canUseExtension(SPIRV::Extension::SPV_EXT_long_vector))) {
+ if (N > 1 || (ResType->getOpcode() == SPIRV::OpTypeVectorIdEXT &&
+ STI.canUseExtension(SPIRV::Extension::SPV_EXT_long_vector))) {
AndOp = SPIRV::OpBitwiseAndV;
OrOp = SPIRV::OpBitwiseOrV;
ShlOp = SPIRV::OpShiftLeftLogicalV;
@@ -4497,8 +4494,8 @@ bool SPIRVInstructionSelector::selectExp10(Register
ResVReg,
Register ConstReg =
GR.buildConstantFP(ConstVal, MIRBuilder, SpirvScalarType);
Register ArgReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
- auto Opcode = isVectorType(ResType) ? SPIRV::OpVectorTimesScalar
- : SPIRV::OpFMulS;
+ auto Opcode =
+ isVectorType(ResType) ? SPIRV::OpVectorTimesScalar : SPIRV::OpFMulS;
if (!selectOpWithSrcs(ArgReg, ResType, I,
{I.getOperand(1).getReg(), ConstReg}, Opcode))
@@ -4715,9 +4712,8 @@ bool SPIRVInstructionSelector::selectSUCmp(Register
ResVReg,
// Ensure we have bool.
SPIRVTypeInst BoolType = GR.getOrCreateSPIRVBoolType(I, TII);
unsigned N = GR.getScalarOrVectorComponentCount(ResType);
- if (N > 1 ||
- (ResType->getOpcode() == SPIRV::OpTypeVectorIdEXT &&
- STI.canUseExtension(SPIRV::Extension::SPV_EXT_long_vector)))
+ if (N > 1 || (ResType->getOpcode() == SPIRV::OpTypeVectorIdEXT &&
+ STI.canUseExtension(SPIRV::Extension::SPV_EXT_long_vector)))
BoolType = GR.getOrCreateSPIRVVectorType(BoolType, N, I, TII);
Register BoolTypeReg = GR.getSPIRVTypeID(BoolType);
// Build less-than-equal and less-than.
@@ -4746,10 +4742,10 @@ bool SPIRVInstructionSelector::selectSUCmp(Register
ResVReg,
MRI->setType(NegOneOrZeroReg, LLT::scalar(64));
GR.assignSPIRVTypeToVReg(ResType, NegOneOrZeroReg, MIRBuilder.getMF());
unsigned SelectOpcode =
- (N > 1 ||
- (ResType->getOpcode() == SPIRV::OpTypeVectorIdEXT &&
- STI.canUseExtension(SPIRV::Extension::SPV_EXT_long_vector)))
- ? SPIRV::OpSelectVIVCond : SPIRV::OpSelectSISCond;
+ (N > 1 || (ResType->getOpcode() == SPIRV::OpTypeVectorIdEXT &&
+ STI.canUseExtension(SPIRV::Extension::SPV_EXT_long_vector)))
+ ? SPIRV::OpSelectVIVCond
+ : SPIRV::OpSelectSISCond;
BuildMI(BB, I, I.getDebugLoc(), TII.get(SelectOpcode))
.addDef(NegOneOrZeroReg)
.addUse(ResTypeReg)
@@ -4774,8 +4770,8 @@ bool SPIRVInstructionSelector::selectIntToBool(Register
IntReg,
SPIRVTypeInst BoolTy) const {
// To truncate to a bool, we use OpBitwiseAnd 1 and OpINotEqual to zero.
Register BitIntReg = createVirtualRegister(IntTy, &GR, MRI, MRI->getMF());
- unsigned Opcode = isVectorType(IntTy) ? SPIRV::OpBitwiseAndV
- : SPIRV::OpBitwiseAndS;
+ unsigned Opcode =
+ isVectorType(IntTy) ? SPIRV::OpBitwiseAndV : SPIRV::OpBitwiseAndS;
Register Zero = buildZerosVal(IntTy, I);
Register One = buildOnesVal(false, IntTy, I);
MachineBasicBlock &BB = *I.getParent();
@@ -7193,8 +7189,8 @@ bool SPIRVInstructionSelector::selectLog10(Register
ResVReg,
Register ScaleReg = GR.buildConstantFP(ScaleVal, MIRBuilder,
SpirvScalarType);
// Multiply log2(x) by 0.30103 to get log10(x) result.
- auto Opcode = isVectorType(ResType) ? SPIRV::OpVectorTimesScalar
- : SPIRV::OpFMulS;
+ auto Opcode =
+ isVectorType(ResType) ? SPIRV::OpVectorTimesScalar : SPIRV::OpFMulS;
BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
.addDef(ResVReg)
.addUse(GR.getSPIRVTypeID(ResType))
diff --git a/llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
b/llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
index 8ef15cb72..fed6886e5 100644
--- a/llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
@@ -389,8 +389,8 @@ class SPIRVLegalizePointerCastImpl {
bool CanUseAnyVectorRank = TM.getSubtargetImpl()->canUseExtension(
SPIRV::Extension::SPV_EXT_long_vector);
Value *Element = (E == 1 && !CanUseAnyVectorRank)
- ? SrcVector
- : makeExtractElement(B, ElemTy, SrcVector, I);
+ ? SrcVector
+ : makeExtractElement(B, ElemTy, SrcVector, I);
StoreInst *SI = B.CreateStore(Element, ElementPtr);
SI->setAlignment(commonAlignment(Alignment, I * ElemSize));
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index fcbbe3877..0f2bfbeec 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -1629,7 +1629,7 @@ void addInstrRequirements(const MachineInstr &MI,
}
break;
}
- case SPIRV::OpTypeVectorIdEXT : {
+ case SPIRV::OpTypeVectorIdEXT: {
if (!ST.canUseExtension(SPIRV::Extension::SPV_EXT_long_vector))
reportFatalUsageError("OpTypeVectorIdEXT requires the following SPIR-V "
"extension: SPV_EXT_long_vector extension");
diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp
b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp
index e8f2b676e..ae521657b 100644
--- a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp
@@ -973,7 +973,7 @@ Register createVirtualRegister(
bool isVectorType(SPIRVTypeInst SPVTy) {
return SPVTy->getOpcode() == SPIRV::OpTypeVector ||
- SPVTy->getOpcode() == SPIRV::OpTypeVectorIdEXT;
+ SPVTy->getOpcode() == SPIRV::OpTypeVectorIdEXT;
}
CallInst *buildIntrWithMD(Intrinsic::ID IntrID, ArrayRef<Type *> Types,
``````````
</details>
https://github.com/llvm/llvm-project/pull/210279
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