================
@@ -0,0 +1,1636 @@
+// REQUIRES: aarch64-registered-target || arm-registered-target
+
+// RUN: %clang_cc1_cg_arm64_neon -emit-llvm %s
-disable-O0-optnone | opt -S -passes=mem2reg,sroa,instcombine | FileCheck %s
--check-prefix=LLVM
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -fclangir -emit-llvm %s
-disable-O0-optnone | opt -S -passes=mem2reg,sroa,instcombine,simplifycfg |
FileCheck %s --check-prefix=LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -fclangir -emit-cir %s
-disable-O0-optnone | FileCheck %s
--check-prefix=CIR %}
+
+#include <arm_neon.h>
+
+//===------------------------------------------------------===//
+// 2.14.3. Store
+// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#store
+//===------------------------------------------------------===//
+
+// LLVM-LABEL: @test_vst1_f16(
+// CIR-LABEL: @test_vst1_f16(
+void test_vst1_f16(float16_t *a, float16x4_t b) {
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !cir.vector<4 x !cir.f16>,
!cir.ptr<!cir.vector<4 x !cir.f16>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <4 x half> noundef {{.*}}[[B:%.*]])
+// LLVM: store <4 x half> [[B]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1_f16(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_f32(
+// CIR-LABEL: @test_vst1_f32(
+void test_vst1_f32(float32_t *a, float32x2_t b) {
+// CIR: cir.store align(4) {{.*}}, {{.*}} : !cir.vector<2 x !cir.float>,
!cir.ptr<!cir.vector<2 x !cir.float>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <2 x float> noundef {{.*}}[[B:%.*]])
+// LLVM: store <2 x float> [[B]], ptr [[A]], align 4
+// LLVM: ret void
+ vst1_f32(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_f64(
+// CIR-LABEL: @test_vst1_f64(
+void test_vst1_f64(float64_t *a, float64x1_t b) {
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !cir.vector<1 x !cir.double>,
!cir.ptr<!cir.vector<1 x !cir.double>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <1 x double> noundef
{{.*}}[[B:%.*]])
+// LLVM: store <1 x double> [[B]], ptr [[A]], align 8
+// LLVM: ret void
+ vst1_f64(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_mf8(
+// CIR-LABEL: @test_vst1_mf8(
+void test_vst1_mf8(mfloat8_t *a, mfloat8x8_t val) {
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !cir.vector<8 x !u8i>,
!cir.ptr<!cir.vector<8 x !u8i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]])
+// LLVM: store <8 x i8> [[B]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1_mf8(a, val);
+}
+
+// LLVM-LABEL: @test_vst1_p16(
+// CIR-LABEL: @test_vst1_p16(
+void test_vst1_p16(poly16_t *a, poly16x4_t b) {
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !cir.vector<4 x !s16i>,
!cir.ptr<!cir.vector<4 x !s16i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <4 x i16> noundef {{.*}}[[B:%.*]])
+// LLVM: store <4 x i16> [[B]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1_p16(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_p64(
+// CIR-LABEL: @test_vst1_p64(
+void test_vst1_p64(poly64_t * ptr, poly64x1_t val) {
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !cir.vector<1 x !s64i>,
!cir.ptr<!cir.vector<1 x !s64i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <1 x i64> noundef {{.*}}[[B:%.*]])
+// LLVM: store <1 x i64> [[B]], ptr [[A]], align 8
+// LLVM: ret void
+ return vst1_p64(ptr, val);
+}
+
+// LLVM-LABEL: @test_vst1_p8(
+// CIR-LABEL: @test_vst1_p8(
+void test_vst1_p8(poly8_t *a, poly8x8_t b) {
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !cir.vector<8 x !s8i>,
!cir.ptr<!cir.vector<8 x !s8i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x i8> noundef {{.*}}[[B:%.*]])
+// LLVM: store <8 x i8> [[B]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1_p8(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_f16(
+// CIR-LABEL: @test_vst1q_f16(
+void test_vst1q_f16(float16_t *a, float16x8_t b) {
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !cir.vector<8 x !cir.f16>,
!cir.ptr<!cir.vector<8 x !cir.f16>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x half> noundef {{.*}}[[B:%.*]])
+// LLVM: store <8 x half> [[B]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1q_f16(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_f32(
+// CIR-LABEL: @test_vst1q_f32(
+void test_vst1q_f32(float32_t *a, float32x4_t b) {
+// CIR: cir.store align(4) {{.*}}, {{.*}} : !cir.vector<4 x !cir.float>,
!cir.ptr<!cir.vector<4 x !cir.float>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <4 x float> noundef {{.*}}[[B:%.*]])
+// LLVM: store <4 x float> [[B]], ptr [[A]], align 4
+// LLVM: ret void
+ vst1q_f32(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_f64(
+// CIR-LABEL: @test_vst1q_f64(
+void test_vst1q_f64(float64_t *a, float64x2_t b) {
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !cir.vector<2 x !cir.double>,
!cir.ptr<!cir.vector<2 x !cir.double>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <2 x double> noundef
{{.*}}[[B:%.*]])
+// LLVM: store <2 x double> [[B]], ptr [[A]], align 8
+// LLVM: ret void
+ vst1q_f64(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_mf8(
+// CIR-LABEL: @test_vst1q_mf8(
+void test_vst1q_mf8(mfloat8_t *a, mfloat8x16_t val) {
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !cir.vector<16 x !u8i>,
!cir.ptr<!cir.vector<16 x !u8i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]])
+// LLVM: store <16 x i8> [[B]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1q_mf8(a, val);
+}
+
+// LLVM-LABEL: @test_vst1q_p16(
+// CIR-LABEL: @test_vst1q_p16(
+void test_vst1q_p16(poly16_t *a, poly16x8_t b) {
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !cir.vector<8 x !s16i>,
!cir.ptr<!cir.vector<8 x !s16i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x i16> noundef {{.*}}[[B:%.*]])
+// LLVM: store <8 x i16> [[B]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1q_p16(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_p64(
+// CIR-LABEL: @test_vst1q_p64(
+void test_vst1q_p64(poly64_t * ptr, poly64x2_t val) {
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !cir.vector<2 x !s64i>,
!cir.ptr<!cir.vector<2 x !s64i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <2 x i64> noundef {{.*}}[[B:%.*]])
+// LLVM: store <2 x i64> [[B]], ptr [[A]], align 8
+// LLVM: ret void
+ return vst1q_p64(ptr, val);
----------------
banach-space wrote:
```suggestion
vst1q_p64(ptr, val);
```
https://github.com/llvm/llvm-project/pull/209347
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