================
@@ -811,6 +811,48 @@ static mlir::Value emitX86MaskedLoad(CIRGenBuilderTy
&builder,
return builder.createMaskedLoad(loc, ty, ptr, alignment, maskVec, ops[1]);
}
+static mlir::Value emitX86VPerm2f128(CIRGenBuilderTy &builder,
+ mlir::Location loc,
+ llvm::SmallVector<mlir::Value> ops) {
+ auto inputType = cast<cir::VectorType>(ops[0].getType());
+ assert(!inputType.getIsScalable() &&
+ "This is only intended for fixed-width vectors");
+
+ const uint8_t imm = CIRGenFunction::getZExtIntValueFromConstOp(ops[2]) &
0xFF;
+ mlir::Value zeroVec = builder.getZero(loc, inputType);
+
+ // Mirror hardware and OGCG behaviour returning a zero vector
+ if ((imm & 0x80) && (imm & 0x08))
+ return zeroVec;
+
+ mlir::Value lanes[2];
+ llvm::SmallVector<int64_t, 64> mask;
----------------
lucaslive974 wrote:
Gotcha! On next's i'm going to verify cir call signatures to avoid unnecessary
processing.
https://github.com/llvm/llvm-project/pull/208851
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