================
@@ -302,17 +303,26 @@ deriveNeonSISDIntrinsicOperandTypes(CIRGenFunction &cgf,
unsigned modifier,
else if (vecArgTy && !(modifier & AddRetType))
funcResTy = wrapAsVector(resultTy);
- // When VectorizeArgTypes is set, wrap every operand that has the same
- // scalar type as arg0 into a vector. This covers intrinsics with multiple
- // data operands of the same type (e.g. vsri takes two data operands,
- // both of which must be wrapped into the same vector type).
+ // LLVMExtendedType<0> preserves the result vector's lane count while
----------------
E00N777 wrote:
Note WidenArgs isn't new hereļ¼#204989 added it, and deriveNeonBinaryArgType
uses it for vraddhn, where both operands are double-width. So
Arg0AsWidenedRetType fits the SISD case but not that one. Would you prefer
renaming both uses, splitting into two flags, or keeping WidenArgs as is?
https://github.com/llvm/llvm-project/pull/209389
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