https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/211199
The PR updated: https://github.com/riscv/riscv-isa-manual/pull/1564 >From a4d626b61cd0c2739924ab46427fa55b065bc641 Mon Sep 17 00:00:00 2001 From: Brandon Wu <[email protected]> Date: Wed, 22 Jul 2026 01:22:51 -0700 Subject: [PATCH] [llvm][RISCV] Bump svukte to 1.0 The PR updated: https://github.com/riscv/riscv-isa-manual/pull/1564 --- clang/test/Driver/print-supported-extensions-riscv.c | 2 +- clang/test/Preprocessor/riscv-target-features.c | 6 +++--- llvm/docs/RISCVUsage.rst | 2 +- llvm/docs/ReleaseNotes.md | 2 ++ llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +- llvm/test/CodeGen/RISCV/attributes.ll | 4 ++-- llvm/test/MC/RISCV/attribute-arch.s | 4 ++-- llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 2 +- 8 files changed, 13 insertions(+), 11 deletions(-) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index a9af276367817..9116b81632d17 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -270,7 +270,7 @@ // CHECK-NEXT: zvvmttls 0.1 'Zvvmttls' (Transposing Matrix Tile Load/Store) // CHECK-NEXT: zvzip 0.1 'Zvzip' (Vector Reordering Structured Data) // CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension) -// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) +// CHECK-NEXT: svukte 1.0 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) // CHECK-NEXT: xqccmt 0.1 'Xqccmt' (Qualcomm 16-bit Table Jump) // CHECK-NEXT: xsfmclic 0.1 'XSfmclic' (SiFive CLIC Machine-mode CSRs) // CHECK-NEXT: xsfsclic 0.1 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 28031814da16a..6019c959eaeb1 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1821,12 +1821,12 @@ // CHECK-SSCTR-EXT: __riscv_ssctr 1000000{{$}} // RUN: %clang --target=riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_svukte0p3 -E -dM %s \ +// RUN: -march=rv32i_svukte1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SVUKTE-EXT %s // RUN: %clang --target=riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_svukte0p3 -E -dM %s \ +// RUN: -march=rv64i_svukte1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SVUKTE-EXT %s -// CHECK-SVUKTE-EXT: __riscv_svukte 3000{{$}} +// CHECK-SVUKTE-EXT: __riscv_svukte 1000000{{$}} // Misaligned diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 72428398fc465..6ec89a5135b6e 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -353,7 +353,7 @@ The primary goal of experimental support is to assist in the process of ratifica LLVM implements the `0.7 release specification <https://github.com/user-attachments/files/16450464/riscv-crypto-spec-vector-extra_v0.0.7.pdf>`__. ``experimental-svukte`` - LLVM implements the `0.3 draft specification <https://github.com/riscv/riscv-isa-manual/pull/1564>`__. + LLVM implements the `1.0 draft specification <https://github.com/riscv/riscv-isa-manual/pull/1564>`__. ``experimental-zvdot4a8i`` LLVM implements the `0.1 draft specification <https://github.com/riscv/riscv-isa-manual/pull/2576>`__. diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 5f47ab6dd925f..af519a0848e90 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -94,6 +94,8 @@ Makes programs 10x faster by doing Special New Thing. ### Changes to the RISC-V Backend +* Bump svukte extension to 1.0. + ### Changes to the WebAssembly Backend ### Changes to the Windows Target diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 03d28b8448ba4..563b87af7e5fc 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1176,7 +1176,7 @@ def FeatureStdExtSha FeatureStdExtShvsatpa, FeatureStdExtShgatpa]>; def FeatureStdExtSvukte - : RISCVExperimentalExtension<0, 3, + : RISCVExperimentalExtension<1, 0, "Address-Independent Latency of User-Mode Faults to Supervisor Addresses">; // Pointer Masking extensions diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 26ffd8bb4ec89..0b39f41c671ca 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -408,7 +408,7 @@ ; RV32SVBARE: .attribute 5, "rv32i2p1_svbare1p0" ; RV32SVNAPOT: .attribute 5, "rv32i2p1_svnapot1p0" ; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0" -; RV32SVUKTE: .attribute 5, "rv32i2p1_svukte0p3" +; RV32SVUKTE: .attribute 5, "rv32i2p1_svukte1p0" ; RV32SVVPTC: .attribute 5, "rv32i2p1_svvptc1p0" ; RV32SVRSW60T59B: .attribute 5, "rv32i2p1_svrsw60t59b1p0" ; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0" @@ -570,7 +570,7 @@ ; RV64SVBARE: .attribute 5, "rv64i2p1_svbare1p0" ; RV64SVNAPOT: .attribute 5, "rv64i2p1_svnapot1p0" ; RV64SVPBMT: .attribute 5, "rv64i2p1_svpbmt1p0" -; RV64SVUKTE: .attribute 5, "rv64i2p1_svukte0p3" +; RV64SVUKTE: .attribute 5, "rv64i2p1_svukte1p0" ; RV64SVVPTC: .attribute 5, "rv64i2p1_svvptc1p0" ; RV64SVRSW60T59B: .attribute 5, "rv64i2p1_svrsw60t59b1p0" ; RV64SVINVAL: .attribute 5, "rv64i2p1_svinval1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 367ec6f04d953..a9020badd719d 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -414,8 +414,8 @@ .attribute arch, "rv64i_svrsw60t59b1p0" # CHECK: attribute 5, "rv64i2p1_svrsw60t59b1p0" -.attribute arch, "rv32i_svukte0p3" -# CHECK: attribute 5, "rv32i2p1_svukte0p3" +.attribute arch, "rv32i_svukte1p0" +# CHECK: attribute 5, "rv32i2p1_svukte1p0" .attribute arch, "rv32i_svvptc1p0" # CHECK: attribute 5, "rv32i2p1_svvptc1p0" diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index cdc2fcea37fcb..ab0f654d2c41d 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1639,7 +1639,7 @@ Experimental extensions zvvmttls 0.1 zvzip 0.1 smpmpmt 0.6 - svukte 0.3 + svukte 1.0 xqccmt 0.1 xsfmclic 0.1 xsfsclic 0.1 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
