llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v @llvm/pr-subscribers-clang-codegen Author: SiHuaN (sihuan) <details> <summary>Changes</summary> Add clang builtins and header wrappers for the packed sign- and zero-extend intrinsics `__riscv_psext_b`/`_h` and `__riscv_pzext_b`/`_h`, lowering to the `llvm.riscv.psext`/`pzext` intrinsics from #<!-- -->208685. The wrappers are unary, so the `__packed_psabs` header macro is renamed to `__packed_unary_builtin` and reused. --- Full diff: https://github.com/llvm/llvm-project/pull/211487.diff 5 Files Affected: - (modified) clang/include/clang/Basic/BuiltinsRISCV.td (+11) - (modified) clang/lib/CodeGen/TargetBuiltins/RISCV.cpp (+23-1) - (modified) clang/lib/Headers/riscv_packed_simd.h (+17-6) - (modified) clang/test/CodeGen/RISCV/rvp-intrinsics.c (+144) - (modified) cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c (+33) ``````````diff diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td index 3814958d81f8b..4728b97937d4f 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.td +++ b/clang/include/clang/Basic/BuiltinsRISCV.td @@ -265,6 +265,17 @@ def psabs_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>)">; def psabs_i8x8 : RISCVBuiltin<"_Vector<8, signed char>(_Vector<8, signed char>)">; def psabs_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>)">; +// Packed Sign and Zero Extend (32-bit) +def psext_b_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>)">; +def pzext_b_u16x2 : RISCVBuiltin<"_Vector<2, unsigned short>(_Vector<2, unsigned short>)">; + +// Packed Sign and Zero Extend (64-bit) +def psext_b_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>)">; +def psext_b_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>)">; +def psext_h_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>)">; +def pzext_b_u16x4 : RISCVBuiltin<"_Vector<4, unsigned short>(_Vector<4, unsigned short>)">; +def pzext_h_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(_Vector<2, unsigned int>)">; + } // Features = "experimental-p" //===----------------------------------------------------------------------===// diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp index a3b1db1732af9..7f8a0727b602e 100644 --- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp @@ -1263,7 +1263,14 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, case RISCV::BI__builtin_riscv_psabs_i8x4: case RISCV::BI__builtin_riscv_psabs_i16x2: case RISCV::BI__builtin_riscv_psabs_i8x8: - case RISCV::BI__builtin_riscv_psabs_i16x4: { + case RISCV::BI__builtin_riscv_psabs_i16x4: + case RISCV::BI__builtin_riscv_psext_b_i16x2: + case RISCV::BI__builtin_riscv_pzext_b_u16x2: + case RISCV::BI__builtin_riscv_psext_b_i16x4: + case RISCV::BI__builtin_riscv_psext_b_i32x2: + case RISCV::BI__builtin_riscv_psext_h_i32x2: + case RISCV::BI__builtin_riscv_pzext_b_u16x4: + case RISCV::BI__builtin_riscv_pzext_h_u32x2: { switch (BuiltinID) { default: llvm_unreachable("unexpected builtin ID"); @@ -1355,6 +1362,21 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, case RISCV::BI__builtin_riscv_psabs_i16x4: ID = Intrinsic::riscv_psabs; break; + case RISCV::BI__builtin_riscv_psext_b_i16x2: + case RISCV::BI__builtin_riscv_psext_b_i16x4: + case RISCV::BI__builtin_riscv_psext_b_i32x2: + ID = Intrinsic::riscv_psext_b; + break; + case RISCV::BI__builtin_riscv_psext_h_i32x2: + ID = Intrinsic::riscv_psext_h; + break; + case RISCV::BI__builtin_riscv_pzext_b_u16x2: + case RISCV::BI__builtin_riscv_pzext_b_u16x4: + ID = Intrinsic::riscv_pzext_b; + break; + case RISCV::BI__builtin_riscv_pzext_h_u32x2: + ID = Intrinsic::riscv_pzext_h; + break; } IntrinsicTypes = {ResultType}; diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h index 7d40f046eba80..93cff3552ddf7 100644 --- a/clang/lib/Headers/riscv_packed_simd.h +++ b/clang/lib/Headers/riscv_packed_simd.h @@ -115,7 +115,7 @@ typedef uint32_t uint32x2_t __attribute__((__vector_size__(8))); return (ty)builtin(__rs1, __rs2, __rd); \ } -#define __packed_psabs(name, ty, builtin) \ +#define __packed_unary_builtin(name, ty, builtin) \ static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \ return builtin(__rs1); \ } @@ -683,12 +683,23 @@ __packed_abdsum_acc(pabdsumau_u8x8_u32, uint32_t, uint8x8_t, __builtin_riscv_pab __packed_abdsum_acc(pabdsumau_u8x8_u64, uint64_t, uint8x8_t, __builtin_riscv_pabdsumau_u8x8_u64) /* Packed Saturating Absolute Value (32-bit) */ -__packed_psabs(psabs_i8x4, int8x4_t, __builtin_riscv_psabs_i8x4) -__packed_psabs(psabs_i16x2, int16x2_t, __builtin_riscv_psabs_i16x2) +__packed_unary_builtin(psabs_i8x4, int8x4_t, __builtin_riscv_psabs_i8x4) +__packed_unary_builtin(psabs_i16x2, int16x2_t, __builtin_riscv_psabs_i16x2) /* Packed Saturating Absolute Value (64-bit) */ -__packed_psabs(psabs_i8x8, int8x8_t, __builtin_riscv_psabs_i8x8) -__packed_psabs(psabs_i16x4, int16x4_t, __builtin_riscv_psabs_i16x4) +__packed_unary_builtin(psabs_i8x8, int8x8_t, __builtin_riscv_psabs_i8x8) +__packed_unary_builtin(psabs_i16x4, int16x4_t, __builtin_riscv_psabs_i16x4) + +/* Packed Sign and Zero Extend (32-bit) */ +__packed_unary_builtin(psext_b_i16x2, int16x2_t, __builtin_riscv_psext_b_i16x2) +__packed_unary_builtin(pzext_b_u16x2, uint16x2_t, __builtin_riscv_pzext_b_u16x2) + +/* Packed Sign and Zero Extend (64-bit) */ +__packed_unary_builtin(psext_b_i16x4, int16x4_t, __builtin_riscv_psext_b_i16x4) +__packed_unary_builtin(psext_b_i32x2, int32x2_t, __builtin_riscv_psext_b_i32x2) +__packed_unary_builtin(psext_h_i32x2, int32x2_t, __builtin_riscv_psext_h_i32x2) +__packed_unary_builtin(pzext_b_u16x4, uint16x4_t, __builtin_riscv_pzext_b_u16x4) +__packed_unary_builtin(pzext_h_u32x2, uint32x2_t, __builtin_riscv_pzext_h_u32x2) /* Reinterpret Casts, Packed <-> Scalar (32-bit) */ __packed_reinterpret(u8x4_u32, uint32_t, uint8x4_t) @@ -801,7 +812,7 @@ __packed_reinterpret(u32x2_i32x2, int32x2_t, uint32x2_t) #undef __packed_binary_builtin_cast #undef __packed_reduction #undef __packed_merge_builtin -#undef __packed_psabs +#undef __packed_unary_builtin #undef __packed_widen_convert #undef __packed_widen_high2 #undef __packed_widen_high4 diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c index 816409268ce02..37f13ad293eaf 100644 --- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c +++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c @@ -7032,6 +7032,150 @@ int16x4_t test_psabs_i16x4(int16x4_t rs1) { return __riscv_psabs_i16x4(rs1); } +/* Packed Sign and Zero Extend (32-bit) */ + +// RV32-LABEL: define dso_local i32 @test_psext_b_i16x2( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.psext.b.v2i16(<2 x i16> [[TMP0]]) +// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32 +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local i32 @test_psext_b_i16x2( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.psext.b.v2i16(<2 x i16> [[TMP0]]) +// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32 +// RV64-NEXT: ret i32 [[TMP2]] +// +int16x2_t test_psext_b_i16x2(int16x2_t rs1) { + return __riscv_psext_b_i16x2(rs1); +} + +// RV32-LABEL: define dso_local i32 @test_pzext_b_u16x2( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pzext.b.v2i16(<2 x i16> [[TMP0]]) +// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32 +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local i32 @test_pzext_b_u16x2( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.pzext.b.v2i16(<2 x i16> [[TMP0]]) +// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32 +// RV64-NEXT: ret i32 [[TMP2]] +// +uint16x2_t test_pzext_b_u16x2(uint16x2_t rs1) { + return __riscv_pzext_b_u16x2(rs1); +} + +/* Packed Sign and Zero Extend (64-bit) */ + +// RV32-LABEL: define dso_local i64 @test_psext_b_i16x4( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.psext.b.v4i16(<4 x i16> [[TMP0]]) +// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_psext_b_i16x4( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.psext.b.v4i16(<4 x i16> [[TMP0]]) +// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +int16x4_t test_psext_b_i16x4(int16x4_t rs1) { + return __riscv_psext_b_i16x4(rs1); +} + +// RV32-LABEL: define dso_local i64 @test_psext_b_i32x2( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV32-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.psext.b.v2i32(<2 x i32> [[TMP0]]) +// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_psext_b_i32x2( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV64-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.psext.b.v2i32(<2 x i32> [[TMP0]]) +// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +int32x2_t test_psext_b_i32x2(int32x2_t rs1) { + return __riscv_psext_b_i32x2(rs1); +} + +// RV32-LABEL: define dso_local i64 @test_psext_h_i32x2( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV32-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.psext.h.v2i32(<2 x i32> [[TMP0]]) +// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_psext_h_i32x2( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV64-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.psext.h.v2i32(<2 x i32> [[TMP0]]) +// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +int32x2_t test_psext_h_i32x2(int32x2_t rs1) { + return __riscv_psext_h_i32x2(rs1); +} + +// RV32-LABEL: define dso_local i64 @test_pzext_b_u16x4( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.pzext.b.v4i16(<4 x i16> [[TMP0]]) +// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_pzext_b_u16x4( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.pzext.b.v4i16(<4 x i16> [[TMP0]]) +// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +uint16x4_t test_pzext_b_u16x4(uint16x4_t rs1) { + return __riscv_pzext_b_u16x4(rs1); +} + +// RV32-LABEL: define dso_local i64 @test_pzext_h_u32x2( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV32-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.pzext.h.v2i32(<2 x i32> [[TMP0]]) +// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_pzext_h_u32x2( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV64-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.riscv.pzext.h.v2i32(<2 x i32> [[TMP0]]) +// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +uint32x2_t test_pzext_h_u32x2(uint32x2_t rs1) { + return __riscv_pzext_h_u32x2(rs1); +} + /* Packed Widening Convert */ // RV32-LABEL: define dso_local i64 @test_pwcvt_i16x4( diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c index 2af196cdaadc0..9c04f1400f4c0 100644 --- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c +++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c @@ -2495,6 +2495,39 @@ int8x8_t test_psabs_i8x8(int8x8_t a) { return __riscv_psabs_i8x8(a); } // RV64: psabs.h int16x4_t test_psabs_i16x4(int16x4_t a) { return __riscv_psabs_i16x4(a); } +// CHECK-LABEL: test_psext_b_i16x2: +// CHECK: psext.h.b +int16x2_t test_psext_b_i16x2(int16x2_t a) { return __riscv_psext_b_i16x2(a); } + +// CHECK-LABEL: test_pzext_b_u16x2: +// CHECK: pzext.h.b +uint16x2_t test_pzext_b_u16x2(uint16x2_t a) { return __riscv_pzext_b_u16x2(a); } + +// CHECK-LABEL: test_psext_b_i16x4: +// RV32: psext.dh.b +// RV64: psext.h.b +int16x4_t test_psext_b_i16x4(int16x4_t a) { return __riscv_psext_b_i16x4(a); } + +// CHECK-LABEL: test_psext_b_i32x2: +// RV32: psext.dw.b +// RV64: psext.w.b +int32x2_t test_psext_b_i32x2(int32x2_t a) { return __riscv_psext_b_i32x2(a); } + +// CHECK-LABEL: test_psext_h_i32x2: +// RV32: psext.dw.h +// RV64: psext.w.h +int32x2_t test_psext_h_i32x2(int32x2_t a) { return __riscv_psext_h_i32x2(a); } + +// CHECK-LABEL: test_pzext_b_u16x4: +// RV32: pzext.dh.b +// RV64: pzext.h.b +uint16x4_t test_pzext_b_u16x4(uint16x4_t a) { return __riscv_pzext_b_u16x4(a); } + +// CHECK-LABEL: test_pzext_h_u32x2: +// RV32: pzext.dw.h +// RV64: pzext.w.h +uint32x2_t test_pzext_h_u32x2(uint32x2_t a) { return __riscv_pzext_h_u32x2(a); } + // CHECK-LABEL: test_pnzip_i8x4: // CHECK: ppaire.b int8x4_t test_pnzip_i8x4(int16x2_t rs1, int16x2_t rs2) { `````````` </details> https://github.com/llvm/llvm-project/pull/211487 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
