https://github.com/jacquesguan created https://github.com/llvm/llvm-project/pull/211555
Leave them NYI now. >From cd641eb486043931ec5749648a4aacc1f35cdd60 Mon Sep 17 00:00:00 2001 From: Jianjian GUAN <[email protected]> Date: Thu, 23 Jul 2026 16:51:18 +0800 Subject: [PATCH] [CIR][RISCV] Add new builtins, NFC Leave them NYI now. --- clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp | 45 +++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp index 25e714a612147..ea04fddc1b710 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp @@ -100,7 +100,25 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) { intrinsicName = "riscv.unzip"; break; } - // Zknh + // Zknd + case RISCV::BI__builtin_riscv_aes32dsi: + case RISCV::BI__builtin_riscv_aes32dsmi: + case RISCV::BI__builtin_riscv_aes64ds: + case RISCV::BI__builtin_riscv_aes64dsm: + case RISCV::BI__builtin_riscv_aes64im: + // Zknd & Zkne + case RISCV::BI__builtin_riscv_aes64ks1i: + case RISCV::BI__builtin_riscv_aes64ks2: + // Zkne + case RISCV::BI__builtin_riscv_aes32esi: + case RISCV::BI__builtin_riscv_aes32esmi: + case RISCV::BI__builtin_riscv_aes64es: + case RISCV::BI__builtin_riscv_aes64esm: { + cgm.errorNYI(e->getSourceRange(), + std::string("unimplemented RISC-V builtin call: ") + + getContext().BuiltinInfo.getName(builtinID)); + return mlir::Value{}; + } case RISCV::BI__builtin_riscv_sha256sig0: { intrinsicName = "riscv.sha256sig0"; break; @@ -117,6 +135,21 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) { intrinsicName = "riscv.sha256sum1"; break; } + case RISCV::BI__builtin_riscv_sha512sig0h: + case RISCV::BI__builtin_riscv_sha512sig0l: + case RISCV::BI__builtin_riscv_sha512sig1h: + case RISCV::BI__builtin_riscv_sha512sig1l: + case RISCV::BI__builtin_riscv_sha512sum0r: + case RISCV::BI__builtin_riscv_sha512sum1r: + case RISCV::BI__builtin_riscv_sha512sig0: + case RISCV::BI__builtin_riscv_sha512sig1: + case RISCV::BI__builtin_riscv_sha512sum0: + case RISCV::BI__builtin_riscv_sha512sum1: { + cgm.errorNYI(e->getSourceRange(), + std::string("unimplemented RISC-V builtin call: ") + + getContext().BuiltinInfo.getName(builtinID)); + return mlir::Value{}; + } // Zksed case RISCV::BI__builtin_riscv_sm4ks: { intrinsicName = "riscv.sm4ks"; @@ -282,6 +315,16 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) { return mlir::Value{}; } + // XMIPS execution control + case RISCV::BI__builtin_riscv_mips_pause: + case RISCV::BI__builtin_riscv_mips_ehb: + case RISCV::BI__builtin_riscv_mips_ihb: { + cgm.errorNYI(e->getSourceRange(), + std::string("unimplemented RISC-V builtin call: ") + + getContext().BuiltinInfo.getName(builtinID)); + return mlir::Value{}; + } + // TODO: Handle vector builtins in tablegen. } _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
