https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/212353
>From 421c503ce7c57748d6cb969987b247aff7d4e426 Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Sun, 26 Jul 2026 11:11:17 +0200 Subject: [PATCH] AMDGPU: Generate TargetParser table from TableGen Migrate .def file to tablegen. The initial TargetParser AMDGPU backend only handled R600. Extend to modern targets. Stub out some tablegen definitions which will be used in future changes. Co-authored-by: Claude (Claude-Opus-4.8) --- clang/lib/Basic/Targets/AMDGPU.cpp | 4 +- clang/lib/Sema/CMakeLists.txt | 3 + .../llvm/TargetParser/AMDGPUTargetParser.def | 155 ----- .../llvm/TargetParser/AMDGPUTargetParser.h | 9 +- llvm/include/llvm/TargetParser/CMakeLists.txt | 3 + llvm/include/module.modulemap | 6 +- llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td | 30 +- llvm/lib/Target/AMDGPU/GCNProcessors.td | 528 ++++++++++-------- llvm/lib/TargetParser/AMDGPUTargetParser.cpp | 44 +- llvm/test/TableGen/AMDGPUTargetDefErrors.td | 16 + .../TableGen/Basic/AMDGPUTargetDefEmitter.cpp | 124 +++- 11 files changed, 497 insertions(+), 425 deletions(-) delete mode 100644 llvm/include/llvm/TargetParser/AMDGPUTargetParser.def diff --git a/clang/lib/Basic/Targets/AMDGPU.cpp b/clang/lib/Basic/Targets/AMDGPU.cpp index 487c1949e7c83..370ef52a9bdb0 100644 --- a/clang/lib/Basic/Targets/AMDGPU.cpp +++ b/clang/lib/Basic/Targets/AMDGPU.cpp @@ -293,8 +293,8 @@ void AMDGPUTargetInfo::getTargetDefines(const LangOptions &Opts, // Sanitize the name of generic targets. // e.g. gfx10-1-generic -> gfx10_1_generic - if (GPUKind >= llvm::AMDGPU::GK_AMDGCN_GENERIC_FIRST && - GPUKind <= llvm::AMDGPU::GK_AMDGCN_GENERIC_LAST) { + if (GPUKind >= llvm::AMDGPU::GK_AMDGPU_GENERIC_FIRST && + GPUKind <= llvm::AMDGPU::GK_AMDGPU_GENERIC_LAST) { llvm::replace(CanonName, '-', '_'); } diff --git a/clang/lib/Sema/CMakeLists.txt b/clang/lib/Sema/CMakeLists.txt index ef729e22c1dc8..88f0c993888d9 100644 --- a/clang/lib/Sema/CMakeLists.txt +++ b/clang/lib/Sema/CMakeLists.txt @@ -107,6 +107,9 @@ add_clang_library(clangSema acc_gen omp_gen ClangDriverOptions + # SemaAMDGPU.cpp includes AMDGPUTargetParser.h, which includes generated + # TargetParser headers. + target_parser_gen LINK_LIBS clangAPINotes diff --git a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.def b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.def deleted file mode 100644 index c09bd25e55deb..0000000000000 --- a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.def +++ /dev/null @@ -1,155 +0,0 @@ -//===- AMDGPUTargetParser.def - AMDGPU target parsing defines ---*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file provides defines to build up the AMDGPU target parser's logic. -// -//===----------------------------------------------------------------------===// - -#ifndef R600_GPU -#define R600_GPU(NAME, ENUM, FEATURES) -#endif - -#ifndef R600_GPU_ALIAS -#define R600_GPU_ALIAS(NAME, ENUM) -#endif - -R600_GPU ("r600", GK_R600, FEATURE_NONE) -R600_GPU_ALIAS("rv630", GK_R600) -R600_GPU_ALIAS("rv635", GK_R600) -R600_GPU ("r630", GK_R630, FEATURE_NONE) -R600_GPU_ALIAS("rs780", GK_RS880) -R600_GPU ("rs880", GK_RS880, FEATURE_NONE) -R600_GPU_ALIAS("rv610", GK_RS880) -R600_GPU_ALIAS("rv620", GK_RS880) -R600_GPU ("rv670", GK_RV670, FEATURE_NONE) -R600_GPU ("rv710", GK_RV710, FEATURE_NONE) -R600_GPU ("rv730", GK_RV730, FEATURE_NONE) -R600_GPU_ALIAS("rv740", GK_RV770) -R600_GPU ("rv770", GK_RV770, FEATURE_NONE) -R600_GPU ("cedar", GK_CEDAR, FEATURE_NONE) -R600_GPU_ALIAS("palm", GK_CEDAR) -R600_GPU ("cypress", GK_CYPRESS, FEATURE_FMA) -R600_GPU_ALIAS("hemlock", GK_CYPRESS) -R600_GPU ("juniper", GK_JUNIPER, FEATURE_NONE) -R600_GPU ("redwood", GK_REDWOOD, FEATURE_NONE) -R600_GPU ("sumo", GK_SUMO, FEATURE_NONE) -R600_GPU_ALIAS("sumo2", GK_SUMO) -R600_GPU ("barts", GK_BARTS, FEATURE_NONE) -R600_GPU ("caicos", GK_CAICOS, FEATURE_NONE) -R600_GPU_ALIAS("aruba", GK_CAYMAN) -R600_GPU ("cayman", GK_CAYMAN, FEATURE_FMA) -R600_GPU ("turks", GK_TURKS, FEATURE_NONE) - -#undef R600_GPU -#undef R600_GPU_ALIAS - -#ifndef AMDGCN_GPU -#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) -#endif - -#ifndef AMDGCN_GPU_ALIAS -#define AMDGCN_GPU_ALIAS(NAME, ENUM) -#endif - -// Don't bother listing the implicitly true features -AMDGCN_GPU ("gfx600", GK_GFX600, Triple::AMDGPUSubArch600, ( 6, 0, 0), FEATURE_FAST_FMA_F32) -AMDGCN_GPU_ALIAS("tahiti", GK_GFX600) -AMDGCN_GPU ("gfx601", GK_GFX601, Triple::AMDGPUSubArch601, ( 6, 0, 1), FEATURE_NONE) -AMDGCN_GPU_ALIAS("pitcairn", GK_GFX601) -AMDGCN_GPU_ALIAS("verde", GK_GFX601) -AMDGCN_GPU ("gfx602", GK_GFX602, Triple::AMDGPUSubArch602, ( 6, 0, 2), FEATURE_NONE) -AMDGCN_GPU_ALIAS("hainan", GK_GFX602) -AMDGCN_GPU_ALIAS("oland", GK_GFX602) -AMDGCN_GPU ("gfx700", GK_GFX700, Triple::AMDGPUSubArch700, ( 7, 0, 0), FEATURE_NONE) -AMDGCN_GPU_ALIAS("kaveri", GK_GFX700) -AMDGCN_GPU ("gfx701", GK_GFX701, Triple::AMDGPUSubArch701, ( 7, 0, 1), FEATURE_FAST_FMA_F32) -AMDGCN_GPU_ALIAS("hawaii", GK_GFX701) -AMDGCN_GPU ("gfx702", GK_GFX702, Triple::AMDGPUSubArch702, ( 7, 0, 2), FEATURE_FAST_FMA_F32) -AMDGCN_GPU ("gfx703", GK_GFX703, Triple::AMDGPUSubArch703, ( 7, 0, 3), FEATURE_NONE) -AMDGCN_GPU_ALIAS("kabini", GK_GFX703) -AMDGCN_GPU_ALIAS("mullins", GK_GFX703) -AMDGCN_GPU ("gfx704", GK_GFX704, Triple::AMDGPUSubArch704, ( 7, 0, 4), FEATURE_NONE) -AMDGCN_GPU_ALIAS("bonaire", GK_GFX704) -AMDGCN_GPU ("gfx705", GK_GFX705, Triple::AMDGPUSubArch705, ( 7, 0, 5), FEATURE_NONE) -AMDGCN_GPU ("gfx801", GK_GFX801, Triple::AMDGPUSubArch801, ( 8, 0, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES) -AMDGCN_GPU_ALIAS("carrizo", GK_GFX801) -AMDGCN_GPU ("gfx802", GK_GFX802, Triple::AMDGPUSubArch802, ( 8, 0, 2), FEATURE_FAST_DENORMAL_F32|FEATURE_SGPR_INIT_BUG) -AMDGCN_GPU_ALIAS("iceland", GK_GFX802) -AMDGCN_GPU_ALIAS("tonga", GK_GFX802) -AMDGCN_GPU ("gfx803", GK_GFX803, Triple::AMDGPUSubArch803, ( 8, 0, 3), FEATURE_FAST_DENORMAL_F32) -AMDGCN_GPU_ALIAS("fiji", GK_GFX803) -AMDGCN_GPU_ALIAS("polaris10", GK_GFX803) -AMDGCN_GPU_ALIAS("polaris11", GK_GFX803) -AMDGCN_GPU ("gfx805", GK_GFX805, Triple::AMDGPUSubArch805, ( 8, 0, 5), FEATURE_FAST_DENORMAL_F32|FEATURE_SGPR_INIT_BUG) -AMDGCN_GPU_ALIAS("tongapro", GK_GFX805) -AMDGCN_GPU ("gfx810", GK_GFX810, Triple::AMDGPUSubArch810, ( 8, 1, 0), FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES) -AMDGCN_GPU_ALIAS("stoney", GK_GFX810) -AMDGCN_GPU ("gfx900", GK_GFX900, Triple::AMDGPUSubArch900, ( 9, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES) -AMDGCN_GPU ("gfx902", GK_GFX902, Triple::AMDGPUSubArch902, ( 9, 0, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES) -AMDGCN_GPU ("gfx904", GK_GFX904, Triple::AMDGPUSubArch904, ( 9, 0, 4), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES) -AMDGCN_GPU ("gfx906", GK_GFX906, Triple::AMDGPUSubArch906, ( 9, 0, 6), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC) -AMDGCN_GPU ("gfx908", GK_GFX908, Triple::AMDGPUSubArch908, ( 9, 0, 8), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC) -AMDGCN_GPU ("gfx909", GK_GFX909, Triple::AMDGPUSubArch909, ( 9, 0, 9), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES) -AMDGCN_GPU ("gfx90a", GK_GFX90A, Triple::AMDGPUSubArch90A, ( 9, 0, 10), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC) -AMDGCN_GPU ("gfx90c", GK_GFX90C, Triple::AMDGPUSubArch90C, ( 9, 0, 12), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES) -AMDGCN_GPU ("gfx942", GK_GFX942, Triple::AMDGPUSubArch942, ( 9, 4, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC) -AMDGCN_GPU ("gfx950", GK_GFX950, Triple::AMDGPUSubArch950, ( 9, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC) -AMDGCN_GPU ("gfx1010", GK_GFX1010, Triple::AMDGPUSubArch1010, (10, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP) -AMDGCN_GPU ("gfx1011", GK_GFX1011, Triple::AMDGPUSubArch1011, (10, 1, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP) -AMDGCN_GPU ("gfx1012", GK_GFX1012, Triple::AMDGPUSubArch1012, (10, 1, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP) -AMDGCN_GPU ("gfx1013", GK_GFX1013, Triple::AMDGPUSubArch1013, (10, 1, 3), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP) -AMDGCN_GPU ("gfx1030", GK_GFX1030, Triple::AMDGPUSubArch1030, (10, 3, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1031", GK_GFX1031, Triple::AMDGPUSubArch1031, (10, 3, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1032", GK_GFX1032, Triple::AMDGPUSubArch1032, (10, 3, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1033", GK_GFX1033, Triple::AMDGPUSubArch1033, (10, 3, 3), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1034", GK_GFX1034, Triple::AMDGPUSubArch1034, (10, 3, 4), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1035", GK_GFX1035, Triple::AMDGPUSubArch1035, (10, 3, 5), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1036", GK_GFX1036, Triple::AMDGPUSubArch1036, (10, 3, 6), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1100", GK_GFX1100, Triple::AMDGPUSubArch1100, (11, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1101", GK_GFX1101, Triple::AMDGPUSubArch1101, (11, 0, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1102", GK_GFX1102, Triple::AMDGPUSubArch1102, (11, 0, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1103", GK_GFX1103, Triple::AMDGPUSubArch1103, (11, 0, 3), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1150", GK_GFX1150, Triple::AMDGPUSubArch1150, (11, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1151", GK_GFX1151, Triple::AMDGPUSubArch1151, (11, 5, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1152", GK_GFX1152, Triple::AMDGPUSubArch1152, (11, 5, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1153", GK_GFX1153, Triple::AMDGPUSubArch1153, (11, 5, 3), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1154", GK_GFX1154, Triple::AMDGPUSubArch1154, (11, 5, 4), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1170", GK_GFX1170, Triple::AMDGPUSubArch1170, (11, 7, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1171", GK_GFX1171, Triple::AMDGPUSubArch1171, (11, 7, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1172", GK_GFX1172, Triple::AMDGPUSubArch1172, (11, 7, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1200", GK_GFX1200, Triple::AMDGPUSubArch1200, (12, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1201", GK_GFX1201, Triple::AMDGPUSubArch1201, (12, 0, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx1250", GK_GFX1250, Triple::AMDGPUSubArch1250, (12, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_SRAMECC) -AMDGCN_GPU ("gfx1251", GK_GFX1251, Triple::AMDGPUSubArch1251, (12, 5, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_SRAMECC) -AMDGCN_GPU ("gfx1310", GK_GFX1310, Triple::AMDGPUSubArch1310, (13, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) - -// Generic targets return the lowest common denominator -// within their family. That is, the ISA that is the most -// restricted in terms of features. -// -// gfx9-generic is tricky because there is no lowest -// common denominator, so we return gfx900 which has mad-mix -// but this family doesn't have it. -// -// This API should never be used to check for a particular -// feature anyway. -// -// TODO: Split up this API depending on its caller so -// generic target handling is more obvious and less risky. -AMDGCN_GPU ("gfx9-generic", GK_GFX9_GENERIC, Triple::AMDGPUSubArch9, ( 9, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES) -AMDGCN_GPU ("gfx9-4-generic", GK_GFX9_4_GENERIC, Triple::AMDGPUSubArch9_4, ( 9, 4, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC) -AMDGCN_GPU ("gfx10-1-generic", GK_GFX10_1_GENERIC, Triple::AMDGPUSubArch10_1, (10, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP) -AMDGCN_GPU ("gfx10-3-generic", GK_GFX10_3_GENERIC, Triple::AMDGPUSubArch10_3, (10, 3, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx11-generic", GK_GFX11_GENERIC, Triple::AMDGPUSubArch11, (11, 0, 3), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx11-7-generic", GK_GFX11_7_GENERIC, Triple::AMDGPUSubArch11_7, (11, 7, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx12-generic", GK_GFX12_GENERIC, Triple::AMDGPUSubArch12, (12, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) -AMDGCN_GPU ("gfx12-5-generic", GK_GFX12_5_GENERIC, Triple::AMDGPUSubArch12_5, (12, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK) -AMDGCN_GPU ("gfx13-generic", GK_GFX13_GENERIC, Triple::AMDGPUSubArch13, (13, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP) - -#undef AMDGCN_GPU -#undef AMDGCN_GPU_ALIAS diff --git a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h index 5b35ff6b88708..fe2e89fa0daf0 100644 --- a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h +++ b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h @@ -36,11 +36,12 @@ enum GPUKind : uint32_t { GK_NONE = 0, #define R600_GPU(NAME, ENUM, FEATURES) ENUM, -#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) ENUM, -#include "AMDGPUTargetParser.def" +#include "llvm/TargetParser/R600TargetParserDef.inc" +#define AMDGPU_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) ENUM, +#include "llvm/TargetParser/AMDGPUTargetParserDef.inc" - GK_AMDGCN_GENERIC_FIRST = GK_GFX9_GENERIC, - GK_AMDGCN_GENERIC_LAST = GK_GFX13_GENERIC, + GK_AMDGPU_GENERIC_FIRST = GK_GFX9_GENERIC, + GK_AMDGPU_GENERIC_LAST = GK_GFX13_GENERIC, }; /// Instruction set architecture version. diff --git a/llvm/include/llvm/TargetParser/CMakeLists.txt b/llvm/include/llvm/TargetParser/CMakeLists.txt index 62e9da1447f68..af26db48f2132 100644 --- a/llvm/include/llvm/TargetParser/CMakeLists.txt +++ b/llvm/include/llvm/TargetParser/CMakeLists.txt @@ -13,5 +13,8 @@ tablegen(LLVM PPCGenTargetFeatures.inc -gen-target-features EXTRA_INCLUDES ${PRO set(LLVM_TARGET_DEFINITIONS ${PROJECT_SOURCE_DIR}/lib/Target/AMDGPU/R600.td) tablegen(LLVM R600TargetParserDef.inc -gen-amdgpu-target-def EXTRA_INCLUDES ${PROJECT_SOURCE_DIR}/lib/Target/AMDGPU) +set(LLVM_TARGET_DEFINITIONS ${PROJECT_SOURCE_DIR}/lib/Target/AMDGPU/AMDGPU.td) +tablegen(LLVM AMDGPUTargetParserDef.inc -gen-amdgpu-target-def EXTRA_INCLUDES ${PROJECT_SOURCE_DIR}/lib/Target/AMDGPU) + # This covers all of the tablegen calls above. add_public_tablegen_target(target_parser_gen) diff --git a/llvm/include/module.modulemap b/llvm/include/module.modulemap index 53e34285eddb0..4d71818df8d2a 100644 --- a/llvm/include/module.modulemap +++ b/llvm/include/module.modulemap @@ -377,6 +377,11 @@ module TargetParserGen { extern module LLVM_Extern_TargetParser_Gen "module.extern.modulemap" export * } + module AMDGPUTargetParserDef { + header "llvm/TargetParser/AMDGPUTargetParser.h" + extern module LLVM_Extern_TargetParser_Gen "module.extern.modulemap" + export * + } } // A module covering ADT/ and Support/. These are intertwined and @@ -421,7 +426,6 @@ module LLVM_Utils { module * { export * } // These are intended for textual inclusion. - textual header "llvm/TargetParser/AMDGPUTargetParser.def" textual header "llvm/TargetParser/ARMTargetParser.def" textual header "llvm/TargetParser/CSKYTargetParser.def" textual header "llvm/TargetParser/X86TargetParser.def" diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td b/llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td index ffa3869e7151e..396804468877e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td @@ -20,12 +20,38 @@ class AMDGPUArchFeature<string spelling> { // R600-only. def FEATURE_FMA : AMDGPUArchFeature<"FEATURE_FMA">; -// Marks a Processor/ProcessorModel record as a canonical TargetParser GPU. -class AMDGPUGPUInfo { +// AMDGCN. +def FEATURE_FAST_FMA_F32 : AMDGPUArchFeature<"FEATURE_FAST_FMA_F32">; +def FEATURE_FAST_DENORMAL_F32 : AMDGPUArchFeature<"FEATURE_FAST_DENORMAL_F32">; +def FEATURE_WAVE32 : AMDGPUArchFeature<"FEATURE_WAVE32">; +def FEATURE_XNACK : AMDGPUArchFeature<"FEATURE_XNACK">; +def FEATURE_SRAMECC : AMDGPUArchFeature<"FEATURE_SRAMECC">; +def FEATURE_WGP : AMDGPUArchFeature<"FEATURE_WGP">; +def FEATURE_XNACK_ON_OFF_MODES : AMDGPUArchFeature<"FEATURE_XNACK_ON_OFF_MODES">; +def FEATURE_SGPR_INIT_BUG : AMDGPUArchFeature<"FEATURE_SGPR_INIT_BUG">; + +// Marks a Processor/ProcessorModel record as a canonical GPU. +// +// \p isa is the ISA version [major, minor, stepping]. Empty for R600 (no AMDGCN +// ISA version); required for AMDGCN GPUs. Not derivable from the name. +class AMDGPUGPUInfo<list<int> isa = []> { list<AMDGPUArchFeature> ArchFeatures = []; + + list<int> IsaVersion = isa; + + // List of targets which are compatible with this target. This + // should be used for a "gfxN-generic" targets only, and empty for + // individual GPUs. + list<Processor> CoveredGPUs = []; } // An R600 processor that is also a canonical TargetParser GPU. class R600ProcessorModel<string n, ProcessorItineraries pi, list<SubtargetFeature> f> : Processor<n, pi, f>, AMDGPUGPUInfo; + +// A gfx6+ processor that is also a canonical TargetParser GPU. \p isa +// is the ISA version [major, minor, stepping]. +class AMDGPUProcessorModel<string n, SchedMachineModel m, + list<SubtargetFeature> f, list<int> isa> + : ProcessorModel<n, m, f>, AMDGPUGPUInfo<isa>; diff --git a/llvm/lib/Target/AMDGPU/GCNProcessors.td b/llvm/lib/Target/AMDGPU/GCNProcessors.td index 3003d23c29b40..b5e648d277fe5 100644 --- a/llvm/lib/Target/AMDGPU/GCNProcessors.td +++ b/llvm/lib/Target/AMDGPU/GCNProcessors.td @@ -6,11 +6,20 @@ // //===----------------------------------------------------------------------===// +// Shared ArchFeature lists. Grouped by wavefront mode and the XNACK/SRAMECC/WGP +// features that recur across many GPUs in a generation. +defvar ArchFeaturesW64Xnack = [FEATURE_FAST_FMA_F32, FEATURE_FAST_DENORMAL_F32, + FEATURE_XNACK, FEATURE_XNACK_ON_OFF_MODES]; +defvar ArchFeaturesW64XnackSramEcc = ArchFeaturesW64Xnack # [FEATURE_SRAMECC]; +defvar ArchFeaturesW32XnackWgp = [FEATURE_FAST_FMA_F32, FEATURE_FAST_DENORMAL_F32, + FEATURE_WAVE32, FEATURE_XNACK, + FEATURE_XNACK_ON_OFF_MODES, FEATURE_WGP]; +defvar ArchFeaturesW32Wgp = [FEATURE_FAST_FMA_F32, FEATURE_FAST_DENORMAL_F32, + FEATURE_WAVE32, FEATURE_WGP]; + // The code produced for "generic" is only useful for tests and cannot -// reasonably be expected to execute on any particular target. -def : ProcessorModel<"generic", NoSchedModel, - [] ->; +// be expected to execute on any target. +def : ProcessorModel<"generic", NoSchedModel, []>; def : ProcessorModel<"generic-hsa", NoSchedModel, [FeatureFlatAddressSpace] @@ -20,21 +29,22 @@ def : ProcessorModel<"generic-hsa", NoSchedModel, // GCN GFX6 (Southern Islands (SI)). //===------------------------------------------------------------===// -def : ProcessorModel<"gfx600", SIFullSpeedModel, - FeatureISAVersion6_0_0.Features ->; +def GFX600 : AMDGPUProcessorModel<"gfx600", SIFullSpeedModel, + FeatureISAVersion6_0_0.Features, [6, 0, 0]> { + let ArchFeatures = [FEATURE_FAST_FMA_F32]; +} def : ProcessorAlias<"tahiti", "gfx600">; -def : ProcessorModel<"gfx601", SIQuarterSpeedModel, - FeatureISAVersion6_0_1.Features +def GFX601 : AMDGPUProcessorModel<"gfx601", SIQuarterSpeedModel, + FeatureISAVersion6_0_1.Features, [6, 0, 1] >; def : ProcessorAlias<"pitcairn", "gfx601">; def : ProcessorAlias<"verde", "gfx601">; -def : ProcessorModel<"gfx602", SIQuarterSpeedModel, - FeatureISAVersion6_0_2.Features +def GFX602 : AMDGPUProcessorModel<"gfx602", SIQuarterSpeedModel, + FeatureISAVersion6_0_2.Features, [6, 0, 2] >; def : ProcessorAlias<"hainan", "gfx602">; @@ -44,73 +54,80 @@ def : ProcessorAlias<"oland", "gfx602">; // GCN GFX7 (Sea Islands (CI)). //===------------------------------------------------------------===// -def : ProcessorModel<"gfx700", SIQuarterSpeedModel, - FeatureISAVersion7_0_0.Features +def GFX700 : AMDGPUProcessorModel<"gfx700", SIQuarterSpeedModel, + FeatureISAVersion7_0_0.Features, [7, 0, 0] >; def : ProcessorAlias<"kaveri", "gfx700">; -def : ProcessorModel<"gfx701", SIFullSpeedModel, - FeatureISAVersion7_0_1.Features ->; +def GFX701 : AMDGPUProcessorModel<"gfx701", SIFullSpeedModel, + FeatureISAVersion7_0_1.Features, [7, 0, 1]> { + let ArchFeatures = [FEATURE_FAST_FMA_F32]; +} def : ProcessorAlias<"hawaii", "gfx701">; -def : ProcessorModel<"gfx702", SIQuarterSpeedModel, - FeatureISAVersion7_0_2.Features ->; +def GFX702 : AMDGPUProcessorModel<"gfx702", SIQuarterSpeedModel, + FeatureISAVersion7_0_2.Features, [7, 0, 2]> { + let ArchFeatures = [FEATURE_FAST_FMA_F32]; +} -def : ProcessorModel<"gfx703", SIQuarterSpeedModel, - FeatureISAVersion7_0_3.Features +def GFX703 : AMDGPUProcessorModel<"gfx703", SIQuarterSpeedModel, + FeatureISAVersion7_0_3.Features, [7, 0, 3] >; def : ProcessorAlias<"kabini", "gfx703">; def : ProcessorAlias<"mullins", "gfx703">; -def : ProcessorModel<"gfx704", SIQuarterSpeedModel, - FeatureISAVersion7_0_4.Features +def GFX704 : AMDGPUProcessorModel<"gfx704", SIQuarterSpeedModel, + FeatureISAVersion7_0_4.Features, [7, 0, 4] >; def : ProcessorAlias<"bonaire", "gfx704">; -def : ProcessorModel<"gfx705", SIQuarterSpeedModel, - FeatureISAVersion7_0_5.Features +def GFX705 : AMDGPUProcessorModel<"gfx705", SIQuarterSpeedModel, + FeatureISAVersion7_0_5.Features, [7, 0, 5] >; //===------------------------------------------------------------===// // GCN GFX8 (Volcanic Islands (VI)). //===------------------------------------------------------------===// -def : ProcessorModel<"gfx801", SIQuarterSpeedModel, - FeatureISAVersion8_0_1.Features ->; +def GFX801 : AMDGPUProcessorModel<"gfx801", SIQuarterSpeedModel, + FeatureISAVersion8_0_1.Features, [8, 0, 1]> { + let ArchFeatures = ArchFeaturesW64Xnack; +} def : ProcessorAlias<"carrizo", "gfx801">; -def : ProcessorModel<"gfx802", SIQuarterSpeedModel, - FeatureISAVersion8_0_2.Features ->; +def GFX802 : AMDGPUProcessorModel<"gfx802", SIQuarterSpeedModel, + FeatureISAVersion8_0_2.Features, [8, 0, 2]> { + let ArchFeatures = [FEATURE_FAST_DENORMAL_F32, FEATURE_SGPR_INIT_BUG]; +} def : ProcessorAlias<"iceland", "gfx802">; def : ProcessorAlias<"tonga", "gfx802">; -def : ProcessorModel<"gfx803", SIQuarterSpeedModel, - FeatureISAVersion8_0_3.Features ->; +def GFX803 : AMDGPUProcessorModel<"gfx803", SIQuarterSpeedModel, + FeatureISAVersion8_0_3.Features, [8, 0, 3]> { + let ArchFeatures = [FEATURE_FAST_DENORMAL_F32]; +} def : ProcessorAlias<"fiji", "gfx803">; def : ProcessorAlias<"polaris10", "gfx803">; def : ProcessorAlias<"polaris11", "gfx803">; -def : ProcessorModel<"gfx805", SIQuarterSpeedModel, - FeatureISAVersion8_0_5.Features ->; +def GFX805 : AMDGPUProcessorModel<"gfx805", SIQuarterSpeedModel, + FeatureISAVersion8_0_5.Features, [8, 0, 5]> { + let ArchFeatures = [FEATURE_FAST_DENORMAL_F32, FEATURE_SGPR_INIT_BUG]; +} def : ProcessorAlias<"tongapro", "gfx805">; -def : ProcessorModel<"gfx810", SIQuarterSpeedModel, - FeatureISAVersion8_1_0.Features ->; +def GFX810 : AMDGPUProcessorModel<"gfx810", SIQuarterSpeedModel, + FeatureISAVersion8_1_0.Features, [8, 1, 0]> { + let ArchFeatures = [FEATURE_FAST_DENORMAL_F32, FEATURE_XNACK, FEATURE_XNACK_ON_OFF_MODES]; +} def : ProcessorAlias<"stoney", "gfx810">; @@ -118,216 +135,263 @@ def : ProcessorAlias<"stoney", "gfx810">; // GCN GFX9. //===------------------------------------------------------------===// -def : ProcessorModel<"gfx900", SIQuarterSpeedModel, - FeatureISAVersion9_0_0.Features ->; - -def : ProcessorModel<"gfx902", SIQuarterSpeedModel, - FeatureISAVersion9_0_2.Features ->; - -def : ProcessorModel<"gfx904", SIQuarterSpeedModel, - FeatureISAVersion9_0_4.Features ->; - -def : ProcessorModel<"gfx906", SIQuarterSpeedModel, - FeatureISAVersion9_0_6.Features ->; - -def : ProcessorModel<"gfx908", SIQuarterSpeedModel, - FeatureISAVersion9_0_8.Features ->; - -def : ProcessorModel<"gfx909", SIQuarterSpeedModel, - FeatureISAVersion9_0_9.Features ->; - -def : ProcessorModel<"gfx90a", SIDPFullSpeedModel, - FeatureISAVersion9_0_A.Features ->; - -def : ProcessorModel<"gfx90c", SIQuarterSpeedModel, - FeatureISAVersion9_0_C.Features ->; - -def : ProcessorModel<"gfx942", SIDPGFX942FullSpeedModel, - FeatureISAVersion9_4_2.Features ->; - -def : ProcessorModel<"gfx950", SIDPGFX950FullSpeedModel, - FeatureISAVersion9_5_0.Features ->; - -// [gfx900, gfx902, gfx904, gfx906, gfx909, gfx90c] -def : ProcessorModel<"gfx9-generic", SIQuarterSpeedModel, - FeatureISAVersion9_Generic.Features ->; - -// [gfx942] -def : ProcessorModel<"gfx9-4-generic", SIDPGFX942FullSpeedModel, - FeatureISAVersion9_4_Generic.Features ->; +def GFX900 : AMDGPUProcessorModel<"gfx900", SIQuarterSpeedModel, + FeatureISAVersion9_0_0.Features, [9, 0, 0]> { + let ArchFeatures = ArchFeaturesW64Xnack; +} + +def GFX902 : AMDGPUProcessorModel<"gfx902", SIQuarterSpeedModel, + FeatureISAVersion9_0_2.Features, [9, 0, 2]> { + let ArchFeatures = ArchFeaturesW64Xnack; +} + +def GFX904 : AMDGPUProcessorModel<"gfx904", SIQuarterSpeedModel, + FeatureISAVersion9_0_4.Features, [9, 0, 4]> { + let ArchFeatures = ArchFeaturesW64Xnack; +} + +def GFX906 : AMDGPUProcessorModel<"gfx906", SIQuarterSpeedModel, + FeatureISAVersion9_0_6.Features, [9, 0, 6]> { + let ArchFeatures = ArchFeaturesW64XnackSramEcc; +} + +def GFX908 : AMDGPUProcessorModel<"gfx908", SIQuarterSpeedModel, + FeatureISAVersion9_0_8.Features, [9, 0, 8]> { + let ArchFeatures = ArchFeaturesW64XnackSramEcc; +} + +def GFX909 : AMDGPUProcessorModel<"gfx909", SIQuarterSpeedModel, + FeatureISAVersion9_0_9.Features, [9, 0, 9]> { + let ArchFeatures = ArchFeaturesW64Xnack; +} + +def GFX90A : AMDGPUProcessorModel<"gfx90a", SIDPFullSpeedModel, + FeatureISAVersion9_0_A.Features, [9, 0, 0xa]> { + let ArchFeatures = ArchFeaturesW64XnackSramEcc; +} + +def GFX90C : AMDGPUProcessorModel<"gfx90c", SIQuarterSpeedModel, + FeatureISAVersion9_0_C.Features, [9, 0, 0xc]> { + let ArchFeatures = ArchFeaturesW64Xnack; +} + +def GFX942 : AMDGPUProcessorModel<"gfx942", SIDPGFX942FullSpeedModel, + FeatureISAVersion9_4_2.Features, [9, 4, 2]> { + let ArchFeatures = ArchFeaturesW64XnackSramEcc; +} + +def GFX950 : AMDGPUProcessorModel<"gfx950", SIDPGFX950FullSpeedModel, + FeatureISAVersion9_5_0.Features, [9, 5, 0]> { + let ArchFeatures = ArchFeaturesW64XnackSramEcc; +} + +def GFX9_GENERIC : AMDGPUProcessorModel<"gfx9-generic", SIQuarterSpeedModel, + FeatureISAVersion9_Generic.Features, [9, 0, 0]> { + let ArchFeatures = ArchFeaturesW64Xnack; + let CoveredGPUs = [GFX900, GFX902, GFX904, GFX906, GFX909, GFX90C]; +} + +def GFX9_4_GENERIC : AMDGPUProcessorModel<"gfx9-4-generic", SIDPGFX942FullSpeedModel, + FeatureISAVersion9_4_Generic.Features, [9, 4, 0]> { + let ArchFeatures = ArchFeaturesW64XnackSramEcc; + let CoveredGPUs = [GFX942, GFX950]; +} //===----------------------------------------------------------------------===// // GCN GFX10. //===----------------------------------------------------------------------===// -def : ProcessorModel<"gfx1010", GFX10SpeedModel, - FeatureISAVersion10_1_0.Features ->; - -def : ProcessorModel<"gfx1011", GFX10SpeedModel, - FeatureISAVersion10_1_1.Features ->; - -def : ProcessorModel<"gfx1012", GFX10SpeedModel, - FeatureISAVersion10_1_2.Features ->; - -def : ProcessorModel<"gfx1013", GFX10SpeedModel, - FeatureISAVersion10_1_3.Features ->; - -def : ProcessorModel<"gfx1030", GFX10SpeedModel, - FeatureISAVersion10_3_0.Features ->; - -def : ProcessorModel<"gfx1031", GFX10SpeedModel, - FeatureISAVersion10_3_0.Features ->; - -def : ProcessorModel<"gfx1032", GFX10SpeedModel, - FeatureISAVersion10_3_0.Features ->; - -def : ProcessorModel<"gfx1033", GFX10SpeedModel, - FeatureISAVersion10_3_0.Features ->; - -def : ProcessorModel<"gfx1034", GFX10SpeedModel, - FeatureISAVersion10_3_0.Features ->; - -def : ProcessorModel<"gfx1035", GFX10SpeedModel, - FeatureISAVersion10_3_0.Features ->; - -def : ProcessorModel<"gfx1036", GFX10SpeedModel, - FeatureISAVersion10_3_0.Features ->; - -// [gfx1010, gfx1011, gfx1012, gfx1013] -def : ProcessorModel<"gfx10-1-generic", GFX10SpeedModel, - FeatureISAVersion10_1_Generic.Features ->; - -// [gfx1030, gfx1031, gfx1032, gfx1033, gfx1034, gfx1035, gfx1036] -def : ProcessorModel<"gfx10-3-generic", GFX10SpeedModel, - FeatureISAVersion10_3_Generic.Features ->; +def GFX1010 : AMDGPUProcessorModel<"gfx1010", GFX10SpeedModel, + FeatureISAVersion10_1_0.Features, [10, 1, 0]> { + let ArchFeatures = ArchFeaturesW32XnackWgp; +} + +def GFX1011 : AMDGPUProcessorModel<"gfx1011", GFX10SpeedModel, + FeatureISAVersion10_1_1.Features, [10, 1, 1]> { + let ArchFeatures = ArchFeaturesW32XnackWgp; +} + +def GFX1012 : AMDGPUProcessorModel<"gfx1012", GFX10SpeedModel, + FeatureISAVersion10_1_2.Features, [10, 1, 2]> { + let ArchFeatures = ArchFeaturesW32XnackWgp; +} + +def GFX1013 : AMDGPUProcessorModel<"gfx1013", GFX10SpeedModel, + FeatureISAVersion10_1_3.Features, [10, 1, 3]> { + let ArchFeatures = ArchFeaturesW32XnackWgp; +} + +def GFX1030 : AMDGPUProcessorModel<"gfx1030", GFX10SpeedModel, + FeatureISAVersion10_3_0.Features, [10, 3, 0]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX1031 : AMDGPUProcessorModel<"gfx1031", GFX10SpeedModel, + FeatureISAVersion10_3_0.Features, [10, 3, 1]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX1032 : AMDGPUProcessorModel<"gfx1032", GFX10SpeedModel, + FeatureISAVersion10_3_0.Features, [10, 3, 2]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX1033 : AMDGPUProcessorModel<"gfx1033", GFX10SpeedModel, + FeatureISAVersion10_3_0.Features, [10, 3, 3]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX1034 : AMDGPUProcessorModel<"gfx1034", GFX10SpeedModel, + FeatureISAVersion10_3_0.Features, [10, 3, 4]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX1035 : AMDGPUProcessorModel<"gfx1035", GFX10SpeedModel, + FeatureISAVersion10_3_0.Features, [10, 3, 5]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX1036 : AMDGPUProcessorModel<"gfx1036", GFX10SpeedModel, + FeatureISAVersion10_3_0.Features, [10, 3, 6]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX10_1_GENERIC : AMDGPUProcessorModel<"gfx10-1-generic", GFX10SpeedModel, + FeatureISAVersion10_1_Generic.Features, [10, 1, 0]> { + let ArchFeatures = ArchFeaturesW32XnackWgp; + let CoveredGPUs = [GFX1010, GFX1011, GFX1012, GFX1013]; +} + +def GFX10_3_GENERIC : AMDGPUProcessorModel<"gfx10-3-generic", GFX10SpeedModel, + FeatureISAVersion10_3_Generic.Features, [10, 3, 0]> { + let ArchFeatures = ArchFeaturesW32Wgp; + let CoveredGPUs = [GFX1030, GFX1031, GFX1032, GFX1033, GFX1034, GFX1035, GFX1036]; +} //===----------------------------------------------------------------------===// // GCN GFX11. //===----------------------------------------------------------------------===// -def : ProcessorModel<"gfx1100", GFX11SpeedModel, - FeatureISAVersion11_0_0.Features ->; - -def : ProcessorModel<"gfx1101", GFX11SpeedModel, - FeatureISAVersion11_0_1.Features ->; - -def : ProcessorModel<"gfx1102", GFX11SpeedModel, - FeatureISAVersion11_0_2.Features ->; - -def : ProcessorModel<"gfx1103", GFX11SpeedModel, - FeatureISAVersion11_0_3.Features ->; - -def : ProcessorModel<"gfx1150", GFX11SpeedModel, - FeatureISAVersion11_5_0.Features ->; - -def : ProcessorModel<"gfx1151", GFX11SpeedModel, - FeatureISAVersion11_5_1.Features ->; - -def : ProcessorModel<"gfx1152", GFX11SpeedModel, - FeatureISAVersion11_5_2.Features ->; - -def : ProcessorModel<"gfx1153", GFX11SpeedModel, - FeatureISAVersion11_5_Common.Features ->; - -def : ProcessorModel<"gfx1154", GFX11SpeedModel, - FeatureISAVersion11_5_Common.Features ->; - -def : ProcessorModel<"gfx1170", GFX11SpeedModel, - FeatureISAVersion11_7_Common.Features ->; - -def : ProcessorModel<"gfx1171", GFX11SpeedModel, - FeatureISAVersion11_7_Common.Features ->; - -def : ProcessorModel<"gfx1172", GFX11SpeedModel, - FeatureISAVersion11_7_Common.Features ->; - -// [gfx1100, gfx1101, gfx1102, gfx1103, -// gfx1150, gfx1151, gfx1152, gfx1153, gfx1154] -def : ProcessorModel<"gfx11-generic", GFX11SpeedModel, - FeatureISAVersion11_Generic.Features ->; - -// [gfx1170, gfx1171, gfx1172] -def : ProcessorModel<"gfx11-7-generic", GFX11SpeedModel, - FeatureISAVersion11_7_Generic.Features ->; +def GFX1100 : AMDGPUProcessorModel<"gfx1100", GFX11SpeedModel, + FeatureISAVersion11_0_0.Features, [11, 0, 0]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX1101 : AMDGPUProcessorModel<"gfx1101", GFX11SpeedModel, + FeatureISAVersion11_0_1.Features, [11, 0, 1]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX1102 : AMDGPUProcessorModel<"gfx1102", GFX11SpeedModel, + FeatureISAVersion11_0_2.Features, [11, 0, 2]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX1103 : AMDGPUProcessorModel<"gfx1103", GFX11SpeedModel, + FeatureISAVersion11_0_3.Features, [11, 0, 3]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX1150 : AMDGPUProcessorModel<"gfx1150", GFX11SpeedModel, + FeatureISAVersion11_5_0.Features, [11, 5, 0]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX1151 : AMDGPUProcessorModel<"gfx1151", GFX11SpeedModel, + FeatureISAVersion11_5_1.Features, [11, 5, 1]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX1152 : AMDGPUProcessorModel<"gfx1152", GFX11SpeedModel, + FeatureISAVersion11_5_2.Features, [11, 5, 2]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX1153 : AMDGPUProcessorModel<"gfx1153", GFX11SpeedModel, + FeatureISAVersion11_5_Common.Features, [11, 5, 3]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX1154 : AMDGPUProcessorModel<"gfx1154", GFX11SpeedModel, + FeatureISAVersion11_5_Common.Features, [11, 5, 4]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX1170 : AMDGPUProcessorModel<"gfx1170", GFX11SpeedModel, + FeatureISAVersion11_7_Common.Features, [11, 7, 0]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX1171 : AMDGPUProcessorModel<"gfx1171", GFX11SpeedModel, + FeatureISAVersion11_7_Common.Features, [11, 7, 1]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX1172 : AMDGPUProcessorModel<"gfx1172", GFX11SpeedModel, + FeatureISAVersion11_7_Common.Features, [11, 7, 2]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX11_GENERIC : AMDGPUProcessorModel<"gfx11-generic", GFX11SpeedModel, + FeatureISAVersion11_Generic.Features, [11, 0, 3]> { + let ArchFeatures = ArchFeaturesW32Wgp; + let CoveredGPUs = [GFX1100, GFX1101, GFX1102, GFX1103, GFX1150, GFX1151, GFX1152, GFX1153, + GFX1154]; +} + +def GFX11_7_GENERIC : AMDGPUProcessorModel<"gfx11-7-generic", GFX11SpeedModel, + FeatureISAVersion11_7_Generic.Features, [11, 7, 0]> { + let ArchFeatures = ArchFeaturesW32Wgp; + let CoveredGPUs = [GFX1170, GFX1171, GFX1172]; +} //===----------------------------------------------------------------------===// // GCN GFX12. //===----------------------------------------------------------------------===// -def : ProcessorModel<"gfx1200", GFX12SpeedModel, - FeatureISAVersion12.Features ->; - -def : ProcessorModel<"gfx1201", GFX12SpeedModel, - FeatureISAVersion12.Features ->; - -// [gfx1200, gfx1201] -def : ProcessorModel<"gfx12-generic", GFX12SpeedModel, - FeatureISAVersion12_Generic.Features ->; - -def : ProcessorModel<"gfx1250", GFX1250SpeedModel, - FeatureISAVersion12_50.Features ->; - -def : ProcessorModel<"gfx1251", GFX1251SpeedModel, - FeatureISAVersion12_51.Features ->; - -// [gfx1250, gfx1251] -def : ProcessorModel<"gfx12-5-generic", GFX125xGenericSpeedModel, - FeatureISAVersion12_5_Generic.Features ->; +def GFX1200 : AMDGPUProcessorModel<"gfx1200", GFX12SpeedModel, + FeatureISAVersion12.Features, [12, 0, 0]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX1201 : AMDGPUProcessorModel<"gfx1201", GFX12SpeedModel, + FeatureISAVersion12.Features, [12, 0, 1]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} + +def GFX12_GENERIC : AMDGPUProcessorModel<"gfx12-generic", GFX12SpeedModel, + FeatureISAVersion12_Generic.Features, [12, 0, 0]> { + let ArchFeatures = ArchFeaturesW32Wgp; + let CoveredGPUs = [GFX1200, GFX1201]; +} + +def GFX1250 : AMDGPUProcessorModel<"gfx1250", GFX1250SpeedModel, + FeatureISAVersion12_50.Features, [12, 5, 0]> { + let ArchFeatures = [FEATURE_FAST_FMA_F32, FEATURE_FAST_DENORMAL_F32, FEATURE_WAVE32, FEATURE_XNACK, FEATURE_SRAMECC]; +} + +def GFX1251 : AMDGPUProcessorModel<"gfx1251", GFX1251SpeedModel, + FeatureISAVersion12_51.Features, [12, 5, 1]> { + let ArchFeatures = [FEATURE_FAST_FMA_F32, FEATURE_FAST_DENORMAL_F32, FEATURE_WAVE32, FEATURE_XNACK, FEATURE_SRAMECC]; +} + +def GFX12_5_GENERIC : AMDGPUProcessorModel<"gfx12-5-generic", GFX125xGenericSpeedModel, + FeatureISAVersion12_5_Generic.Features, [12, 5, 0]> { + let ArchFeatures = [FEATURE_FAST_FMA_F32, FEATURE_FAST_DENORMAL_F32, FEATURE_WAVE32, FEATURE_XNACK]; + let CoveredGPUs = [GFX1250, GFX1251]; +} //===----------------------------------------------------------------------===// // GCN GFX13. //===----------------------------------------------------------------------===// -def : ProcessorModel<"gfx1310", GFX12SpeedModel, - FeatureISAVersion13.Features ->; +def GFX1310 : AMDGPUProcessorModel<"gfx1310", GFX12SpeedModel, + FeatureISAVersion13.Features, [13, 1, 0]> { + let ArchFeatures = ArchFeaturesW32Wgp; +} -// [gfx1310] -def : ProcessorModel<"gfx13-generic", GFX12SpeedModel, - FeatureISAVersion13_Generic.Features ->; +def GFX13_GENERIC : AMDGPUProcessorModel<"gfx13-generic", GFX12SpeedModel, + FeatureISAVersion13_Generic.Features, [13, 1, 0]> { + let ArchFeatures = ArchFeaturesW32Wgp; + let CoveredGPUs = [GFX1310]; +} diff --git a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp index dbc3b59a0861b..a1e7a12e55d85 100644 --- a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp +++ b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp @@ -24,10 +24,10 @@ using namespace AMDGPU; StringRef llvm::AMDGPU::getArchFamilyNameAMDGCN(GPUKind AK) { StringRef ArchName = getArchNameAMDGCN(AK); - assert((AK >= GK_AMDGCN_GENERIC_FIRST && AK <= GK_AMDGCN_GENERIC_LAST) == + assert((AK >= GK_AMDGPU_GENERIC_FIRST && AK <= GK_AMDGPU_GENERIC_LAST) == ArchName.ends_with("-generic") && "Generic AMDGCN arch not classified correctly!"); - if (AK >= GK_AMDGCN_GENERIC_FIRST && AK <= GK_AMDGCN_GENERIC_LAST) { + if (AK >= GK_AMDGPU_GENERIC_FIRST && AK <= GK_AMDGPU_GENERIC_LAST) { // Return the part before the first '-', e.g. "gfx9-4-generic" -> "gfx9". return ArchName.take_front(ArchName.find('-')); } @@ -36,10 +36,10 @@ StringRef llvm::AMDGPU::getArchFamilyNameAMDGCN(GPUKind AK) { Triple::SubArchType llvm::AMDGPU::getSubArch(GPUKind AK) { switch (AK) { -#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \ +#define AMDGPU_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \ case ENUM: \ return SUBARCH; -#include "llvm/TargetParser/AMDGPUTargetParser.def" +#include "llvm/TargetParser/AMDGPUTargetParserDef.inc" default: return Triple::SubArchType::NoSubArch; } @@ -48,10 +48,10 @@ Triple::SubArchType llvm::AMDGPU::getSubArch(GPUKind AK) { AMDGPU::GPUKind llvm::AMDGPU::getGPUKindFromSubArch(Triple::SubArchType SubArch) { switch (SubArch) { -#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \ +#define AMDGPU_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \ case SUBARCH: \ return ENUM; -#include "llvm/TargetParser/AMDGPUTargetParser.def" +#include "llvm/TargetParser/AMDGPUTargetParserDef.inc" default: return GK_NONE; } @@ -186,10 +186,10 @@ std::string AMDGPU::mergeSubArch(const Triple &A, const Triple &B) { StringRef llvm::AMDGPU::getArchNameAMDGCN(GPUKind AK) { switch (AK) { -#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \ +#define AMDGPU_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \ case ENUM: \ return NAME; -#include "llvm/TargetParser/AMDGPUTargetParser.def" +#include "llvm/TargetParser/AMDGPUTargetParserDef.inc" default: return ""; } @@ -253,9 +253,9 @@ StringRef llvm::AMDGPU::getArchNameR600(GPUKind AK) { AMDGPU::GPUKind llvm::AMDGPU::parseArchAMDGCN(StringRef CPU) { return StringSwitch<AMDGPU::GPUKind>(CPU) -#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) .Case(NAME, ENUM) -#define AMDGCN_GPU_ALIAS(NAME, ENUM) .Case(NAME, ENUM) -#include "llvm/TargetParser/AMDGPUTargetParser.def" +#define AMDGPU_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) .Case(NAME, ENUM) +#define AMDGPU_GPU_ALIAS(NAME, ENUM) .Case(NAME, ENUM) +#include "llvm/TargetParser/AMDGPUTargetParserDef.inc" .Case("generic", AMDGPU::GPUKind::GK_GFX600) .Case("generic-hsa", AMDGPU::GPUKind::GK_GFX700) .Default(AMDGPU::GPUKind::GK_NONE); @@ -271,10 +271,10 @@ AMDGPU::GPUKind llvm::AMDGPU::parseArchR600(StringRef CPU) { unsigned AMDGPU::getArchAttrAMDGCN(GPUKind AK) { switch (AK) { -#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \ +#define AMDGPU_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \ case ENUM: \ return FEATURES; -#include "llvm/TargetParser/AMDGPUTargetParser.def" +#include "llvm/TargetParser/AMDGPUTargetParserDef.inc" default: return FEATURE_NONE; } @@ -282,10 +282,10 @@ unsigned AMDGPU::getArchAttrAMDGCN(GPUKind AK) { unsigned AMDGPU::getArchAttrAMDGCN(Triple::SubArchType SubArch) { switch (SubArch) { -#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \ +#define AMDGPU_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \ case SUBARCH: \ return FEATURES; -#include "llvm/TargetParser/AMDGPUTargetParser.def" +#include "llvm/TargetParser/AMDGPUTargetParserDef.inc" default: return FEATURE_NONE; } @@ -306,13 +306,13 @@ void AMDGPU::fillValidArchListAMDGCN(SmallVectorImpl<StringRef> &Values, Triple::SubArchType SubArch) { // XXX: Should this only report unique canonical names? // An alias shares its GPU's GPUKind, so it is filtered alongside it. -#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \ +#define AMDGPU_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \ if (isCPUValidForSubArch(SubArch, ENUM)) \ Values.push_back(NAME); -#define AMDGCN_GPU_ALIAS(NAME, ENUM) \ +#define AMDGPU_GPU_ALIAS(NAME, ENUM) \ if (isCPUValidForSubArch(SubArch, ENUM)) \ Values.push_back(NAME); -#include "llvm/TargetParser/AMDGPUTargetParser.def" +#include "llvm/TargetParser/AMDGPUTargetParserDef.inc" } void AMDGPU::fillValidArchListR600(SmallVectorImpl<StringRef> &Values) { @@ -335,10 +335,10 @@ AMDGPU::IsaVersion AMDGPU::getIsaVersion(StringRef GPU) { switch (AK) { #define MAKE_ISAVERSION(A, B, C) {A, B, C} -#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \ +#define AMDGPU_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \ case ENUM: \ return MAKE_ISAVERSION ISAVERSION; -#include "llvm/TargetParser/AMDGPUTargetParser.def" +#include "llvm/TargetParser/AMDGPUTargetParserDef.inc" #undef MAKE_ISAVERSION default: return {0, 0, 0}; @@ -348,10 +348,10 @@ AMDGPU::IsaVersion AMDGPU::getIsaVersion(StringRef GPU) { AMDGPU::IsaVersion AMDGPU::getIsaVersion(Triple::SubArchType SubArch) { switch (SubArch) { #define MAKE_ISAVERSION(A, B, C) {A, B, C} -#define AMDGCN_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \ +#define AMDGPU_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES) \ case SUBARCH: \ return MAKE_ISAVERSION ISAVERSION; -#include "llvm/TargetParser/AMDGPUTargetParser.def" +#include "llvm/TargetParser/AMDGPUTargetParserDef.inc" #undef MAKE_ISAVERSION default: return {0, 0, 0}; diff --git a/llvm/test/TableGen/AMDGPUTargetDefErrors.td b/llvm/test/TableGen/AMDGPUTargetDefErrors.td index 922ca47353d58..7e72f0ea23489 100644 --- a/llvm/test/TableGen/AMDGPUTargetDefErrors.td +++ b/llvm/test/TableGen/AMDGPUTargetDefErrors.td @@ -5,6 +5,8 @@ // RUN: | FileCheck %t/dup-processor.td -DFILE=%t/dup-processor.td --implicit-check-not="error:" // RUN: not llvm-tblgen -gen-amdgpu-target-def -I %p/../../include %t/alias-shadows-processor.td 2>&1 \ // RUN: | FileCheck %t/alias-shadows-processor.td -DFILE=%t/alias-shadows-processor.td --implicit-check-not="error:" +// RUN: not llvm-tblgen -gen-amdgpu-target-def -I %p/../../include %t/bad-isa-version.td 2>&1 \ +// RUN: | FileCheck %t/bad-isa-version.td -DFILE=%t/bad-isa-version.td --implicit-check-not="error:" // Verify the validation performed by the -gen-amdgpu-target-def backend. @@ -40,3 +42,17 @@ def : ProcessorModel<"gfx900", NoSchedModel, []>, AMDGPUGPUInfo; // An alias name must not collide with a canonical GPU name. // CHECK: [[FILE]]:[[#@LINE+1]]:1: error: duplicate AMDGPU processor name 'gfx900' def : ProcessorAlias<"gfx900", "gfx900">; + +//--- bad-isa-version.td +include "llvm/Target/Target.td" +def MyTarget : Target; +class AMDGPUArchFeature<string spelling> { string Spelling = spelling; } +class AMDGPUGPUInfo<list<int> isa = []> { + list<AMDGPUArchFeature> ArchFeatures = []; + list<int> IsaVersion = isa; + list<string> CoveredGPUs = []; +} +// A malformed IsaVersion is reported (not asserted), so this stays a clean +// diagnostic in release builds. +// CHECK: [[FILE]]:[[#@LINE+1]]:1: error: GPU 'gfx900' must have a 3-element [major, minor, stepping] IsaVersion +def : ProcessorModel<"gfx900", NoSchedModel, []>, AMDGPUGPUInfo<[9, 0]>; diff --git a/llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp b/llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp index e8a013227411a..e28f7f93da371 100644 --- a/llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp @@ -29,11 +29,47 @@ static void emitGPUKindEnum(raw_ostream &OS, StringRef Name) { OS << ((C == '-') ? '_' : toUpper(C)); } +// Derive the Triple::SubArchType from an AMDGPU processor name, e.g. "gfx90a" +// -> Triple::AMDGPUSubArch90A. A generic target uses its family's major +// subarch, e.g. "gfx9-generic" -> Triple::AMDGPUSubArch9. +static void emitSubArch(raw_ostream &OS, StringRef Name) { + StringRef Suffix = Name; + Suffix.consume_front("gfx"); + Suffix.consume_back("-generic"); + + OS << "Triple::AMDGPUSubArch"; + for (char C : Suffix) + OS << ((C == '-') ? '_' : toUpper(C)); +} + +// Emit the ISA version tuple "(major, minor, stepping)". +static void emitIsaVersion(raw_ostream &OS, const Record *Rec) { + std::vector<int64_t> V = Rec->getValueAsListOfInts("IsaVersion"); + if (V.size() != 3) { + PrintFatalError(Rec->getLoc(), + "GPU '" + Rec->getValueAsString("Name") + + "' must have a 3-element [major, minor, stepping] " + "IsaVersion"); + } + + OS << '(' << V[0] << ", " << V[1] << ", " << V[2] << ')'; +} + // A canonical GPU or a ProcessorAlias. namespace { struct GPUEntry { const Record *Rec; bool IsAlias; + + // An entry is generic if it is (or aliases) a "gfxN-generic" family target, + // i.e. a canonical that covers a set of concrete GPUs (non-empty + // CoveredGPUs). + // \p Canonicals maps canonical GPU names to their records. + bool isGeneric(const StringMap<const Record *> &Canonicals) const { + const Record *Canon = + IsAlias ? Canonicals.lookup(Rec->getValueAsString("Alias")) : Rec; + return Canon && !Canon->getValueAsListOfDefs("CoveredGPUs").empty(); + } }; } // namespace @@ -50,18 +86,29 @@ static void emitFeatureExpr(raw_ostream &OS, const Record *Rec) { OS << "FEATURE_NONE"; } -// Collect canonical GPUs and their aliases, in TableGen definition order. -static std::vector<GPUEntry> collectGPUs(const RecordKeeper &RK) { +// Collect canonical GPUs and their aliases, in TableGen definition order. R600 +// GPUs are plain Processor records; AMDGPU GPUs are ProcessorModel records (a +// Processor subclass), so \p WantR600 selects the family to emit. +static std::vector<GPUEntry> collectGPUs(const RecordKeeper &RK, + bool WantR600) { ArrayRef<const Record *> GPUs = RK.getAllDerivedDefinitions("AMDGPUGPUInfo"); std::vector<GPUEntry> Entries; Entries.reserve(GPUs.size()); - for (const Record *Rec : GPUs) + for (const Record *Rec : GPUs) { + if (Rec->isSubClassOf("ProcessorModel") == WantR600) + continue; Entries.push_back({Rec, /*IsAlias=*/false}); + } - for (const Record *Rec : - RK.getAllDerivedDefinitionsIfDefined("ProcessorAlias")) - Entries.push_back({Rec, /*IsAlias=*/true}); + // Aliases only make sense when their canonical is present, so only gather + // them for the family being emitted. + if (!Entries.empty()) { + for (const Record *Rec : + RK.getAllDerivedDefinitionsIfDefined("ProcessorAlias")) + Entries.push_back({Rec, /*IsAlias=*/true}); + } + // Sort to preserve declaration order instead of name order. sort(Entries, [](const GPUEntry &A, const GPUEntry &B) { return A.Rec->getID() < B.Rec->getID(); }); @@ -96,8 +143,10 @@ static void validate(ArrayRef<GPUEntry> Entries) { } static void emitR600(raw_ostream &OS, const RecordKeeper &RK) { - std::vector<GPUEntry> Entries = collectGPUs(RK); + std::vector<GPUEntry> Entries = collectGPUs(RK, /*WantR600=*/true); validate(Entries); + if (Entries.empty()) + return; OS << "#ifndef R600_GPU\n" "#define R600_GPU(NAME, ENUM, FEATURES)\n" @@ -125,9 +174,70 @@ static void emitR600(raw_ostream &OS, const RecordKeeper &RK) { "#undef R600_GPU_ALIAS\n"; } +static void emitAMDGPUEntry(raw_ostream &OS, const GPUEntry &E) { + StringRef Name = E.Rec->getValueAsString("Name"); + if (E.IsAlias) { + OS << "AMDGPU_GPU_ALIAS(\"" << Name << "\", "; + emitGPUKindEnum(OS, E.Rec->getValueAsString("Alias")); + OS << ")\n"; + } else { + OS << "AMDGPU_GPU(\"" << Name << "\", "; + emitGPUKindEnum(OS, Name); + OS << ", "; + emitSubArch(OS, Name); + OS << ", "; + emitIsaVersion(OS, E.Rec); + OS << ", "; + emitFeatureExpr(OS, E.Rec); + OS << ")\n"; + } +} + +static void emitAMDGPU(raw_ostream &OS, const RecordKeeper &RK) { + std::vector<GPUEntry> Entries = collectGPUs(RK, /*WantR600=*/false); + validate(Entries); + if (Entries.empty()) + return; + + StringMap<const Record *> Canonicals; + for (const GPUEntry &E : Entries) { + if (!E.IsAlias) + Canonicals[E.Rec->getValueAsString("Name")] = E.Rec; + } + + OS << "#ifndef AMDGPU_GPU\n" + "#define AMDGPU_GPU(NAME, ENUM, SUBARCH, ISAVERSION, FEATURES)\n" + "#endif\n\n" + "#ifndef AMDGPU_GPU_ALIAS\n" + "#define AMDGPU_GPU_ALIAS(NAME, ENUM)\n" + "#endif\n\n"; + + // The GPUKind enum is positional and code relies on the generic targets + // being a contiguous block at the end (GK_AMDGPU_GENERIC_FIRST/LAST), so emit + // all non-generic entries first, then the generics, each group preserving + // TableGen definition order. + for (const GPUEntry &E : Entries) { + if (!E.isGeneric(Canonicals)) + emitAMDGPUEntry(OS, E); + } + + for (const GPUEntry &E : Entries) { + if (E.isGeneric(Canonicals)) + emitAMDGPUEntry(OS, E); + } + + OS << "\n#undef AMDGPU_GPU\n" + "#undef AMDGPU_GPU_ALIAS\n"; +} + static void emitAMDGPUTargetDef(const RecordKeeper &RK, raw_ostream &OS) { OS << "// Autogenerated by AMDGPUTargetDefEmitter.cpp\n\n"; + // R600 processors are Processor records; AMDGPU processors are + // ProcessorModel records. R600.td and AMDGPU.td are separate top-level files + // (neither includes the other), so exactly one family is present in a given + // run; the other section emits nothing. emitR600(OS, RK); + emitAMDGPU(OS, RK); } static TableGen::Emitter::Opt X("gen-amdgpu-target-def", emitAMDGPUTargetDef, _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
