================
@@ -272,14 +277,36 @@ static std::optional<ArgClassification>
convertABIArgInfo(const llvm::abi::ArgInfo &info, MLIRContext *ctx,
mlir::Type origTy) {
if (info.isDirect()) {
- // A scalar passes as-is; only an aggregate carries a coercion type.
- if (!origTy || !isa<cir::RecordType, cir::ArrayType>(origTy))
+ // A non-null coerce type does not by itself mean the value needs a
rewrite:
+ // the classifier names one even where it matches the natural type. Three
+ // cases do need one: an aggregate must be unpacked into the register(s)
+ // holding it, a multi-register tuple coerce must be flattened into one
+ // argument per field, and a scalar the classifier widened must travel in
+ // the wider type. Any other scalar keeps its natural CIR type, which a
+ // null coercion denotes here. Keeping it off the abiTypeToCIR path is
+ // also what preserves its ABI alignment: that mapping does not carry the
+ // bit-precise flag. A _BitInt(128) coerces to the bit-precise integer
+ // itself, so routing it through would produce a plain !cir.int<s, 128>
+ // with __int128's 16-byte alignment instead of 8.
+ const llvm::abi::Type *coerceAbi = info.getCoerceToType();
+ bool isAggregate = origTy && isa<cir::RecordType, cir::ArrayType>(origTy);
----------------
erichkeane wrote:
```suggestion
bool isAggregate = isa_and_present<cir::RecordType, cir::ArrayType>(origTy);
```
https://github.com/llvm/llvm-project/pull/212668
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