================ @@ -0,0 +1,82 @@ +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck %s + +; The AMDGPU data layout has to give i128 an ABI alignment of 16, matching the +; ABI implemented by Clang, whose AMDGPUTargetInfo leaves Int128Align at its +; 128-bit default. Without an explicit entry the alignment would be inherited +; from the i64:64 entry, and the layout LLVM computes for an aggregate would ---------------- simeonschaub wrote:
Apparently not, NVPTX at least also sets this explicitly: https://github.com/llvm/llvm-project/blob/db8d8fdd9831d2b8b2fdeb65498a41e7a8a7456c/llvm/lib/TargetParser/TargetDataLayout.cpp#L484 https://github.com/llvm/llvm-project/pull/213523 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
