https://github.com/zjin-lcf created https://github.com/llvm/llvm-project/pull/213691
The `__CLC_HAS_ATOMIC` guards in `clc_atomic_def.inc` and `clc_atomic_compare_exchange.inc` restrict atomics to 32-bit types when `__NVPTX__` is defined. Per the discussion in #146814, that exclusion was added to silence the `large atomic operation may incur significant performance penalty` warning on 32-bit targets, but `__NVPTX__` is defined for both nvptx and nvptx64. NVPTX sets `MaxAtomicInlineWidth` to the target pointer width (`clang/lib/Basic/Targets/NVPTX.cpp`), so nvptx64 lowers 64-bit atomics natively and never emits that warning; only the 32-bit nvptx target did. libclc no longer builds a 32-bit nvptx target (`LIBCLC_ARCHS_NVPTX` is just `nvptx64`), so the exclusion now only prevents nvptx64 from getting the 64-bit atomics that `atomic_decl.inc` declares unconditionally, leaving them declared but never defined. This restricts the 32-bit-only guard to `__SPIR32__` in both files, matching the intent of the original change. ## Test plan Compiling `clc/lib/generic/atomic/*.cl` for `nvptx64--nvidiacl` with the libclc build flags: - No new warnings, in particular no `large atomic operation` warnings. For contrast, the same sources built for 32-bit `nvptx--nvidiacl` do produce them, which is the case the `__NVPTX__` guard was covering. - `clc_atomic_compare_exchange.cl` now defines 21 functions instead of 12; the `long`/`ulong`/`double` overloads are defined for global (AS1), local (AS3) and generic address spaces, where previously they were declared but undefined. - The 64-bit overloads emit `cmpxchg ... i64`, and the linked atomic bitcode has no undefined symbols, i.e. no atomic libcalls are introduced. Downstream this fixes `Unresolved extern function '_Z29__clc_atomic_compare_exchange...'` ptxas failures in intel/llvm for SYCL programs using 64-bit compare-and-swap (see intel/llvm#22750, where it was verified end-to-end on an A100 with `-fsycl-targets=nvptx64-nvidia-cuda`). intel/llvm already carries the `clc_atomic_def.inc` half of this change locally as a not-yet-upstreamed patch; `clc_atomic_compare_exchange.inc` was missed there. >From 67c4e670046237b93eca42861948f0756d66431c Mon Sep 17 00:00:00 2001 From: Zheming Jin <[email protected]> Date: Mon, 3 Aug 2026 09:47:48 -0500 Subject: [PATCH] [libclc] Enable 64-bit atomics for nvptx64 The `__CLC_HAS_ATOMIC` guards in `clc_atomic_def.inc` and `clc_atomic_compare_exchange.inc` restrict atomics to 32-bit types for `__NVPTX__`. That exclusion was added to silence the "large atomic operation may incur significant performance penalty" warning on 32-bit targets, but `__NVPTX__` is defined for both nvptx and nvptx64. NVPTX sets `MaxAtomicInlineWidth` to the target pointer width, so nvptx64 lowers 64-bit atomics natively and never emits that warning; only the 32-bit nvptx target did. libclc no longer builds a 32-bit nvptx target (`LIBCLC_ARCHS_NVPTX` is just `nvptx64`), so the exclusion now only prevents nvptx64 from getting the 64-bit atomics that `atomic_decl.inc` declares unconditionally, leaving them declared but never defined. Restrict the 32-bit-only guard to `__SPIR32__`, so nvptx64 defines the 64-bit atomics. --- .../clc/lib/generic/atomic/clc_atomic_compare_exchange.inc | 6 +++--- libclc/clc/lib/generic/atomic/clc_atomic_def.inc | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/libclc/clc/lib/generic/atomic/clc_atomic_compare_exchange.inc b/libclc/clc/lib/generic/atomic/clc_atomic_compare_exchange.inc index d28e3c72e465e..3d37ba52d370d 100644 --- a/libclc/clc/lib/generic/atomic/clc_atomic_compare_exchange.inc +++ b/libclc/clc/lib/generic/atomic/clc_atomic_compare_exchange.inc @@ -8,16 +8,16 @@ #ifdef __CLC_SCALAR -#if defined(__SPIR32__) || defined(__NVPTX__) +#ifdef __SPIR32__ #if (defined(__CLC_FPSIZE) && __CLC_FPSIZE <= 32) || \ (defined(__CLC_GENSIZE) && (__CLC_GENSIZE == 32)) #define __CLC_HAS_ATOMIC #endif -#else // defined(__SPIR32__) || defined(__NVPTX__) +#else // __SPIR32__ #if defined(__CLC_FPSIZE) || (__CLC_GENSIZE >= 32) #define __CLC_HAS_ATOMIC #endif -#endif // defined(__SPIR32__) || defined(__NVPTX__) +#endif // __SPIR32__ #ifdef __CLC_HAS_ATOMIC diff --git a/libclc/clc/lib/generic/atomic/clc_atomic_def.inc b/libclc/clc/lib/generic/atomic/clc_atomic_def.inc index 2af450ffbbe5c..bf40ff626fc81 100644 --- a/libclc/clc/lib/generic/atomic/clc_atomic_def.inc +++ b/libclc/clc/lib/generic/atomic/clc_atomic_def.inc @@ -8,16 +8,16 @@ #ifdef __CLC_SCALAR -#if defined(__SPIR32__) || defined(__NVPTX__) +#ifdef __SPIR32__ #if (defined(__CLC_FPSIZE) && __CLC_FPSIZE <= 32) || \ (defined(__CLC_GENSIZE) && (__CLC_GENSIZE == 32)) #define __CLC_HAS_ATOMIC #endif -#else // defined(__SPIR32__) || defined(__NVPTX__) +#else // __SPIR32__ #if defined(__CLC_FPSIZE) || (__CLC_GENSIZE >= 32) #define __CLC_HAS_ATOMIC #endif -#endif // defined(__SPIR32__) || defined(__NVPTX__) +#endif // __SPIR32__ #ifdef __CLC_HAS_ATOMIC _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
