llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Andy Kaylor (andykaylor) <details> <summary>Changes</summary> This change replaces some locations where the Neon builtin handling was calling LLVM intrinsics directly for FMA and sqrt operations rather than using the CIR operations. Using the CIR operations will be necessary to get the best constrained FP handling. This will still require setting the fenv attribute on these operations when needed. This change is just the first of a few preliminary changes needed to get us in a good state to add the constrained FP handling. Assisted-by: Cursor / Grok 4.5 --- Patch is 50.71 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/213800.diff 5 Files Affected: - (modified) clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp (+36-36) - (modified) clang/test/CodeGen/AArch64/neon/fullfp16.c (+3-3) - (modified) clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c (+14-14) - (modified) clang/test/CodeGen/AArch64/neon/fused-multiply.c (+36-36) - (modified) clang/test/CodeGen/AArch64/neon/intrinsics.c (+4-4) ``````````diff diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index dbc42404e11a4..df5f42e595556 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -84,17 +84,6 @@ findARMVectorIntrinsicInMap(ArrayRef<IntrinsicInfo> intrinsicMap, //===----------------------------------------------------------------------===// // Generic helpers //===----------------------------------------------------------------------===// -// Emit an intrinsic where all operands are of the same type as the result. -// Depending on mode, this may be a constrained floating-point intrinsic. -static mlir::Value -emitCallMaybeConstrainedBuiltin(CIRGenBuilderTy &builder, mlir::Location loc, - StringRef intrName, mlir::Type retTy, - llvm::SmallVector<mlir::Value> &ops) { - assert(!cir::MissingFeatures::emitConstrainedFPCall()); - - return builder.emitIntrinsicCallOp(loc, intrName, retTy, ops); -} - static llvm::StringRef getLLVMIntrNameNoPrefix(llvm::Intrinsic::ID intrID) { llvm::StringRef llvmIntrName = llvm::Intrinsic::getBaseName(intrID); assert(llvmIntrName.starts_with("llvm.") && "Not an LLVM intrinsic!"); @@ -980,14 +969,14 @@ static mlir::Value emitCommonNeonBuiltinExpr( case NEON::BI__builtin_neon_vfma_v: case NEON::BI__builtin_neon_vfmaq_v: { // NEON intrinsic: vfma(q)(accumulator, multiplicand1, multiplicand2) - // LLVM intrinsic: fma(multiplicand1, multiplicand2, accumulator) - // Reorder arguments to match LLVM fma signature. + // CIR fma: fma(multiplicand1, multiplicand2, accumulator) + // Reorder arguments to match fma signature. mlir::Value op0 = cgf.getBuilder().createBitcast(ops[0], ty); mlir::Value op1 = cgf.getBuilder().createBitcast(ops[1], ty); mlir::Value op2 = cgf.getBuilder().createBitcast(ops[2], ty); llvm::SmallVector<mlir::Value> fmaOps = {op1, op2, op0}; - return emitCallMaybeConstrainedBuiltin(cgf.getBuilder(), loc, "fma", ty, - fmaOps); + return emitNeonCallToOp<cir::FMAOp>(cgf.cgm, cgf.getBuilder(), {ty, ty, ty}, + fmaOps, std::nullopt, ty, loc); } case NEON::BI__builtin_neon_vld1_v: case NEON::BI__builtin_neon_vld1q_v: @@ -2706,18 +2695,21 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, return builder.createFMul(loc, ops[0], ops[1]); case NEON::BI__builtin_neon_vdivh_f16: return builder.createFDiv(loc, ops[0], ops[1]); - case NEON::BI__builtin_neon_vfmah_f16: - // NEON intrinsic puts accumulator first, unlike the LLVM fma. + case NEON::BI__builtin_neon_vfmah_f16: { + // NEON intrinsic puts accumulator first, unlike fma. std::rotate(ops.begin(), ops.begin() + 1, ops.end()); - return emitCallMaybeConstrainedBuiltin(builder, loc, "fma", - convertType(expr->getType()), ops); - break; - case NEON::BI__builtin_neon_vfmsh_f16: - // NEON intrinsic puts accumulator first, unlike the LLVM fma. + mlir::Type ty = convertType(expr->getType()); + return emitNeonCallToOp<cir::FMAOp>(cgm, builder, {ty, ty, ty}, ops, + std::nullopt, ty, loc); + } + case NEON::BI__builtin_neon_vfmsh_f16: { + // NEON intrinsic puts accumulator first, unlike fma. std::rotate(ops.begin(), ops.begin() + 1, ops.end()); ops[0] = builder.createFNeg(loc, ops[0]); - return emitCallMaybeConstrainedBuiltin(builder, loc, "fma", - convertType(expr->getType()), ops); + mlir::Type ty = convertType(expr->getType()); + return emitNeonCallToOp<cir::FMAOp>(cgm, builder, {ty, ty, ty}, ops, + std::nullopt, ty, loc); + } case NEON::BI__builtin_neon_vaddd_s64: case NEON::BI__builtin_neon_vaddd_u64: return builder.createAdd(loc, ops[0], ops[1]); @@ -2906,7 +2898,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, laneSource = emitNeonSplat(builder, loc, laneSource, ops[3], ty.getSize()); llvm::SmallVector<mlir::Value> fmaOps = {multiplicand, laneSource, addend}; - return emitCallMaybeConstrainedBuiltin(builder, loc, "fma", ty, fmaOps); + return emitNeonCallToOp<cir::FMAOp>(cgm, builder, {ty, ty, ty}, fmaOps, + std::nullopt, ty, loc); } case NEON::BI__builtin_neon_vfma_laneq_v: { // v1f64 fma should be mapped to Neon scalar f64 fma. @@ -2924,8 +2917,9 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, llvm::SmallVector<mlir::Value> fmaOps = {multiplicand, laneSource, addend}; return builder.createBitcast( - emitCallMaybeConstrainedBuiltin(builder, loc, "fma", cgm.doubleTy, - fmaOps), + emitNeonCallToOp<cir::FMAOp>( + cgm, builder, {cgm.doubleTy, cgm.doubleTy, cgm.doubleTy}, fmaOps, + std::nullopt, cgm.doubleTy, loc), ty); } @@ -2939,7 +2933,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, laneSource = emitNeonSplat(builder, loc, laneSource, ops[3], ty.getSize()); llvm::SmallVector<mlir::Value> fmaOps = {laneSource, multiplicand, addend}; - return emitCallMaybeConstrainedBuiltin(builder, loc, "fma", ty, fmaOps); + return emitNeonCallToOp<cir::FMAOp>(cgm, builder, {ty, ty, ty}, fmaOps, + std::nullopt, ty, loc); } case NEON::BI__builtin_neon_vfmaq_laneq_v: { mlir::Value addend = builder.createBitcast(ops[0], ty); @@ -2948,7 +2943,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, laneSource = emitNeonSplat(builder, loc, laneSource, ops[3], ty.getSize()); llvm::SmallVector<mlir::Value> fmaOps = {laneSource, multiplicand, addend}; - return emitCallMaybeConstrainedBuiltin(builder, loc, "fma", ty, fmaOps); + return emitNeonCallToOp<cir::FMAOp>(cgm, builder, {ty, ty, ty}, fmaOps, + std::nullopt, ty, loc); } case NEON::BI__builtin_neon_vfmah_lane_f16: case NEON::BI__builtin_neon_vfmas_lane_f32: @@ -2959,8 +2955,9 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, loc, ops[2], static_cast<uint64_t>(getIntValueFromConstOp(ops[3]))); llvm::SmallVector<mlir::Value> fmaOps = {ops[1], laneSource, ops[0]}; - return emitCallMaybeConstrainedBuiltin( - builder, loc, "fma", convertType(expr->getType()), fmaOps); + mlir::Type ty = convertType(expr->getType()); + return emitNeonCallToOp<cir::FMAOp>(cgm, builder, {ty, ty, ty}, fmaOps, + std::nullopt, ty, loc); } case NEON::BI__builtin_neon_vfmad_lane_f64: case NEON::BI__builtin_neon_vfmad_laneq_f64: { @@ -2970,8 +2967,9 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, loc, ops[2], static_cast<uint64_t>(getIntValueFromConstOp(ops[3]))); llvm::SmallVector<mlir::Value> fmaOps = {ops[1], laneSource, ops[0]}; - return emitCallMaybeConstrainedBuiltin(builder, loc, "fma", cgm.doubleTy, - fmaOps); + return emitNeonCallToOp<cir::FMAOp>( + cgm, builder, {cgm.doubleTy, cgm.doubleTy, cgm.doubleTy}, fmaOps, + std::nullopt, cgm.doubleTy, loc); } case NEON::BI__builtin_neon_vmull_v: { intrName = usgn ? "aarch64.neon.umull" : "aarch64.neon.smull"; @@ -3229,13 +3227,15 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, intrName = "aarch64.neon.fminnmp"; return emitNeonCall(cgm, builder, {ty, ty}, ops, intrName, ty, loc); case NEON::BI__builtin_neon_vsqrth_f16: { - auto halfTy = builder.getFp16Ty(); - return emitCallMaybeConstrainedBuiltin(builder, loc, "sqrt", {halfTy}, ops); + mlir::Type halfTy = builder.getFp16Ty(); + return emitNeonCallToOp<cir::SqrtOp>(cgm, builder, {halfTy}, ops, + std::nullopt, halfTy, loc); } case NEON::BI__builtin_neon_vsqrt_v: case NEON::BI__builtin_neon_vsqrtq_v: assert(!cir::MissingFeatures::emitConstrainedFPCall()); - return emitNeonCall(cgm, builder, {ty}, ops, "sqrt", ty, loc); + return emitNeonCallToOp<cir::SqrtOp>(cgm, builder, {ty}, ops, std::nullopt, + ty, loc); case NEON::BI__builtin_neon_vrbit_v: case NEON::BI__builtin_neon_vrbitq_v: case NEON::BI__builtin_neon_vmaxv_f16: diff --git a/clang/test/CodeGen/AArch64/neon/fullfp16.c b/clang/test/CodeGen/AArch64/neon/fullfp16.c index 5c229ff8a1736..c17518eb813de 100644 --- a/clang/test/CodeGen/AArch64/neon/fullfp16.c +++ b/clang/test/CodeGen/AArch64/neon/fullfp16.c @@ -311,7 +311,7 @@ float16_t test_vrndxh_f16(float16_t a) { //===------------------------------------------------------===// // ALL-LABEL: test_vsqrth_f16 float16_t test_vsqrth_f16(float16_t a) { -// CIR: cir.call_llvm_intrinsic "sqrt" +// CIR: cir.sqrt // LLVM-SAME: half{{.*}} [[A:%.*]]) // LLVM: [[SQR:%.*]] = call half @llvm.sqrt.f16(half [[A]]) @@ -337,7 +337,7 @@ float16_t test_vnegh_f16(float16_t a) { //===------------------------------------------------------===// // ALL-LABEL: test_vfmah_f16 float16_t test_vfmah_f16(float16_t a, float16_t b, float16_t c) { -// CIR: cir.call_llvm_intrinsic "fma" {{.*}} : (!cir.f16, !cir.f16, !cir.f16) -> !cir.f16 +// CIR: cir.fma {{.*}} : !cir.f16 // LLVM-SAME: half{{.*}} [[A:%.*]], half{{.*}} [[B:%.*]], half{{.*}} [[C:%.*]]) // LLVM: [[FMA:%.*]] = call half @llvm.fma.f16(half [[B]], half [[C]], half [[A]]) @@ -348,7 +348,7 @@ float16_t test_vfmah_f16(float16_t a, float16_t b, float16_t c) { // ALL-LABEL: test_vfmsh_f16 float16_t test_vfmsh_f16(float16_t a, float16_t b, float16_t c) { // CIR: [[SUB:%.*]] = cir.fneg %{{.*}} : !cir.f16 -// CIR: cir.call_llvm_intrinsic "fma" [[SUB]], {{.*}} : (!cir.f16, !cir.f16, !cir.f16) -> !cir.f16 +// CIR: cir.fma [[SUB]], {{.*}} : !cir.f16 // LLVM-SAME: half{{.*}} [[A:%.*]], half{{.*}} [[B:%.*]], half{{.*}} [[C:%.*]]) // LLVM: [[SUB:%.*]] = fneg half [[B]] diff --git a/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c b/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c index e83f528586d3b..7231a1108a94f 100644 --- a/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c +++ b/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c @@ -31,7 +31,7 @@ // LLVM-LABEL: @test_vfma_f16( // CIR-LABEL: @vfma_f16( float16x4_t test_vfma_f16(float16x4_t a, float16x4_t b, float16x4_t c) { -// CIR: cir.call_llvm_intrinsic "fma" %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>) -> !cir.vector<4 x !cir.f16> +// CIR: cir.fma %{{.*}}, %{{.*}}, %{{.*}} : !cir.vector<4 x !cir.f16> // LLVM-SAME: <4 x half> {{.*}} [[A:%.*]], <4 x half> {{.*}} [[B:%.*]], <4 x half> {{.*}} [[C:%.*]]) {{.*}} { // LLVM: [[A_I:%.*]] = bitcast <4 x half> [[A]] to <4 x i16> @@ -51,7 +51,7 @@ float16x4_t test_vfma_f16(float16x4_t a, float16x4_t b, float16x4_t c) { // LLVM-LABEL: @test_vfmaq_f16( // CIR-LABEL: @vfmaq_f16( float16x8_t test_vfmaq_f16(float16x8_t a, float16x8_t b, float16x8_t c) { -// CIR: cir.call_llvm_intrinsic "fma" %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>) -> !cir.vector<8 x !cir.f16> +// CIR: cir.fma %{{.*}}, %{{.*}}, %{{.*}} : !cir.vector<8 x !cir.f16> // LLVM-SAME: <8 x half> {{.*}} [[A:%.*]], <8 x half> {{.*}} [[B:%.*]], <8 x half> {{.*}} [[C:%.*]]) {{.*}} { // LLVM: [[A_I:%.*]] = bitcast <8 x half> [[A]] to <8 x i16> @@ -116,7 +116,7 @@ float16x8_t test_vfmsq_f16(float16x8_t a, float16x8_t b, float16x8_t c) { float16x4_t test_vfma_lane_f16(float16x4_t a, float16x4_t b, float16x4_t c) { // CIR: [[LANE:%.*]] = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<4 x !cir.f16>) [#cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i] : !cir.vector<4 x !cir.f16> -// CIR: cir.call_llvm_intrinsic "fma" %{{.*}}, [[LANE]], %{{.*}} : (!cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>) -> !cir.vector<4 x !cir.f16> +// CIR: cir.fma %{{.*}}, [[LANE]], %{{.*}} : !cir.vector<4 x !cir.f16> // LLVM-SAME: <4 x half> {{.*}} [[A:%.*]], <4 x half> {{.*}} [[B:%.*]], <4 x half> {{.*}} [[C:%.*]]) {{.*}} { // LLVM: [[A_I:%.*]] = bitcast <4 x half> [[A]] to <4 x i16> @@ -138,7 +138,7 @@ float16x4_t test_vfma_lane_f16(float16x4_t a, float16x4_t b, float16x8_t test_vfmaq_lane_f16(float16x8_t a, float16x8_t b, float16x4_t c) { // CIR: [[LANE:%.*]] = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<4 x !cir.f16>) [#cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i] : !cir.vector<8 x !cir.f16> -// CIR: cir.call_llvm_intrinsic "fma" %{{.*}}, [[LANE]], %{{.*}} : (!cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>) -> !cir.vector<8 x !cir.f16> +// CIR: cir.fma %{{.*}}, [[LANE]], %{{.*}} : !cir.vector<8 x !cir.f16> // LLVM-SAME: <8 x half> {{.*}} [[A:%.*]], <8 x half> {{.*}} [[B:%.*]], <4 x half> {{.*}} [[C:%.*]]) {{.*}} { // LLVM: [[A_I:%.*]] = bitcast <8 x half> [[A]] to <8 x i16> @@ -160,7 +160,7 @@ float16x8_t test_vfmaq_lane_f16(float16x8_t a, float16x8_t b, float16x4_t test_vfma_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t c) { // CIR: [[LANE:%.*]] = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<8 x !cir.f16>) [#cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i] : !cir.vector<4 x !cir.f16> -// CIR: cir.call_llvm_intrinsic "fma" [[LANE]], %{{.*}}, %{{.*}} : (!cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>) -> !cir.vector<4 x !cir.f16> +// CIR: cir.fma [[LANE]], %{{.*}}, %{{.*}} : !cir.vector<4 x !cir.f16> // LLVM-SAME: <4 x half> {{.*}} [[A:%.*]], <4 x half> {{.*}} [[B:%.*]], <8 x half> {{.*}} [[C:%.*]]) {{.*}} { // LLVM: [[A_I:%.*]] = bitcast <4 x half> [[A]] to <4 x i16> @@ -182,7 +182,7 @@ float16x4_t test_vfma_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t test_vfmaq_laneq_f16(float16x8_t a, float16x8_t b, float16x8_t c) { // CIR: [[LANE:%.*]] = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<8 x !cir.f16>) [#cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i] : !cir.vector<8 x !cir.f16> -// CIR: cir.call_llvm_intrinsic "fma" [[LANE]], %{{.*}}, %{{.*}} : (!cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>) -> !cir.vector<8 x !cir.f16> +// CIR: cir.fma [[LANE]], %{{.*}}, %{{.*}} : !cir.vector<8 x !cir.f16> // LLVM-SAME: <8 x half> {{.*}} [[A:%.*]], <8 x half> {{.*}} [[B:%.*]], <8 x half> {{.*}} [[C:%.*]]) {{.*}} { // LLVM: [[A_I:%.*]] = bitcast <8 x half> [[A]] to <8 x i16> @@ -245,7 +245,7 @@ float16x8_t test_vfmaq_n_f16(float16x8_t a, float16x8_t b, float16_t c) { // ALL-LABEL: @test_vfmah_lane_f16( float16_t test_vfmah_lane_f16(float16_t a, float16_t b, float16x4_t c) { // CIR: [[LANE:%.*]] = cir.vec.extract %{{.*}}[%{{.*}} : !u64i] : !cir.vector<4 x !cir.f16> -// CIR: cir.call_llvm_intrinsic "fma" %{{.*}}, [[LANE]], %{{.*}} : (!cir.f16, !cir.f16, !cir.f16) -> !cir.f16 +// CIR: cir.fma %{{.*}}, [[LANE]], %{{.*}} : !cir.f16 // LLVM-SAME: half {{.*}} [[A:%.*]], half {{.*}} [[B:%.*]], <4 x half> {{.*}} [[C:%.*]]) {{.*}} { // LLVM: [[LANE:%.*]] = extractelement <4 x half> [[C]], i{{32|64}} 3 @@ -257,7 +257,7 @@ float16_t test_vfmah_lane_f16(float16_t a, float16_t b, float16x4_t c) { // ALL-LABEL: @test_vfmah_laneq_f16( float16_t test_vfmah_laneq_f16(float16_t a, float16_t b, float16x8_t c) { // CIR: [[LANE:%.*]] = cir.vec.extract %{{.*}}[%{{.*}} : !u64i] : !cir.vector<8 x !cir.f16> -// CIR: cir.call_llvm_intrinsic "fma" %{{.*}}, [[LANE]], %{{.*}} : (!cir.f16, !cir.f16, !cir.f16) -> !cir.f16 +// CIR: cir.fma %{{.*}}, [[LANE]], %{{.*}} : !cir.f16 // LLVM-SAME: half {{.*}} [[A:%.*]], half {{.*}} [[B:%.*]], <8 x half> {{.*}} [[C:%.*]]) {{.*}} { // LLVM: [[LANE:%.*]] = extractelement <8 x half> [[C]], i{{32|64}} 7 @@ -275,7 +275,7 @@ float16x4_t test_vfms_lane_f16(float16x4_t a, float16x4_t b, // CIR: [[NEG_BYTES:%.*]] = cir.load align(8) [[NEG_PTR]] : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> // CIR: [[NEG_CAST:%.*]] = cir.cast bitcast [[NEG_BYTES]] : !cir.vector<8 x !s8i> -> !cir.vector<4 x !cir.f16> // CIR: [[LANE:%.*]] = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<4 x !cir.f16>) [#cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i] : !cir.vector<4 x !cir.f16> -// CIR: cir.call_llvm_intrinsic "fma" [[NEG_CAST]], [[LANE]], %{{.*}} : (!cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>) -> !cir.vector<4 x !cir.f16> +// CIR: cir.fma [[NEG_CAST]], [[LANE]], %{{.*}} : !cir.vector<4 x !cir.f16> // LLVM-SAME: <4 x half> {{.*}} [[A:%.*]], <4 x half> {{.*}} [[B:%.*]], <4 x half> {{.*}} [[C:%.*]]) {{.*}} { // LLVM: [[A_I:%.*]] = bitcast <4 x half> [[A]] to <4 x i16> @@ -303,7 +303,7 @@ float16x8_t test_vfmsq_lane_f16(float16x8_t a, float16x8_t b, // CIR: [[NEG_BYTES:%.*]] = cir.load align(16) [[NEG_PTR]] : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> // CIR: [[NEG_CAST:%.*]] = cir.cast bitcast [[NEG_BYTES]] : !cir.vector<16 x !s8i> -> !cir.vector<8 x !cir.f16> // CIR: [[LANE:%.*]] = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<4 x !cir.f16>) [#cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i] : !cir.vector<8 x !cir.f16> -// CIR: cir.call_llvm_intrinsic "fma" [[NEG_CAST]], [[LANE]], %{{.*}} : (!cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>) -> !cir.vector<8 x !cir.f16> +// CIR: cir.fma [[NEG_CAST]], [[LANE]], %{{.*}} : !cir.vector<8 x !cir.f16> // LLVM-SAME: <8 x half> {{.*}} [[A:%.*]], <8 x half> {{.*}} [[B:%.*]], <4 x half> {{.*}} [[C:%.*]]) {{.*}} { // LLVM: [[A_I:%.*]] = bitcast <8 x half> [[A]] to <8 x i16> @@ -331,7 +331,7 @@ float16x4_t test_vfms_laneq_f16(float16x4_t a, float16x4_t b, // CIR: [[NEG_BYTES:%.*]] = cir.load align(8) [[NEG_PTR]] : !cir.ptr<!cir.vector<8 x !s8i>>, !cir.vector<8 x !s8i> // CIR: [[NEG_CAST:%.*]] = cir.cast bitcast [[NEG_BYTES]] : !cir.vector<8 x !s8i> -> !cir.vector<4 x !cir.f16> // CIR: [[LANE:%.*]] = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<8 x !cir.f16>) [#cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i] : !cir.vector<4 x !cir.f16> -// CIR: cir.call_llvm_intrinsic "fma" [[LANE]], [[NEG_CAST]], %{{.*}} : (!cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>) -> !cir.vector<4 x !cir.f16> +// CIR: cir.fma [[LANE]], [[NEG_CAST]], %{{.*}} : !cir.vector<4 x !cir.f16> // LLVM-SAME: <4 x half> {{.*}} [[A:%.*]], <4 x half> {{.*}} [[B:%.*]], <8 x half> {{.*}} [[C:%.*]]) {{.*}} { // LLVM: [[A_I:%.*]] = bitcast <4 x half> [[A]] to <4 x i16> @@ -359,7 +359,7 @@ float16x8_t test_vfmsq_laneq_f16(float16x8_t a, float16x8_t b, // CIR: [[NEG_BYTES:%.*]] = cir.load align(16) [[NEG_PTR]] : !cir.ptr<!cir.vector<16 x !s8i>>, !cir.vector<16 x !s8i> // CIR: [[NEG_CAST:%.*]] = cir.cast bitcast [[NEG_BYTES]] : !cir.vector<16 x !s8i> -> !cir.vector<8 x !cir.f16> // CIR: [[LANE:%.*]] = cir.vec.shuffle(%{{.*}}, %{{.*}} : !cir.vector<8 x !cir.f16>) [#cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i] : !cir.vector<8 x !cir.f16> -// CIR: cir.call_llvm_intrinsic "fma" [[LANE]], [[NEG_CAST]], %{{.*}} : (!cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>) -> !cir.vector<8 x !cir.f16> +// CIR: cir.fma [[LANE]], [[NEG_CA... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/213800 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
