https://github.com/kieroxide updated https://github.com/llvm/llvm-project/pull/212459
>From 556b0e0b5eb9e991917f3c8bfc924f51cf32ef8b Mon Sep 17 00:00:00 2001 From: Kieran Bailey <[email protected]> Date: Fri, 31 Jul 2026 11:52:01 +0000 Subject: [PATCH 1/3] [Clang] Fix immediate range check for NEON widening left-shifts Change the immediate check for c intrinsic vshll_n from 0..((eltsize*2) - 1) to 0..eltsize. The ACLE specifies this intrinsic to have a valid immediate range size of 0..eltsize. Update the range check and testing to match the specified behaviour --- .../include/clang/Basic/arm_immcheck_incl.td | 43 ++++++++++--------- clang/include/clang/Basic/arm_neon.td | 11 +++-- clang/lib/Sema/SemaARM.cpp | 4 ++ .../vector-shift-left.c | 43 +++++++++++-------- 4 files changed, 56 insertions(+), 45 deletions(-) diff --git a/clang/include/clang/Basic/arm_immcheck_incl.td b/clang/include/clang/Basic/arm_immcheck_incl.td index 6892b8299771b..52f3f57a9b37d 100644 --- a/clang/include/clang/Basic/arm_immcheck_incl.td +++ b/clang/include/clang/Basic/arm_immcheck_incl.td @@ -11,27 +11,28 @@ def ImmCheckExtract : ImmCheckType<2>; // 0..(2048/sizeinbits(elt) def ImmCheckShiftRight : ImmCheckType<3>; // 1..sizeinbits(elt) def ImmCheckShiftRightNarrow : ImmCheckType<4>; // 1..sizeinbits(elt)/2 def ImmCheckShiftLeft : ImmCheckType<5>; // 0..(sizeinbits(elt) - 1) -def ImmCheck0_7 : ImmCheckType<6>; // 0..7 -def ImmCheckLaneIndex : ImmCheckType<7>; // 0..(container_size/(sizeinbits(elt)) - 1) -def ImmCheckCvt : ImmCheckType<8>; // 1..sizeinbits(elt) (same as ShiftRight) -def ImmCheckLaneIndexCompRotate : ImmCheckType<9>; // 0..(container_size/(2*sizeinbits(elt)) - 1) -def ImmCheckLaneIndexDot : ImmCheckType<10>; // 0..(container_size/(4*sizeinbits(elt)) - 1) -def ImmCheckComplexRot90_270 : ImmCheckType<11>; // [90,270] -def ImmCheckComplexRotAll90 : ImmCheckType<12>; // [0, 90, 180,270] -def ImmCheck0_13 : ImmCheckType<13>; // 0..13 -def ImmCheck0_1 : ImmCheckType<14>; // 0..1 -def ImmCheck0_2 : ImmCheckType<15>; // 0..2 -def ImmCheck0_3 : ImmCheckType<16>; // 0..3 -def ImmCheck0_0 : ImmCheckType<17>; // 0..0 -def ImmCheck0_15 : ImmCheckType<18>; // 0..15 -def ImmCheck0_255 : ImmCheckType<19>; // 0..255 -def ImmCheck2_4_Mul2 : ImmCheckType<20>; // 2, 4 -def ImmCheck1_1 : ImmCheckType<21>; // 1..1 -def ImmCheck1_3 : ImmCheckType<22>; // 1..3 -def ImmCheck1_7 : ImmCheckType<23>; // 1..7 -def ImmCheck1_32 : ImmCheckType<24>; // 1..32 -def ImmCheck1_64 : ImmCheckType<25>; // 1..64 -def ImmCheck0_63 : ImmCheckType<26>; // 0..63 +def ImmCheckShiftLeftLong : ImmCheckType<6>; // 0..(sizeinbits(elt)/2) +def ImmCheck0_7 : ImmCheckType<7>; // 0..7 +def ImmCheckLaneIndex : ImmCheckType<8>; // 0..(container_size/(sizeinbits(elt)) - 1) +def ImmCheckCvt : ImmCheckType<9>; // 1..sizeinbits(elt) (same as ShiftRight) +def ImmCheckLaneIndexCompRotate : ImmCheckType<10>; // 0..(container_size/(2*sizeinbits(elt)) - 1) +def ImmCheckLaneIndexDot : ImmCheckType<11>; // 0..(container_size/(4*sizeinbits(elt)) - 1) +def ImmCheckComplexRot90_270 : ImmCheckType<12>; // [90,270] +def ImmCheckComplexRotAll90 : ImmCheckType<13>; // [0, 90, 180,270] +def ImmCheck0_13 : ImmCheckType<14>; // 0..13 +def ImmCheck0_1 : ImmCheckType<15>; // 0..1 +def ImmCheck0_2 : ImmCheckType<16>; // 0..2 +def ImmCheck0_3 : ImmCheckType<17>; // 0..3 +def ImmCheck0_0 : ImmCheckType<18>; // 0..0 +def ImmCheck0_15 : ImmCheckType<19>; // 0..15 +def ImmCheck0_255 : ImmCheckType<20>; // 0..255 +def ImmCheck2_4_Mul2 : ImmCheckType<21>; // 2, 4 +def ImmCheck1_1 : ImmCheckType<22>; // 1..1 +def ImmCheck1_3 : ImmCheckType<23>; // 1..3 +def ImmCheck1_7 : ImmCheckType<24>; // 1..7 +def ImmCheck1_32 : ImmCheckType<25>; // 1..32 +def ImmCheck1_64 : ImmCheckType<26>; // 1..64 +def ImmCheck0_63 : ImmCheckType<27>; // 0..63 class ImmCheck<int immArgIdx, ImmCheckType kind, int typeArgIdx = -1> { // Parameter index of immediate argument to be verified diff --git a/clang/include/clang/Basic/arm_neon.td b/clang/include/clang/Basic/arm_neon.td index 041a420875290..b74d3805e950a 100644 --- a/clang/include/clang/Basic/arm_neon.td +++ b/clang/include/clang/Basic/arm_neon.td @@ -432,13 +432,12 @@ def VRSHRN_N : IInst<"vrshrn_n", "<QI", "silUsUiUl", def VQRSHRN_N : SInst<"vqrshrn_n", "<QI", "silUsUiUl", [ImmCheck<1, ImmCheckShiftRight>]>; -// Widening left-shifts should have a range of 0..(sizeinbits(arg)-1). -// This polymorphic builtin is supplied the wider return type as it's overloaded -// base type, so the range here is actually 0..(sizeinbits(arg)*2). -// This cannot be rectified currently due to a use of vshll_n_s16 with an -// out-of-bounds immediate in the defintiion of vcvt_f32_bf16. +// Widening left-shifts should have an immediate range of 0..sizeinbits(arg). +// However, as the overloaded type code that is supplied to a polymorphic builtin +// is that of the return type (twice as wide as the argument in this case). +// ImmCheckShiftLeftLong produces the correct behavior here. def VSHLL_N : SInst<"vshll_n", "(>Q).I", "csiUcUsUi", - [ImmCheck<1, ImmCheckShiftLeft>]>; + [ImmCheck<1, ImmCheckShiftLeftLong>]>; //////////////////////////////////////////////////////////////////////////////// // E.3.13 Shifts with insert diff --git a/clang/lib/Sema/SemaARM.cpp b/clang/lib/Sema/SemaARM.cpp index 5e7504fab416d..f549016bb17ae 100644 --- a/clang/lib/Sema/SemaARM.cpp +++ b/clang/lib/Sema/SemaARM.cpp @@ -452,6 +452,10 @@ bool SemaARM::CheckImmediateArg(CallExpr *TheCall, unsigned CheckTy, if (SemaRef.BuiltinConstantArgRange(TheCall, ArgIdx, 0, EltBitWidth - 1)) return true; break; + case ImmCheckType::ImmCheckShiftLeftLong: + if (SemaRef.BuiltinConstantArgRange(TheCall, ArgIdx, 0, (EltBitWidth / 2))) + return true; + break; case ImmCheckType::ImmCheckLaneIndex: if (SemaRef.BuiltinConstantArgRange(TheCall, ArgIdx, 0, (ContainerBitWidth / EltBitWidth) - 1)) diff --git a/clang/test/Sema/aarch64-neon-immediate-ranges/vector-shift-left.c b/clang/test/Sema/aarch64-neon-immediate-ranges/vector-shift-left.c index 1def72fc843d9..6bc259b098201 100644 --- a/clang/test/Sema/aarch64-neon-immediate-ranges/vector-shift-left.c +++ b/clang/test/Sema/aarch64-neon-immediate-ranges/vector-shift-left.c @@ -1,13 +1,9 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon -ffreestanding -fsyntax-only -verify %s #include <arm_neon.h> // REQUIRES: aarch64-registered-target -// Widening left-shifts should have a range of 0..(sizeinbits(arg)-1), this range has had -// to be weakened to 0..((sizeinbits(arg)*2)-1) due to a use of vshll_n_s16 with an -// out-of-bounds immediate in the defintiion of vcvt_f32_bf16. As a result, the upper bounds -// of widening left-shift intrinsics are not currently tested here. - void test_vector_shift_left_s8(int8x8_t arg_i8x8, int8x16_t arg_i8x16) { vshl_n_s8(arg_i8x8, 0); vshl_n_s8(arg_i8x8, 7); @@ -328,63 +324,74 @@ void test_vector_saturating_shift_left_u64(uint64x1_t arg_u64x1, uint64_t arg_u6 void test_vector_shift_left_and_widen_s8(int8x8_t arg_i8x8, int8x16_t arg_i8x16) { vshll_n_s8(arg_i8x8, 0); - vshll_n_s8(arg_i8x8, 7); + vshll_n_s8(arg_i8x8, 8); vshll_n_s8(arg_i8x8, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}} - + vshll_n_s8(arg_i8x8, 9); // expected-error-re {{argument value {{.*}} is outside the valid range}} vshll_high_n_s8(arg_i8x16, 0); - vshll_high_n_s8(arg_i8x16, 7); + vshll_high_n_s8(arg_i8x16, 8); vshll_high_n_s8(arg_i8x16, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}} + vshll_high_n_s8(arg_i8x16, 9); // expected-error-re {{argument value {{.*}} is outside the valid range}} } void test_vector_shift_left_and_widen_s16(int16x4_t arg_i16x4, int16x8_t arg_i16x8) { vshll_n_s16(arg_i16x4, 0); - vshll_n_s16(arg_i16x4, 15); + vshll_n_s16(arg_i16x4, 16); vshll_n_s16(arg_i16x4, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}} + vshll_n_s16(arg_i16x4, 17); // expected-error-re {{argument value {{.*}} is outside the valid range}} vshll_high_n_s16(arg_i16x8, 0); - vshll_high_n_s16(arg_i16x8, 15); + vshll_high_n_s16(arg_i16x8, 16); vshll_high_n_s16(arg_i16x8, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}} + vshll_high_n_s16(arg_i16x8, 17); // expected-error-re {{argument value {{.*}} is outside the valid range}} } void test_vector_shift_left_and_widen_s32(int32x2_t arg_i32x2, int32x4_t arg_i32x4) { vshll_n_s32(arg_i32x2, 0); - vshll_n_s32(arg_i32x2, 31); + vshll_n_s32(arg_i32x2, 32); vshll_n_s32(arg_i32x2, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}} + vshll_n_s32(arg_i32x2, 33); // expected-error-re {{argument value {{.*}} is outside the valid range}} vshll_high_n_s32(arg_i32x4, 0); - vshll_high_n_s32(arg_i32x4, 31); + vshll_high_n_s32(arg_i32x4, 32); vshll_high_n_s32(arg_i32x4, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}} + vshll_high_n_s32(arg_i32x4, 33); // expected-error-re {{argument value {{.*}} is outside the valid range}} } void test_vector_shift_left_and_widen_u8(uint8x8_t arg_u8x8, uint8x16_t arg_u8x16) { vshll_n_u8(arg_u8x8, 0); - vshll_n_u8(arg_u8x8, 7); + vshll_n_u8(arg_u8x8, 8); vshll_n_u8(arg_u8x8, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}} + vshll_n_u8(arg_u8x8, 9); // expected-error-re {{argument value {{.*}} is outside the valid range}} vshll_high_n_u8(arg_u8x16, 0); - vshll_high_n_u8(arg_u8x16, 7); + vshll_high_n_u8(arg_u8x16, 8); vshll_high_n_u8(arg_u8x16, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}} + vshll_high_n_u8(arg_u8x16, 9); // expected-error-re {{argument value {{.*}} is outside the valid range}} } void test_vector_shift_left_and_widen_u16(uint16x4_t arg_u16x4, uint16x8_t arg_u16x8) { vshll_n_u16(arg_u16x4, 0); - vshll_n_u16(arg_u16x4, 15); + vshll_n_u16(arg_u16x4, 16); vshll_n_u16(arg_u16x4, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}} + vshll_n_u16(arg_u16x4, 17); // expected-error-re {{argument value {{.*}} is outside the valid range}} vshll_high_n_u16(arg_u16x8, 0); - vshll_high_n_u16(arg_u16x8, 15); + vshll_high_n_u16(arg_u16x8, 16); vshll_high_n_u16(arg_u16x8, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}} + vshll_high_n_u16(arg_u16x8, 17); // expected-error-re {{argument value {{.*}} is outside the valid range}} } void test_vector_shift_left_and_widen_u32(uint32x2_t arg_u32x2, uint32x4_t arg_u32x4) { vshll_n_u32(arg_u32x2, 0); - vshll_n_u32(arg_u32x2, 31); + vshll_n_u32(arg_u32x2, 32); vshll_n_u32(arg_u32x2, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}} + vshll_n_u32(arg_u32x2, 33); // expected-error-re {{argument value {{.*}} is outside the valid range}} vshll_high_n_u32(arg_u32x4, 0); - vshll_high_n_u32(arg_u32x4, 31); + vshll_high_n_u32(arg_u32x4, 32); vshll_high_n_u32(arg_u32x4, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}} + vshll_high_n_u32(arg_u32x4, 33); // expected-error-re {{argument value {{.*}} is outside the valid range}} } void test_vector_shift_left_and_insert_s8(int8x8_t arg_i8x8, int8x16_t arg_i8x16) { >From c97b98e6f844f181671d573054f80e9d07180613 Mon Sep 17 00:00:00 2001 From: Kieran Bailey <[email protected]> Date: Mon, 3 Aug 2026 09:44:17 +0000 Subject: [PATCH 2/3] Add tests to existing test file to test zext/sext + shl with an immediate equal to eltsize --- .../CodeGen/AArch64/neon-shift-left-long.ll | 200 ++++++++++++++++++ 1 file changed, 200 insertions(+) diff --git a/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll b/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll index a8c55b476b810..f308c6672c669 100644 --- a/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll +++ b/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll @@ -12,6 +12,22 @@ define <8 x i16> @test_sshll_v8i8(<8 x i8> %a) { ret <8 x i16> %tmp } +define <8 x i16> @test_sshll_v8i8_eltsize(<8 x i8> %a) { +; CHECK-SD-LABEL: test_sshll_v8i8_eltsize: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: shll v0.8h, v0.8b, #8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_sshll_v8i8_eltsize: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0 +; CHECK-GI-NEXT: shl v0.8h, v0.8h, #8 +; CHECK-GI-NEXT: ret + %1 = sext <8 x i8> %a to <8 x i16> + %tmp = shl <8 x i16> %1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> + ret <8 x i16> %tmp +} + define <8 x i16> @test_sshll_v8i8_big(<8 x i8> %a) { ; CHECK-SD-LABEL: test_sshll_v8i8_big: ; CHECK-SD: // %bb.0: @@ -39,6 +55,22 @@ define <4 x i32> @test_sshll_v4i16(<4 x i16> %a) { ret <4 x i32> %tmp } +define <4 x i32> @test_sshll_v4i16_eltsize(<4 x i16> %a) { +; CHECK-SD-LABEL: test_sshll_v4i16_eltsize: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_sshll_v4i16_eltsize: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #0 +; CHECK-GI-NEXT: shl v0.4s, v0.4s, #16 +; CHECK-GI-NEXT: ret + %1 = sext <4 x i16> %a to <4 x i32> + %tmp = shl <4 x i32> %1, <i32 16, i32 16, i32 16, i32 16> + ret <4 x i32> %tmp +} + define <4 x i32> @test_sshll_v4i16_big(<4 x i16> %a) { ; CHECK-SD-LABEL: test_sshll_v4i16_big: ; CHECK-SD: // %bb.0: @@ -66,6 +98,23 @@ define <2 x i64> @test_sshll_v2i32(<2 x i32> %a) { ret <2 x i64> %tmp } +define <2 x i64> @test_sshll_v2i32_eltsize(<2 x i32> %a) { +; CHECK-SD-LABEL: test_sshll_v2i32_eltsize: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: shll v0.2d, v0.2s, #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_sshll_v2i32_eltsize: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #0 +; CHECK-GI-NEXT: shl v0.2d, v0.2d, #32 +; CHECK-GI-NEXT: ret + %1 = sext <2 x i32> %a to <2 x i64> + %tmp = shl <2 x i64> %1, <i64 32, i64 32> + ret <2 x i64> %tmp +} + + define <2 x i64> @test_sshll_v2i32_big(<2 x i32> %a) { ; CHECK-SD-LABEL: test_sshll_v2i32_big: ; CHECK-SD: // %bb.0: @@ -93,6 +142,22 @@ define <8 x i16> @test_ushll_v8i8(<8 x i8> %a) { ret <8 x i16> %tmp } +define <8 x i16> @test_ushll_v8i8_eltsize(<8 x i8> %a) { +; CHECK-SD-LABEL: test_ushll_v8i8_eltsize: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: shll v0.8h, v0.8b, #8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_ushll_v8i8_eltsize: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0 +; CHECK-GI-NEXT: shl v0.8h, v0.8h, #8 +; CHECK-GI-NEXT: ret + %1 = zext <8 x i8> %a to <8 x i16> + %tmp = shl <8 x i16> %1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> + ret <8 x i16> %tmp +} + define <8 x i16> @test_ushll_v8i8_big(<8 x i8> %a) { ; CHECK-LABEL: test_ushll_v8i8_big: ; CHECK: // %bb.0: @@ -114,6 +179,22 @@ define <4 x i32> @test_ushll_v4i16(<4 x i16> %a) { ret <4 x i32> %tmp } +define <4 x i32> @test_ushll_v4i16_eltsize(<4 x i16> %a) { +; CHECK-SD-LABEL: test_ushll_v4i16_eltsize: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_ushll_v4i16_eltsize: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0 +; CHECK-GI-NEXT: shl v0.4s, v0.4s, #16 +; CHECK-GI-NEXT: ret + %1 = zext <4 x i16> %a to <4 x i32> + %tmp = shl <4 x i32> %1, <i32 16, i32 16, i32 16, i32 16> + ret <4 x i32> %tmp +} + define <4 x i32> @test_ushll_v4i16_big(<4 x i16> %a) { ; CHECK-LABEL: test_ushll_v4i16_big: ; CHECK: // %bb.0: @@ -135,6 +216,22 @@ define <2 x i64> @test_ushll_v2i32(<2 x i32> %a) { ret <2 x i64> %tmp } +define <2 x i64> @test_ushll_v2i32_eltsize(<2 x i32> %a) { +; CHECK-SD-LABEL: test_ushll_v2i32_eltsize: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: shll v0.2d, v0.2s, #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_ushll_v2i32_eltsize: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0 +; CHECK-GI-NEXT: shl v0.2d, v0.2d, #32 +; CHECK-GI-NEXT: ret + %1 = zext <2 x i32> %a to <2 x i64> + %tmp = shl <2 x i64> %1, <i64 32, i64 32> + ret <2 x i64> %tmp +} + define <2 x i64> @test_ushll_v2i32_big(<2 x i32> %a) { ; CHECK-LABEL: test_ushll_v2i32_big: ; CHECK: // %bb.0: @@ -163,6 +260,23 @@ define <8 x i16> @test_sshll2_v16i8(<16 x i8> %a) { ret <8 x i16> %tmp } +define <8 x i16> @test_sshll2_v16i8_eltsize(<16 x i8> %a) { +; CHECK-SD-LABEL: test_sshll2_v16i8_eltsize: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: shll2 v0.8h, v0.16b, #8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_sshll2_v16i8_eltsize: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: sshll2 v0.8h, v0.16b, #0 +; CHECK-GI-NEXT: shl v0.8h, v0.8h, #8 +; CHECK-GI-NEXT: ret + %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %2 = sext <8 x i8> %1 to <8 x i16> + %tmp = shl <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> + ret <8 x i16> %tmp +} + define <8 x i16> @test_sshll2_v16i8_big(<16 x i8> %a) { ; CHECK-SD-LABEL: test_sshll2_v16i8_big: ; CHECK-SD: // %bb.0: @@ -198,6 +312,23 @@ define <4 x i32> @test_sshll2_v8i16(<8 x i16> %a) { ret <4 x i32> %tmp } +define <4 x i32> @test_sshll2_v8i16_eltsize(<8 x i16> %a) { +; CHECK-SD-LABEL: test_sshll2_v8i16_eltsize: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: shll2 v0.4s, v0.8h, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_sshll2_v8i16_eltsize: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0 +; CHECK-GI-NEXT: shl v0.4s, v0.4s, #16 +; CHECK-GI-NEXT: ret + %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> + %2 = sext <4 x i16> %1 to <4 x i32> + %tmp = shl <4 x i32> %2, <i32 16, i32 16, i32 16, i32 16> + ret <4 x i32> %tmp +} + define <4 x i32> @test_sshll2_v8i16_big(<8 x i16> %a) { ; CHECK-SD-LABEL: test_sshll2_v8i16_big: ; CHECK-SD: // %bb.0: @@ -233,6 +364,23 @@ define <2 x i64> @test_sshll2_v4i32(<4 x i32> %a) { ret <2 x i64> %tmp } +define <2 x i64> @test_sshll2_v4i32_eltsize(<4 x i32> %a) { +; CHECK-SD-LABEL: test_sshll2_v4i32_eltsize: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: shll2 v0.2d, v0.4s, #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_sshll2_v4i32_eltsize: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: sshll2 v0.2d, v0.4s, #0 +; CHECK-GI-NEXT: shl v0.2d, v0.2d, #32 +; CHECK-GI-NEXT: ret + %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3> + %2 = sext <2 x i32> %1 to <2 x i64> + %tmp = shl <2 x i64> %2, <i64 32, i64 32> + ret <2 x i64> %tmp +} + define <2 x i64> @test_sshll2_v4i32_big(<4 x i32> %a) { ; CHECK-SD-LABEL: test_sshll2_v4i32_big: ; CHECK-SD: // %bb.0: @@ -268,6 +416,24 @@ define <8 x i16> @test_ushll2_v16i8(<16 x i8> %a) { ret <8 x i16> %tmp } +define <8 x i16> @test_ushll2_v16i8_eltsize(<16 x i8> %a) { +; CHECK-SD-LABEL: test_ushll2_v16i8_eltsize: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: shll2 v0.8h, v0.16b, #8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_ushll2_v16i8_eltsize: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0 +; CHECK-GI-NEXT: shl v0.8h, v0.8h, #8 +; CHECK-GI-NEXT: ret + %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %2 = zext <8 x i8> %1 to <8 x i16> + %tmp = shl <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> + ret <8 x i16> %tmp +} + + define <8 x i16> @test_ushll2_v16i8_big(<16 x i8> %a) { ; CHECK-LABEL: test_ushll2_v16i8_big: ; CHECK: // %bb.0: @@ -297,6 +463,23 @@ define <4 x i32> @test_ushll2_v8i16(<8 x i16> %a) { ret <4 x i32> %tmp } +define <4 x i32> @test_ushll2_v8i16_eltsize(<8 x i16> %a) { +; CHECK-SD-LABEL: test_ushll2_v8i16_eltsize: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: shll2 v0.4s, v0.8h, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_ushll2_v8i16_eltsize: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0 +; CHECK-GI-NEXT: shl v0.4s, v0.4s, #16 +; CHECK-GI-NEXT: ret + %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> + %2 = zext <4 x i16> %1 to <4 x i32> + %tmp = shl <4 x i32> %2, <i32 16, i32 16, i32 16, i32 16> + ret <4 x i32> %tmp +} + define <4 x i32> @test_ushll2_v8i16_big(<8 x i16> %a) { ; CHECK-LABEL: test_ushll2_v8i16_big: ; CHECK: // %bb.0: @@ -326,6 +509,23 @@ define <2 x i64> @test_ushll2_v4i32(<4 x i32> %a) { ret <2 x i64> %tmp } +define <2 x i64> @test_ushll2_v4i32_eltsize(<4 x i32> %a) { +; CHECK-SD-LABEL: test_ushll2_v4i32_eltsize: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: shll2 v0.2d, v0.4s, #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_ushll2_v4i32_eltsize: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: ushll2 v0.2d, v0.4s, #0 +; CHECK-GI-NEXT: shl v0.2d, v0.2d, #32 +; CHECK-GI-NEXT: ret + %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3> + %2 = zext <2 x i32> %1 to <2 x i64> + %tmp = shl <2 x i64> %2, <i64 32, i64 32> + ret <2 x i64> %tmp +} + define <2 x i64> @test_ushll2_v4i32_big(<4 x i32> %a) { ; CHECK-LABEL: test_ushll2_v4i32_big: ; CHECK: // %bb.0: >From 93f28e6672d18e4f49894b2d789e548f32a2cb98 Mon Sep 17 00:00:00 2001 From: Kieran Bailey <[email protected]> Date: Tue, 4 Aug 2026 08:36:16 +0000 Subject: [PATCH 3/3] Add tests to existing test file to test zext/sext + shl with an immediate equal to eltsize undef was changed to poision aswell to stop clang-format failing. --- .../CodeGen/AArch64/neon-shift-left-long.ll | 49 +++++++++---------- 1 file changed, 24 insertions(+), 25 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll b/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll index f308c6672c669..88e49950d0114 100644 --- a/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll +++ b/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll @@ -114,7 +114,6 @@ define <2 x i64> @test_sshll_v2i32_eltsize(<2 x i32> %a) { ret <2 x i64> %tmp } - define <2 x i64> @test_sshll_v2i32_big(<2 x i32> %a) { ; CHECK-SD-LABEL: test_sshll_v2i32_big: ; CHECK-SD: // %bb.0: @@ -254,7 +253,7 @@ define <8 x i16> @test_sshll2_v16i8(<16 x i8> %a) { ; CHECK-GI-NEXT: mov d0, v0.d[1] ; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #3 ; CHECK-GI-NEXT: ret - %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %2 = sext <8 x i8> %1 to <8 x i16> %tmp = shl <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> ret <8 x i16> %tmp @@ -271,7 +270,7 @@ define <8 x i16> @test_sshll2_v16i8_eltsize(<16 x i8> %a) { ; CHECK-GI-NEXT: sshll2 v0.8h, v0.16b, #0 ; CHECK-GI-NEXT: shl v0.8h, v0.8h, #8 ; CHECK-GI-NEXT: ret - %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %2 = sext <8 x i8> %1 to <8 x i16> %tmp = shl <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> ret <8 x i16> %tmp @@ -289,7 +288,7 @@ define <8 x i16> @test_sshll2_v16i8_big(<16 x i8> %a) { ; CHECK-GI-NEXT: sshll2 v0.8h, v0.16b, #0 ; CHECK-GI-NEXT: shl v0.8h, v0.8h, #9 ; CHECK-GI-NEXT: ret - %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %2 = sext <8 x i8> %1 to <8 x i16> %tmp = shl <8 x i16> %2, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9> ret <8 x i16> %tmp @@ -306,7 +305,7 @@ define <4 x i32> @test_sshll2_v8i16(<8 x i16> %a) { ; CHECK-GI-NEXT: mov d0, v0.d[1] ; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #9 ; CHECK-GI-NEXT: ret - %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> + %1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %2 = sext <4 x i16> %1 to <4 x i32> %tmp = shl <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9> ret <4 x i32> %tmp @@ -323,7 +322,7 @@ define <4 x i32> @test_sshll2_v8i16_eltsize(<8 x i16> %a) { ; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0 ; CHECK-GI-NEXT: shl v0.4s, v0.4s, #16 ; CHECK-GI-NEXT: ret - %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> + %1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %2 = sext <4 x i16> %1 to <4 x i32> %tmp = shl <4 x i32> %2, <i32 16, i32 16, i32 16, i32 16> ret <4 x i32> %tmp @@ -341,7 +340,7 @@ define <4 x i32> @test_sshll2_v8i16_big(<8 x i16> %a) { ; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0 ; CHECK-GI-NEXT: shl v0.4s, v0.4s, #19 ; CHECK-GI-NEXT: ret - %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> + %1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %2 = sext <4 x i16> %1 to <4 x i32> %tmp = shl <4 x i32> %2, <i32 19, i32 19, i32 19, i32 19> ret <4 x i32> %tmp @@ -358,7 +357,7 @@ define <2 x i64> @test_sshll2_v4i32(<4 x i32> %a) { ; CHECK-GI-NEXT: mov d0, v0.d[1] ; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #19 ; CHECK-GI-NEXT: ret - %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3> + %1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3> %2 = sext <2 x i32> %1 to <2 x i64> %tmp = shl <2 x i64> %2, <i64 19, i64 19> ret <2 x i64> %tmp @@ -375,7 +374,7 @@ define <2 x i64> @test_sshll2_v4i32_eltsize(<4 x i32> %a) { ; CHECK-GI-NEXT: sshll2 v0.2d, v0.4s, #0 ; CHECK-GI-NEXT: shl v0.2d, v0.2d, #32 ; CHECK-GI-NEXT: ret - %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3> + %1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3> %2 = sext <2 x i32> %1 to <2 x i64> %tmp = shl <2 x i64> %2, <i64 32, i64 32> ret <2 x i64> %tmp @@ -393,7 +392,7 @@ define <2 x i64> @test_sshll2_v4i32_big(<4 x i32> %a) { ; CHECK-GI-NEXT: sshll2 v0.2d, v0.4s, #0 ; CHECK-GI-NEXT: shl v0.2d, v0.2d, #36 ; CHECK-GI-NEXT: ret - %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3> + %1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3> %2 = sext <2 x i32> %1 to <2 x i64> %tmp = shl <2 x i64> %2, <i64 36, i64 36> ret <2 x i64> %tmp @@ -410,7 +409,7 @@ define <8 x i16> @test_ushll2_v16i8(<16 x i8> %a) { ; CHECK-GI-NEXT: mov d0, v0.d[1] ; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #3 ; CHECK-GI-NEXT: ret - %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %2 = zext <8 x i8> %1 to <8 x i16> %tmp = shl <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> ret <8 x i16> %tmp @@ -427,7 +426,7 @@ define <8 x i16> @test_ushll2_v16i8_eltsize(<16 x i8> %a) { ; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0 ; CHECK-GI-NEXT: shl v0.8h, v0.8h, #8 ; CHECK-GI-NEXT: ret - %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %2 = zext <8 x i8> %1 to <8 x i16> %tmp = shl <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> ret <8 x i16> %tmp @@ -440,7 +439,7 @@ define <8 x i16> @test_ushll2_v16i8_big(<16 x i8> %a) { ; CHECK-NEXT: ushll2 v0.8h, v0.16b, #0 ; CHECK-NEXT: shl v0.8h, v0.8h, #9 ; CHECK-NEXT: ret - %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %2 = zext <8 x i8> %1 to <8 x i16> %tmp = shl <8 x i16> %2, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9> ret <8 x i16> %tmp @@ -457,7 +456,7 @@ define <4 x i32> @test_ushll2_v8i16(<8 x i16> %a) { ; CHECK-GI-NEXT: mov d0, v0.d[1] ; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #9 ; CHECK-GI-NEXT: ret - %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> + %1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %2 = zext <4 x i16> %1 to <4 x i32> %tmp = shl <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9> ret <4 x i32> %tmp @@ -474,7 +473,7 @@ define <4 x i32> @test_ushll2_v8i16_eltsize(<8 x i16> %a) { ; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0 ; CHECK-GI-NEXT: shl v0.4s, v0.4s, #16 ; CHECK-GI-NEXT: ret - %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> + %1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %2 = zext <4 x i16> %1 to <4 x i32> %tmp = shl <4 x i32> %2, <i32 16, i32 16, i32 16, i32 16> ret <4 x i32> %tmp @@ -486,7 +485,7 @@ define <4 x i32> @test_ushll2_v8i16_big(<8 x i16> %a) { ; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0 ; CHECK-NEXT: shl v0.4s, v0.4s, #19 ; CHECK-NEXT: ret - %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> + %1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %2 = zext <4 x i16> %1 to <4 x i32> %tmp = shl <4 x i32> %2, <i32 19, i32 19, i32 19, i32 19> ret <4 x i32> %tmp @@ -503,7 +502,7 @@ define <2 x i64> @test_ushll2_v4i32(<4 x i32> %a) { ; CHECK-GI-NEXT: mov d0, v0.d[1] ; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #19 ; CHECK-GI-NEXT: ret - %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3> + %1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3> %2 = zext <2 x i32> %1 to <2 x i64> %tmp = shl <2 x i64> %2, <i64 19, i64 19> ret <2 x i64> %tmp @@ -520,7 +519,7 @@ define <2 x i64> @test_ushll2_v4i32_eltsize(<4 x i32> %a) { ; CHECK-GI-NEXT: ushll2 v0.2d, v0.4s, #0 ; CHECK-GI-NEXT: shl v0.2d, v0.2d, #32 ; CHECK-GI-NEXT: ret - %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3> + %1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3> %2 = zext <2 x i32> %1 to <2 x i64> %tmp = shl <2 x i64> %2, <i64 32, i64 32> ret <2 x i64> %tmp @@ -532,7 +531,7 @@ define <2 x i64> @test_ushll2_v4i32_big(<4 x i32> %a) { ; CHECK-NEXT: ushll2 v0.2d, v0.4s, #0 ; CHECK-NEXT: shl v0.2d, v0.2d, #36 ; CHECK-NEXT: ret - %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3> + %1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3> %2 = zext <2 x i32> %1 to <2 x i64> %tmp = shl <2 x i64> %2, <i64 36, i64 36> ret <2 x i64> %tmp @@ -597,7 +596,7 @@ define <8 x i16> @test_sshll2_shl0_v16i8(<16 x i8> %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: sshll2 v0.8h, v0.16b, #0 ; CHECK-NEXT: ret - %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %tmp = sext <8 x i8> %1 to <8 x i16> ret <8 x i16> %tmp } @@ -607,7 +606,7 @@ define <4 x i32> @test_sshll2_shl0_v8i16(<8 x i16> %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: sshll2 v0.4s, v0.8h, #0 ; CHECK-NEXT: ret - %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> + %1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp = sext <4 x i16> %1 to <4 x i32> ret <4 x i32> %tmp } @@ -617,7 +616,7 @@ define <2 x i64> @test_sshll2_shl0_v4i32(<4 x i32> %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: sshll2 v0.2d, v0.4s, #0 ; CHECK-NEXT: ret - %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3> + %1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3> %tmp = sext <2 x i32> %1 to <2 x i64> ret <2 x i64> %tmp } @@ -627,7 +626,7 @@ define <8 x i16> @test_ushll2_shl0_v16i8(<16 x i8> %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ushll2 v0.8h, v0.16b, #0 ; CHECK-NEXT: ret - %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %tmp = zext <8 x i8> %1 to <8 x i16> ret <8 x i16> %tmp } @@ -637,7 +636,7 @@ define <4 x i32> @test_ushll2_shl0_v8i16(<8 x i16> %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0 ; CHECK-NEXT: ret - %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> + %1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp = zext <4 x i16> %1 to <4 x i32> ret <4 x i32> %tmp } @@ -647,7 +646,7 @@ define <2 x i64> @test_ushll2_shl0_v4i32(<4 x i32> %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: ushll2 v0.2d, v0.4s, #0 ; CHECK-NEXT: ret - %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3> + %1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3> %tmp = zext <2 x i32> %1 to <2 x i64> ret <2 x i64> %tmp } _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
