https://github.com/iamvickynguyen updated https://github.com/llvm/llvm-project/pull/213755
>From 1bbc4a3afad8cee4ca52532ac9614c646414cd12 Mon Sep 17 00:00:00 2001 From: Vicky Nguyen <[email protected]> Date: Tue, 14 Jul 2026 20:46:19 -0700 Subject: [PATCH] [CIR][AArch64] Upstream saturating-addition NEON builtins --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 39 +- clang/test/CodeGen/AArch64/neon-intrinsics.c | 626 ------------------ clang/test/CodeGen/AArch64/neon/add.c | 557 ++++++++++++++++ 3 files changed, 595 insertions(+), 627 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index 0be493fe9084a..cbea215de83a2 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -303,6 +303,17 @@ deriveNeonSISDIntrinsicOperandTypes(CIRGenFunction &cgf, unsigned modifier, vecArgTy = cir::VectorType::get(arg0Ty, resVecTy.getSize()); } + // True if `ty` is arg0's type, or an integer of the same width that only + // differs in signedness. vsqadd/vuqadd mix the two on purpose: vsqaddb_u8 + // takes a uint8_t and an int8_t, but both become the same vector type. + auto matchesArg0Ty = [&](mlir::Type ty) { + if (ty == arg0Ty) + return true; + auto intTy = mlir::dyn_cast<cir::IntType>(ty); + auto arg0IntTy = mlir::dyn_cast<cir::IntType>(arg0Ty); + return intTy && arg0IntTy && intTy.getWidth() == arg0IntTy.getWidth(); + }; + // `vecArgTy` is populated by `VectorizeArgTypes` or // `ArgAsWidenedRetType`. When set, wrap every non-immediate data operand // that has the same scalar type as arg0. Checking the ICE bitmap prevents @@ -312,7 +323,7 @@ deriveNeonSISDIntrinsicOperandTypes(CIRGenFunction &cgf, unsigned modifier, argTypes.reserve(ops.size()); for (unsigned i = 0, e = ops.size(); i != e; ++i) { bool isImmediate = iceArguments & (1U << i); - if (vecArgTy && !isImmediate && ops[i].getType() == arg0Ty) + if (vecArgTy && !isImmediate && matchesArg0Ty(ops[i].getType())) argTypes.push_back(vecArgTy); else argTypes.push_back(ops[i].getType()); @@ -509,6 +520,22 @@ emitCommonNeonSISDBuiltinExpr(CIRGenFunction &cgf, case NEON::BI__builtin_neon_vqsubs_u32: case NEON::BI__builtin_neon_vqsubd_s64: case NEON::BI__builtin_neon_vqsubd_u64: + case NEON::BI__builtin_neon_vqaddb_s8: + case NEON::BI__builtin_neon_vqaddb_u8: + case NEON::BI__builtin_neon_vqaddh_s16: + case NEON::BI__builtin_neon_vqaddh_u16: + case NEON::BI__builtin_neon_vqadds_s32: + case NEON::BI__builtin_neon_vqadds_u32: + case NEON::BI__builtin_neon_vqaddd_s64: + case NEON::BI__builtin_neon_vqaddd_u64: + case NEON::BI__builtin_neon_vsqaddb_u8: + case NEON::BI__builtin_neon_vsqaddh_u16: + case NEON::BI__builtin_neon_vsqadds_u32: + case NEON::BI__builtin_neon_vsqaddd_u64: + case NEON::BI__builtin_neon_vuqaddb_s8: + case NEON::BI__builtin_neon_vuqaddh_s16: + case NEON::BI__builtin_neon_vuqadds_s32: + case NEON::BI__builtin_neon_vuqaddd_s64: break; } @@ -1237,6 +1264,8 @@ static mlir::Value emitCommonNeonBuiltinExpr( case NEON::BI__builtin_neon_vhaddq_v: case NEON::BI__builtin_neon_vhsub_v: case NEON::BI__builtin_neon_vhsubq_v: + case NEON::BI__builtin_neon_vqadd_v: + case NEON::BI__builtin_neon_vqaddq_v: case NEON::BI__builtin_neon_vrhadd_v: case NEON::BI__builtin_neon_vrhaddq_v: case NEON::BI__builtin_neon_vshl_v: @@ -3515,10 +3544,18 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, case NEON::BI__builtin_neon_vqtbx2q_v: case NEON::BI__builtin_neon_vqtbx3q_v: case NEON::BI__builtin_neon_vqtbx4q_v: + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AArch64 builtin call: ") + + getContext().BuiltinInfo.getName(builtinID)); + return mlir::Value{}; case NEON::BI__builtin_neon_vsqadd_v: case NEON::BI__builtin_neon_vsqaddq_v: + return emitNeonCall(cgm, builder, {ty, ty}, ops, "aarch64.neon.usqadd", ty, + loc); case NEON::BI__builtin_neon_vuqadd_v: case NEON::BI__builtin_neon_vuqaddq_v: + return emitNeonCall(cgm, builder, {ty, ty}, ops, "aarch64.neon.suqadd", ty, + loc); case NEON::BI__builtin_neon_vluti2_laneq_mf8: case NEON::BI__builtin_neon_vluti2_laneq_bf16: case NEON::BI__builtin_neon_vluti2_laneq_f16: diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index 05f563a5331e3..ee91751fed634 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -2325,240 +2325,6 @@ uint64x2_t test_vcltq_f64(float64x2_t v1, float64x2_t v2) { return vcltq_f64(v1, v2); } -// CHECK-LABEL: define dso_local <8 x i8> @test_vqadd_s8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQADD_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8> [[A]], <8 x i8> [[B]]) -// CHECK-NEXT: ret <8 x i8> [[VQADD_V_I]] -// -int8x8_t test_vqadd_s8(int8x8_t a, int8x8_t b) { - return vqadd_s8(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vqadd_s16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[VQADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VQADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VQADD_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> [[VQADD_V_I]], <4 x i16> [[VQADD_V1_I]]) -// CHECK-NEXT: [[VQADD_V3_I:%.*]] = bitcast <4 x i16> [[VQADD_V2_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQADD_V3_I]] to <4 x i16> -// CHECK-NEXT: ret <4 x i16> [[TMP2]] -// -int16x4_t test_vqadd_s16(int16x4_t a, int16x4_t b) { - return vqadd_s16(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vqadd_s32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[VQADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VQADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VQADD_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> [[VQADD_V_I]], <2 x i32> [[VQADD_V1_I]]) -// CHECK-NEXT: [[VQADD_V3_I:%.*]] = bitcast <2 x i32> [[VQADD_V2_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQADD_V3_I]] to <2 x i32> -// CHECK-NEXT: ret <2 x i32> [[TMP2]] -// -int32x2_t test_vqadd_s32(int32x2_t a, int32x2_t b) { - return vqadd_s32(a, b); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vqadd_s64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// CHECK-NEXT: [[VQADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VQADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> -// CHECK-NEXT: [[VQADD_V2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqadd.v1i64(<1 x i64> [[VQADD_V_I]], <1 x i64> [[VQADD_V1_I]]) -// CHECK-NEXT: [[VQADD_V3_I:%.*]] = bitcast <1 x i64> [[VQADD_V2_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQADD_V3_I]] to i64 -// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0 -// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]] -// -int64x1_t test_vqadd_s64(int64x1_t a, int64x1_t b) { - return vqadd_s64(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vqadd_u8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQADD_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqadd.v8i8(<8 x i8> [[A]], <8 x i8> [[B]]) -// CHECK-NEXT: ret <8 x i8> [[VQADD_V_I]] -// -uint8x8_t test_vqadd_u8(uint8x8_t a, uint8x8_t b) { - return vqadd_u8(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vqadd_u16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[VQADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VQADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VQADD_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqadd.v4i16(<4 x i16> [[VQADD_V_I]], <4 x i16> [[VQADD_V1_I]]) -// CHECK-NEXT: [[VQADD_V3_I:%.*]] = bitcast <4 x i16> [[VQADD_V2_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQADD_V3_I]] to <4 x i16> -// CHECK-NEXT: ret <4 x i16> [[TMP2]] -// -uint16x4_t test_vqadd_u16(uint16x4_t a, uint16x4_t b) { - return vqadd_u16(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vqadd_u32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[VQADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VQADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VQADD_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqadd.v2i32(<2 x i32> [[VQADD_V_I]], <2 x i32> [[VQADD_V1_I]]) -// CHECK-NEXT: [[VQADD_V3_I:%.*]] = bitcast <2 x i32> [[VQADD_V2_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQADD_V3_I]] to <2 x i32> -// CHECK-NEXT: ret <2 x i32> [[TMP2]] -// -uint32x2_t test_vqadd_u32(uint32x2_t a, uint32x2_t b) { - return vqadd_u32(a, b); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vqadd_u64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// CHECK-NEXT: [[VQADD_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VQADD_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> -// CHECK-NEXT: [[VQADD_V2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqadd.v1i64(<1 x i64> [[VQADD_V_I]], <1 x i64> [[VQADD_V1_I]]) -// CHECK-NEXT: [[VQADD_V3_I:%.*]] = bitcast <1 x i64> [[VQADD_V2_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQADD_V3_I]] to i64 -// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0 -// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]] -// -uint64x1_t test_vqadd_u64(uint64x1_t a, uint64x1_t b) { - return vqadd_u64(a, b); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vqaddq_s8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQADDQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqadd.v16i8(<16 x i8> [[A]], <16 x i8> [[B]]) -// CHECK-NEXT: ret <16 x i8> [[VQADDQ_V_I]] -// -int8x16_t test_vqaddq_s8(int8x16_t a, int8x16_t b) { - return vqaddq_s8(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vqaddq_s16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// CHECK-NEXT: [[VQADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VQADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK-NEXT: [[VQADDQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> [[VQADDQ_V_I]], <8 x i16> [[VQADDQ_V1_I]]) -// CHECK-NEXT: [[VQADDQ_V3_I:%.*]] = bitcast <8 x i16> [[VQADDQ_V2_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQADDQ_V3_I]] to <8 x i16> -// CHECK-NEXT: ret <8 x i16> [[TMP2]] -// -int16x8_t test_vqaddq_s16(int16x8_t a, int16x8_t b) { - return vqaddq_s16(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vqaddq_s32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> -// CHECK-NEXT: [[VQADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VQADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> -// CHECK-NEXT: [[VQADDQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[VQADDQ_V_I]], <4 x i32> [[VQADDQ_V1_I]]) -// CHECK-NEXT: [[VQADDQ_V3_I:%.*]] = bitcast <4 x i32> [[VQADDQ_V2_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQADDQ_V3_I]] to <4 x i32> -// CHECK-NEXT: ret <4 x i32> [[TMP2]] -// -int32x4_t test_vqaddq_s32(int32x4_t a, int32x4_t b) { - return vqaddq_s32(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vqaddq_s64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// CHECK-NEXT: [[VQADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VQADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> -// CHECK-NEXT: [[VQADDQ_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[VQADDQ_V_I]], <2 x i64> [[VQADDQ_V1_I]]) -// CHECK-NEXT: [[VQADDQ_V3_I:%.*]] = bitcast <2 x i64> [[VQADDQ_V2_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQADDQ_V3_I]] to <2 x i64> -// CHECK-NEXT: ret <2 x i64> [[TMP2]] -// -int64x2_t test_vqaddq_s64(int64x2_t a, int64x2_t b) { - return vqaddq_s64(a, b); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vqaddq_u8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQADDQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.uqadd.v16i8(<16 x i8> [[A]], <16 x i8> [[B]]) -// CHECK-NEXT: ret <16 x i8> [[VQADDQ_V_I]] -// -uint8x16_t test_vqaddq_u8(uint8x16_t a, uint8x16_t b) { - return vqaddq_u8(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vqaddq_u16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// CHECK-NEXT: [[VQADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VQADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK-NEXT: [[VQADDQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqadd.v8i16(<8 x i16> [[VQADDQ_V_I]], <8 x i16> [[VQADDQ_V1_I]]) -// CHECK-NEXT: [[VQADDQ_V3_I:%.*]] = bitcast <8 x i16> [[VQADDQ_V2_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQADDQ_V3_I]] to <8 x i16> -// CHECK-NEXT: ret <8 x i16> [[TMP2]] -// -uint16x8_t test_vqaddq_u16(uint16x8_t a, uint16x8_t b) { - return vqaddq_u16(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vqaddq_u32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> -// CHECK-NEXT: [[VQADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VQADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> -// CHECK-NEXT: [[VQADDQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqadd.v4i32(<4 x i32> [[VQADDQ_V_I]], <4 x i32> [[VQADDQ_V1_I]]) -// CHECK-NEXT: [[VQADDQ_V3_I:%.*]] = bitcast <4 x i32> [[VQADDQ_V2_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQADDQ_V3_I]] to <4 x i32> -// CHECK-NEXT: ret <4 x i32> [[TMP2]] -// -uint32x4_t test_vqaddq_u32(uint32x4_t a, uint32x4_t b) { - return vqaddq_u32(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vqaddq_u64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// CHECK-NEXT: [[VQADDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VQADDQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> -// CHECK-NEXT: [[VQADDQ_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqadd.v2i64(<2 x i64> [[VQADDQ_V_I]], <2 x i64> [[VQADDQ_V1_I]]) -// CHECK-NEXT: [[VQADDQ_V3_I:%.*]] = bitcast <2 x i64> [[VQADDQ_V2_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQADDQ_V3_I]] to <2 x i64> -// CHECK-NEXT: ret <2 x i64> [[TMP2]] -// -uint64x2_t test_vqaddq_u64(uint64x2_t a, uint64x2_t b) { - return vqaddq_u64(a, b); -} - // CHECK-LABEL: define dso_local <8 x i8> @test_vqsub_s8( // CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -5370,98 +5136,6 @@ int64x2_t test_vqdmlsl_high_s32(int64x2_t a, int32x4_t b, int32x4_t c) { return vqdmlsl_high_s32(a, b, c); } -// CHECK-LABEL: define dso_local i8 @test_vqaddb_s8( -// CHECK-SAME: i8 noundef [[A:%.*]], i8 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 -// CHECK-NEXT: [[VQADDB_S8_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]]) -// CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[VQADDB_S8_I]], i64 0 -// CHECK-NEXT: ret i8 [[TMP2]] -// -int8_t test_vqaddb_s8(int8_t a, int8_t b) { - return vqaddb_s8(a, b); -} - -// CHECK-LABEL: define dso_local i16 @test_vqaddh_s16( -// CHECK-SAME: i16 noundef [[A:%.*]], i16 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 -// CHECK-NEXT: [[VQADDH_S16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) -// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[VQADDH_S16_I]], i64 0 -// CHECK-NEXT: ret i16 [[TMP2]] -// -int16_t test_vqaddh_s16(int16_t a, int16_t b) { - return vqaddh_s16(a, b); -} - -// CHECK-LABEL: define dso_local i32 @test_vqadds_s32( -// CHECK-SAME: i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQADDS_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sqadd.i32(i32 [[A]], i32 [[B]]) -// CHECK-NEXT: ret i32 [[VQADDS_S32_I]] -// -int32_t test_vqadds_s32(int32_t a, int32_t b) { - return vqadds_s32(a, b); -} - -// CHECK-LABEL: define dso_local i64 @test_vqaddd_s64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQADDD_S64_I:%.*]] = call i64 @llvm.aarch64.neon.sqadd.i64(i64 [[A]], i64 [[B]]) -// CHECK-NEXT: ret i64 [[VQADDD_S64_I]] -// -int64_t test_vqaddd_s64(int64_t a, int64_t b) { - return vqaddd_s64(a, b); -} - -// CHECK-LABEL: define dso_local i8 @test_vqaddb_u8( -// CHECK-SAME: i8 noundef [[A:%.*]], i8 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 -// CHECK-NEXT: [[VQADDB_U8_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqadd.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]]) -// CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[VQADDB_U8_I]], i64 0 -// CHECK-NEXT: ret i8 [[TMP2]] -// -uint8_t test_vqaddb_u8(uint8_t a, uint8_t b) { - return vqaddb_u8(a, b); -} - -// CHECK-LABEL: define dso_local i16 @test_vqaddh_u16( -// CHECK-SAME: i16 noundef [[A:%.*]], i16 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 -// CHECK-NEXT: [[VQADDH_U16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqadd.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) -// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[VQADDH_U16_I]], i64 0 -// CHECK-NEXT: ret i16 [[TMP2]] -// -uint16_t test_vqaddh_u16(uint16_t a, uint16_t b) { - return vqaddh_u16(a, b); -} - -// CHECK-LABEL: define dso_local i32 @test_vqadds_u32( -// CHECK-SAME: i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQADDS_U32_I:%.*]] = call i32 @llvm.aarch64.neon.uqadd.i32(i32 [[A]], i32 [[B]]) -// CHECK-NEXT: ret i32 [[VQADDS_U32_I]] -// -uint32_t test_vqadds_u32(uint32_t a, uint32_t b) { - return vqadds_u32(a, b); -} - -// CHECK-LABEL: define dso_local i64 @test_vqaddd_u64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQADDD_U64_I:%.*]] = call i64 @llvm.aarch64.neon.uqadd.i64(i64 [[A]], i64 [[B]]) -// CHECK-NEXT: ret i64 [[VQADDD_U64_I]] -// -uint64_t test_vqaddd_u64(uint64_t a, uint64_t b) { - return vqaddd_u64(a, b); -} - // CHECK-LABEL: define dso_local i8 @test_vqshlb_s8( // CHECK-SAME: i8 noundef [[A:%.*]], i8 noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -8266,98 +7940,6 @@ int64_t test_vqnegd_s64(int64_t a) { return (int64_t)vqnegd_s64(a); } -// CHECK-LABEL: define dso_local i8 @test_vuqaddb_s8( -// CHECK-SAME: i8 noundef [[A:%.*]], i8 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 -// CHECK-NEXT: [[VUQADDB_S8_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.suqadd.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]]) -// CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[VUQADDB_S8_I]], i64 0 -// CHECK-NEXT: ret i8 [[TMP2]] -// -int8_t test_vuqaddb_s8(int8_t a, uint8_t b) { - return (int8_t)vuqaddb_s8(a, b); -} - -// CHECK-LABEL: define dso_local i16 @test_vuqaddh_s16( -// CHECK-SAME: i16 noundef [[A:%.*]], i16 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 -// CHECK-NEXT: [[VUQADDH_S16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.suqadd.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) -// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[VUQADDH_S16_I]], i64 0 -// CHECK-NEXT: ret i16 [[TMP2]] -// -int16_t test_vuqaddh_s16(int16_t a, uint16_t b) { - return (int16_t)vuqaddh_s16(a, b); -} - -// CHECK-LABEL: define dso_local i32 @test_vuqadds_s32( -// CHECK-SAME: i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VUQADDS_S32_I:%.*]] = call i32 @llvm.aarch64.neon.suqadd.i32(i32 [[A]], i32 [[B]]) -// CHECK-NEXT: ret i32 [[VUQADDS_S32_I]] -// -int32_t test_vuqadds_s32(int32_t a, uint32_t b) { - return (int32_t)vuqadds_s32(a, b); -} - -// CHECK-LABEL: define dso_local i64 @test_vuqaddd_s64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VUQADDD_S64_I:%.*]] = call i64 @llvm.aarch64.neon.suqadd.i64(i64 [[A]], i64 [[B]]) -// CHECK-NEXT: ret i64 [[VUQADDD_S64_I]] -// -int64_t test_vuqaddd_s64(int64_t a, uint64_t b) { - return (int64_t)vuqaddd_s64(a, b); -} - -// CHECK-LABEL: define dso_local i8 @test_vsqaddb_u8( -// CHECK-SAME: i8 noundef [[A:%.*]], i8 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 -// CHECK-NEXT: [[VSQADDB_U8_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]]) -// CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[VSQADDB_U8_I]], i64 0 -// CHECK-NEXT: ret i8 [[TMP2]] -// -uint8_t test_vsqaddb_u8(uint8_t a, int8_t b) { - return (uint8_t)vsqaddb_u8(a, b); -} - -// CHECK-LABEL: define dso_local i16 @test_vsqaddh_u16( -// CHECK-SAME: i16 noundef [[A:%.*]], i16 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 -// CHECK-NEXT: [[VSQADDH_U16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) -// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[VSQADDH_U16_I]], i64 0 -// CHECK-NEXT: ret i16 [[TMP2]] -// -uint16_t test_vsqaddh_u16(uint16_t a, int16_t b) { - return (uint16_t)vsqaddh_u16(a, b); -} - -// CHECK-LABEL: define dso_local i32 @test_vsqadds_u32( -// CHECK-SAME: i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSQADDS_U32_I:%.*]] = call i32 @llvm.aarch64.neon.usqadd.i32(i32 [[A]], i32 [[B]]) -// CHECK-NEXT: ret i32 [[VSQADDS_U32_I]] -// -uint32_t test_vsqadds_u32(uint32_t a, int32_t b) { - return (uint32_t)vsqadds_u32(a, b); -} - -// CHECK-LABEL: define dso_local i64 @test_vsqaddd_u64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSQADDD_U64_I:%.*]] = call i64 @llvm.aarch64.neon.usqadd.i64(i64 [[A]], i64 [[B]]) -// CHECK-NEXT: ret i64 [[VSQADDD_U64_I]] -// -uint64_t test_vsqaddd_u64(uint64_t a, int64_t b) { - return (uint64_t)vsqaddd_u64(a, b); -} - // CHECK-LABEL: define dso_local i32 @test_vqdmlalh_s16( // CHECK-SAME: i32 noundef [[A:%.*]], i16 noundef [[B:%.*]], i16 noundef [[C:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -12914,214 +12496,6 @@ poly64x2_t test_vreinterpretq_p64_p16(poly16x8_t a) { return vreinterpretq_p64_p16(a); } -// CHECK-LABEL: define dso_local <16 x i8> @test_vuqaddq_s8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VUQADD_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.suqadd.v16i8(<16 x i8> [[A]], <16 x i8> [[B]]) -// CHECK-NEXT: ret <16 x i8> [[VUQADD_I]] -// -int8x16_t test_vuqaddq_s8(int8x16_t a, uint8x16_t b) { - return vuqaddq_s8(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vuqaddq_s32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> -// CHECK-NEXT: [[VUQADD_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VUQADD1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> -// CHECK-NEXT: [[VUQADD2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.suqadd.v4i32(<4 x i32> [[VUQADD_I]], <4 x i32> [[VUQADD1_I]]) -// CHECK-NEXT: ret <4 x i32> [[VUQADD2_I]] -// -int32x4_t test_vuqaddq_s32(int32x4_t a, uint32x4_t b) { - return vuqaddq_s32(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vuqaddq_s64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// CHECK-NEXT: [[VUQADD_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VUQADD1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> -// CHECK-NEXT: [[VUQADD2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.suqadd.v2i64(<2 x i64> [[VUQADD_I]], <2 x i64> [[VUQADD1_I]]) -// CHECK-NEXT: ret <2 x i64> [[VUQADD2_I]] -// -int64x2_t test_vuqaddq_s64(int64x2_t a, uint64x2_t b) { - return vuqaddq_s64(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vuqaddq_s16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// CHECK-NEXT: [[VUQADD_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VUQADD1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK-NEXT: [[VUQADD2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.suqadd.v8i16(<8 x i16> [[VUQADD_I]], <8 x i16> [[VUQADD1_I]]) -// CHECK-NEXT: ret <8 x i16> [[VUQADD2_I]] -// -int16x8_t test_vuqaddq_s16(int16x8_t a, uint16x8_t b) { - return vuqaddq_s16(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vuqadd_s8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VUQADD_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.suqadd.v8i8(<8 x i8> [[A]], <8 x i8> [[B]]) -// CHECK-NEXT: ret <8 x i8> [[VUQADD_I]] -// -int8x8_t test_vuqadd_s8(int8x8_t a, uint8x8_t b) { - return vuqadd_s8(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vuqadd_s32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[VUQADD_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VUQADD1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VUQADD2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.suqadd.v2i32(<2 x i32> [[VUQADD_I]], <2 x i32> [[VUQADD1_I]]) -// CHECK-NEXT: ret <2 x i32> [[VUQADD2_I]] -// -int32x2_t test_vuqadd_s32(int32x2_t a, uint32x2_t b) { - return vuqadd_s32(a, b); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vuqadd_s64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// CHECK-NEXT: [[VUQADD_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VUQADD1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> -// CHECK-NEXT: [[VUQADD2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.suqadd.v1i64(<1 x i64> [[VUQADD_I]], <1 x i64> [[VUQADD1_I]]) -// CHECK-NEXT: ret <1 x i64> [[VUQADD2_I]] -// -int64x1_t test_vuqadd_s64(int64x1_t a, uint64x1_t b) { - return vuqadd_s64(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vuqadd_s16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[VUQADD_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VUQADD1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VUQADD2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.suqadd.v4i16(<4 x i16> [[VUQADD_I]], <4 x i16> [[VUQADD1_I]]) -// CHECK-NEXT: ret <4 x i16> [[VUQADD2_I]] -// -int16x4_t test_vuqadd_s16(int16x4_t a, uint16x4_t b) { - return vuqadd_s16(a, b); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vsqadd_u64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// CHECK-NEXT: [[VSQADD_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VSQADD1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> -// CHECK-NEXT: [[VSQADD2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64> [[VSQADD_I]], <1 x i64> [[VSQADD1_I]]) -// CHECK-NEXT: ret <1 x i64> [[VSQADD2_I]] -// -uint64x1_t test_vsqadd_u64(uint64x1_t a, int64x1_t b) { - return vsqadd_u64(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vsqadd_u8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSQADD_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8> [[A]], <8 x i8> [[B]]) -// CHECK-NEXT: ret <8 x i8> [[VSQADD_I]] -// -uint8x8_t test_vsqadd_u8(uint8x8_t a, int8x8_t b) { - return vsqadd_u8(a, b); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vsqaddq_u8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSQADD_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.usqadd.v16i8(<16 x i8> [[A]], <16 x i8> [[B]]) -// CHECK-NEXT: ret <16 x i8> [[VSQADD_I]] -// -uint8x16_t test_vsqaddq_u8(uint8x16_t a, int8x16_t b) { - return vsqaddq_u8(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vsqadd_u16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[VSQADD_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VSQADD1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VSQADD2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16> [[VSQADD_I]], <4 x i16> [[VSQADD1_I]]) -// CHECK-NEXT: ret <4 x i16> [[VSQADD2_I]] -// -uint16x4_t test_vsqadd_u16(uint16x4_t a, int16x4_t b) { - return vsqadd_u16(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vsqaddq_u16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// CHECK-NEXT: [[VSQADD_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VSQADD1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK-NEXT: [[VSQADD2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.usqadd.v8i16(<8 x i16> [[VSQADD_I]], <8 x i16> [[VSQADD1_I]]) -// CHECK-NEXT: ret <8 x i16> [[VSQADD2_I]] -// -uint16x8_t test_vsqaddq_u16(uint16x8_t a, int16x8_t b) { - return vsqaddq_u16(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vsqadd_u32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[VSQADD_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VSQADD1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VSQADD2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.usqadd.v2i32(<2 x i32> [[VSQADD_I]], <2 x i32> [[VSQADD1_I]]) -// CHECK-NEXT: ret <2 x i32> [[VSQADD2_I]] -// -uint32x2_t test_vsqadd_u32(uint32x2_t a, int32x2_t b) { - return vsqadd_u32(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vsqaddq_u32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> -// CHECK-NEXT: [[VSQADD_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VSQADD1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> -// CHECK-NEXT: [[VSQADD2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.usqadd.v4i32(<4 x i32> [[VSQADD_I]], <4 x i32> [[VSQADD1_I]]) -// CHECK-NEXT: ret <4 x i32> [[VSQADD2_I]] -// -uint32x4_t test_vsqaddq_u32(uint32x4_t a, int32x4_t b) { - return vsqaddq_u32(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vsqaddq_u64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// CHECK-NEXT: [[VSQADD_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VSQADD1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> -// CHECK-NEXT: [[VSQADD2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.usqadd.v2i64(<2 x i64> [[VSQADD_I]], <2 x i64> [[VSQADD1_I]]) -// CHECK-NEXT: ret <2 x i64> [[VSQADD2_I]] -// -uint64x2_t test_vsqaddq_u64(uint64x2_t a, int64x2_t b) { - return vsqaddq_u64(a, b); -} - // CHECK-LABEL: define dso_local <1 x i64> @test_vabs_s64( // CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] diff --git a/clang/test/CodeGen/AArch64/neon/add.c b/clang/test/CodeGen/AArch64/neon/add.c index d462d9bc60a6e..5508f4df7fdfc 100644 --- a/clang/test/CodeGen/AArch64/neon/add.c +++ b/clang/test/CodeGen/AArch64/neon/add.c @@ -1250,3 +1250,560 @@ uint32x4_t test_vraddhn_high_u64(uint32x2_t r, uint64x2_t a, uint64x2_t b) { // LLVM: ret <4 x i32> [[RES]] return vraddhn_high_u64(r, a, b); } + +//===------------------------------------------------------===// +// 2.1.1.1.4. Saturating addition +// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#saturating-addition +//===------------------------------------------------------===// + +// LLVM-LABEL: @test_vqadd_s8( +// CIR-LABEL: @vqadd_s8( +int8x8_t test_vqadd_s8(int8x8_t a, int8x8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.sqadd" + +// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8> [[A]], <8 x i8> [[B]]) +// LLVM: ret <8 x i8> [[RES]] + return vqadd_s8(a, b); +} + +// LLVM-LABEL: @test_vqadd_s16( +// CIR-LABEL: @vqadd_s16( +int16x4_t test_vqadd_s16(int16x4_t a, int16x4_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.sqadd" + +// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> [[A]], <4 x i16> [[B]]) +// LLVM: ret <4 x i16> [[RES]] + return vqadd_s16(a, b); +} + +// LLVM-LABEL: @test_vqadd_s32( +// CIR-LABEL: @vqadd_s32( +int32x2_t test_vqadd_s32(int32x2_t a, int32x2_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.sqadd" + +// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> [[A]], <2 x i32> [[B]]) +// LLVM: ret <2 x i32> [[RES]] + return vqadd_s32(a, b); +} + +// LLVM-LABEL: @test_vqadd_s64( +// CIR-LABEL: @vqadd_s64( +int64x1_t test_vqadd_s64(int64x1_t a, int64x1_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.sqadd" + +// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqadd.v1i64(<1 x i64> [[A]], <1 x i64> [[B]]) +// LLVM: ret <1 x i64> [[RES]] + return vqadd_s64(a, b); +} + +// LLVM-LABEL: @test_vqadd_u8( +// CIR-LABEL: @vqadd_u8( +uint8x8_t test_vqadd_u8(uint8x8_t a, uint8x8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.uqadd" + +// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqadd.v8i8(<8 x i8> [[A]], <8 x i8> [[B]]) +// LLVM: ret <8 x i8> [[RES]] + return vqadd_u8(a, b); +} + +// LLVM-LABEL: @test_vqadd_u16( +// CIR-LABEL: @vqadd_u16( +uint16x4_t test_vqadd_u16(uint16x4_t a, uint16x4_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.uqadd" + +// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqadd.v4i16(<4 x i16> [[A]], <4 x i16> [[B]]) +// LLVM: ret <4 x i16> [[RES]] + return vqadd_u16(a, b); +} + +// LLVM-LABEL: @test_vqadd_u32( +// CIR-LABEL: @vqadd_u32( +uint32x2_t test_vqadd_u32(uint32x2_t a, uint32x2_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.uqadd" + +// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqadd.v2i32(<2 x i32> [[A]], <2 x i32> [[B]]) +// LLVM: ret <2 x i32> [[RES]] + return vqadd_u32(a, b); +} + +// LLVM-LABEL: @test_vqadd_u64( +// CIR-LABEL: @vqadd_u64( +uint64x1_t test_vqadd_u64(uint64x1_t a, uint64x1_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.uqadd" + +// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqadd.v1i64(<1 x i64> [[A]], <1 x i64> [[B]]) +// LLVM: ret <1 x i64> [[RES]] + return vqadd_u64(a, b); +} + +// LLVM-LABEL: @test_vqaddq_s8( +// CIR-LABEL: @vqaddq_s8( +int8x16_t test_vqaddq_s8(int8x16_t a, int8x16_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.sqadd" + +// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqadd.v16i8(<16 x i8> [[A]], <16 x i8> [[B]]) +// LLVM: ret <16 x i8> [[RES]] + return vqaddq_s8(a, b); +} + +// LLVM-LABEL: @test_vqaddq_s16( +// CIR-LABEL: @vqaddq_s16( +int16x8_t test_vqaddq_s16(int16x8_t a, int16x8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.sqadd" + +// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> [[A]], <8 x i16> [[B]]) +// LLVM: ret <8 x i16> [[RES]] + return vqaddq_s16(a, b); +} + +// LLVM-LABEL: @test_vqaddq_s32( +// CIR-LABEL: @vqaddq_s32( +int32x4_t test_vqaddq_s32(int32x4_t a, int32x4_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.sqadd" + +// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) +// LLVM: ret <4 x i32> [[RES]] + return vqaddq_s32(a, b); +} + +// LLVM-LABEL: @test_vqaddq_s64( +// CIR-LABEL: @vqaddq_s64( +int64x2_t test_vqaddq_s64(int64x2_t a, int64x2_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.sqadd" + +// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[A]], <2 x i64> [[B]]) +// LLVM: ret <2 x i64> [[RES]] + return vqaddq_s64(a, b); +} + +// LLVM-LABEL: @test_vqaddq_u8( +// CIR-LABEL: @vqaddq_u8( +uint8x16_t test_vqaddq_u8(uint8x16_t a, uint8x16_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.uqadd" + +// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <16 x i8> @llvm.aarch64.neon.uqadd.v16i8(<16 x i8> [[A]], <16 x i8> [[B]]) +// LLVM: ret <16 x i8> [[RES]] + return vqaddq_u8(a, b); +} + +// LLVM-LABEL: @test_vqaddq_u16( +// CIR-LABEL: @vqaddq_u16( +uint16x8_t test_vqaddq_u16(uint16x8_t a, uint16x8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.uqadd" + +// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqadd.v8i16(<8 x i16> [[A]], <8 x i16> [[B]]) +// LLVM: ret <8 x i16> [[RES]] + return vqaddq_u16(a, b); +} + +// LLVM-LABEL: @test_vqaddq_u32( +// CIR-LABEL: @vqaddq_u32( +uint32x4_t test_vqaddq_u32(uint32x4_t a, uint32x4_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.uqadd" + +// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqadd.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) +// LLVM: ret <4 x i32> [[RES]] + return vqaddq_u32(a, b); +} + +// LLVM-LABEL: @test_vqaddq_u64( +// CIR-LABEL: @vqaddq_u64( +uint64x2_t test_vqaddq_u64(uint64x2_t a, uint64x2_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.uqadd" + +// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqadd.v2i64(<2 x i64> [[A]], <2 x i64> [[B]]) +// LLVM: ret <2 x i64> [[RES]] + return vqaddq_u64(a, b); +} + +// LLVM-LABEL: @test_vqaddb_s8( +// CIR-LABEL: @vqaddb_s8( +int8_t test_vqaddb_s8(int8_t a, int8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.sqadd" + +// LLVM-SAME: i8 {{.*}}[[A:%.*]], i8 {{.*}}[[B:%.*]]) +// LLVM: [[V0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 +// LLVM: [[V1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 +// LLVM: [[RES:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8> [[V0]], <8 x i8> [[V1]]) +// LLVM: [[EXT:%.*]] = extractelement <8 x i8> [[RES]], i64 0 +// LLVM: ret i8 [[EXT]] + return vqaddb_s8(a, b); +} + +// LLVM-LABEL: @test_vqaddh_s16( +// CIR-LABEL: @vqaddh_s16( +int16_t test_vqaddh_s16(int16_t a, int16_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.sqadd" + +// LLVM-SAME: i16 {{.*}}[[A:%.*]], i16 {{.*}}[[B:%.*]]) +// LLVM: [[V0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 +// LLVM: [[V1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 +// LLVM: [[RES:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> [[V0]], <4 x i16> [[V1]]) +// LLVM: [[EXT:%.*]] = extractelement <4 x i16> [[RES]], i64 0 +// LLVM: ret i16 [[EXT]] + return vqaddh_s16(a, b); +} + +// LLVM-LABEL: @test_vqadds_s32( +// CIR-LABEL: @vqadds_s32( +int32_t test_vqadds_s32(int32_t a, int32_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.sqadd" + +// LLVM-SAME: i32 {{.*}}[[A:%.*]], i32 {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call i32 @llvm.aarch64.neon.sqadd.i32(i32 [[A]], i32 [[B]]) +// LLVM: ret i32 [[RES]] + return vqadds_s32(a, b); +} + +// LLVM-LABEL: @test_vqaddd_s64( +// CIR-LABEL: @vqaddd_s64( +int64_t test_vqaddd_s64(int64_t a, int64_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.sqadd" + +// LLVM-SAME: i64 {{.*}}[[A:%.*]], i64 {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call i64 @llvm.aarch64.neon.sqadd.i64(i64 [[A]], i64 [[B]]) +// LLVM: ret i64 [[RES]] + return vqaddd_s64(a, b); +} + +// LLVM-LABEL: @test_vqaddb_u8( +// CIR-LABEL: @vqaddb_u8( +uint8_t test_vqaddb_u8(uint8_t a, uint8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.uqadd" + +// LLVM-SAME: i8 {{.*}}[[A:%.*]], i8 {{.*}}[[B:%.*]]) +// LLVM: [[V0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 +// LLVM: [[V1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 +// LLVM: [[RES:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqadd.v8i8(<8 x i8> [[V0]], <8 x i8> [[V1]]) +// LLVM: [[EXT:%.*]] = extractelement <8 x i8> [[RES]], i64 0 +// LLVM: ret i8 [[EXT]] + return vqaddb_u8(a, b); +} + +// LLVM-LABEL: @test_vqaddh_u16( +// CIR-LABEL: @vqaddh_u16( +uint16_t test_vqaddh_u16(uint16_t a, uint16_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.uqadd" + +// LLVM-SAME: i16 {{.*}}[[A:%.*]], i16 {{.*}}[[B:%.*]]) +// LLVM: [[V0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 +// LLVM: [[V1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 +// LLVM: [[RES:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqadd.v4i16(<4 x i16> [[V0]], <4 x i16> [[V1]]) +// LLVM: [[EXT:%.*]] = extractelement <4 x i16> [[RES]], i64 0 +// LLVM: ret i16 [[EXT]] + return vqaddh_u16(a, b); +} + +// LLVM-LABEL: @test_vqadds_u32( +// CIR-LABEL: @vqadds_u32( +uint32_t test_vqadds_u32(uint32_t a, uint32_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.uqadd" + +// LLVM-SAME: i32 {{.*}}[[A:%.*]], i32 {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call i32 @llvm.aarch64.neon.uqadd.i32(i32 [[A]], i32 [[B]]) +// LLVM: ret i32 [[RES]] + return vqadds_u32(a, b); +} + +// LLVM-LABEL: @test_vqaddd_u64( +// CIR-LABEL: @vqaddd_u64( +uint64_t test_vqaddd_u64(uint64_t a, uint64_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.uqadd" + +// LLVM-SAME: i64 {{.*}}[[A:%.*]], i64 {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call i64 @llvm.aarch64.neon.uqadd.i64(i64 [[A]], i64 [[B]]) +// LLVM: ret i64 [[RES]] + return vqaddd_u64(a, b); +} + +// LLVM-LABEL: @test_vsqadd_u8( +// CIR-LABEL: @vsqadd_u8( +uint8x8_t test_vsqadd_u8(uint8x8_t a, int8x8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.usqadd" + +// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8> [[A]], <8 x i8> [[B]]) +// LLVM: ret <8 x i8> [[RES]] + return vsqadd_u8(a, b); +} + +// LLVM-LABEL: @test_vsqadd_u16( +// CIR-LABEL: @vsqadd_u16( +uint16x4_t test_vsqadd_u16(uint16x4_t a, int16x4_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.usqadd" + +// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16> [[A]], <4 x i16> [[B]]) +// LLVM: ret <4 x i16> [[RES]] + return vsqadd_u16(a, b); +} + +// LLVM-LABEL: @test_vsqadd_u32( +// CIR-LABEL: @vsqadd_u32( +uint32x2_t test_vsqadd_u32(uint32x2_t a, int32x2_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.usqadd" + +// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <2 x i32> @llvm.aarch64.neon.usqadd.v2i32(<2 x i32> [[A]], <2 x i32> [[B]]) +// LLVM: ret <2 x i32> [[RES]] + return vsqadd_u32(a, b); +} + +// LLVM-LABEL: @test_vsqadd_u64( +// CIR-LABEL: @vsqadd_u64( +uint64x1_t test_vsqadd_u64(uint64x1_t a, int64x1_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.usqadd" + +// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64> [[A]], <1 x i64> [[B]]) +// LLVM: ret <1 x i64> [[RES]] + return vsqadd_u64(a, b); +} + +// LLVM-LABEL: @test_vsqaddq_u8( +// CIR-LABEL: @vsqaddq_u8( +uint8x16_t test_vsqaddq_u8(uint8x16_t a, int8x16_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.usqadd" + +// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <16 x i8> @llvm.aarch64.neon.usqadd.v16i8(<16 x i8> [[A]], <16 x i8> [[B]]) +// LLVM: ret <16 x i8> [[RES]] + return vsqaddq_u8(a, b); +} + +// LLVM-LABEL: @test_vsqaddq_u16( +// CIR-LABEL: @vsqaddq_u16( +uint16x8_t test_vsqaddq_u16(uint16x8_t a, int16x8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.usqadd" + +// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <8 x i16> @llvm.aarch64.neon.usqadd.v8i16(<8 x i16> [[A]], <8 x i16> [[B]]) +// LLVM: ret <8 x i16> [[RES]] + return vsqaddq_u16(a, b); +} + +// LLVM-LABEL: @test_vsqaddq_u32( +// CIR-LABEL: @vsqaddq_u32( +uint32x4_t test_vsqaddq_u32(uint32x4_t a, int32x4_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.usqadd" + +// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <4 x i32> @llvm.aarch64.neon.usqadd.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) +// LLVM: ret <4 x i32> [[RES]] + return vsqaddq_u32(a, b); +} + +// LLVM-LABEL: @test_vsqaddq_u64( +// CIR-LABEL: @vsqaddq_u64( +uint64x2_t test_vsqaddq_u64(uint64x2_t a, int64x2_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.usqadd" + +// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <2 x i64> @llvm.aarch64.neon.usqadd.v2i64(<2 x i64> [[A]], <2 x i64> [[B]]) +// LLVM: ret <2 x i64> [[RES]] + return vsqaddq_u64(a, b); +} + +// LLVM-LABEL: @test_vsqaddb_u8( +// CIR-LABEL: @vsqaddb_u8( +uint8_t test_vsqaddb_u8(uint8_t a, int8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.usqadd" + +// LLVM-SAME: i8 {{.*}}[[A:%.*]], i8 {{.*}}[[B:%.*]]) +// LLVM: [[V0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 +// LLVM: [[V1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 +// LLVM: [[RES:%.*]] = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8> [[V0]], <8 x i8> [[V1]]) +// LLVM: [[EXT:%.*]] = extractelement <8 x i8> [[RES]], i64 0 +// LLVM: ret i8 [[EXT]] + return (uint8_t)vsqaddb_u8(a, b); +} + +// LLVM-LABEL: @test_vsqaddh_u16( +// CIR-LABEL: @vsqaddh_u16( +uint16_t test_vsqaddh_u16(uint16_t a, int16_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.usqadd" + +// LLVM-SAME: i16 {{.*}}[[A:%.*]], i16 {{.*}}[[B:%.*]]) +// LLVM: [[V0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 +// LLVM: [[V1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 +// LLVM: [[RES:%.*]] = call <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16> [[V0]], <4 x i16> [[V1]]) +// LLVM: [[EXT:%.*]] = extractelement <4 x i16> [[RES]], i64 0 +// LLVM: ret i16 [[EXT]] + return (uint16_t)vsqaddh_u16(a, b); +} + +// LLVM-LABEL: @test_vsqadds_u32( +// CIR-LABEL: @vsqadds_u32( +uint32_t test_vsqadds_u32(uint32_t a, int32_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.usqadd" + +// LLVM-SAME: i32 {{.*}}[[A:%.*]], i32 {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call i32 @llvm.aarch64.neon.usqadd.i32(i32 [[A]], i32 [[B]]) +// LLVM: ret i32 [[RES]] + return (uint32_t)vsqadds_u32(a, b); +} + +// LLVM-LABEL: @test_vsqaddd_u64( +// CIR-LABEL: @vsqaddd_u64( +uint64_t test_vsqaddd_u64(uint64_t a, int64_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.usqadd" + +// LLVM-SAME: i64 {{.*}}[[A:%.*]], i64 {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call i64 @llvm.aarch64.neon.usqadd.i64(i64 [[A]], i64 [[B]]) +// LLVM: ret i64 [[RES]] + return (uint64_t)vsqaddd_u64(a, b); +} + +// LLVM-LABEL: @test_vuqadd_s8( +// CIR-LABEL: @vuqadd_s8( +int8x8_t test_vuqadd_s8(int8x8_t a, uint8x8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.suqadd" + +// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <8 x i8> @llvm.aarch64.neon.suqadd.v8i8(<8 x i8> [[A]], <8 x i8> [[B]]) +// LLVM: ret <8 x i8> [[RES]] + return vuqadd_s8(a, b); +} + +// LLVM-LABEL: @test_vuqadd_s16( +// CIR-LABEL: @vuqadd_s16( +int16x4_t test_vuqadd_s16(int16x4_t a, uint16x4_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.suqadd" + +// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <4 x i16> @llvm.aarch64.neon.suqadd.v4i16(<4 x i16> [[A]], <4 x i16> [[B]]) +// LLVM: ret <4 x i16> [[RES]] + return vuqadd_s16(a, b); +} + +// LLVM-LABEL: @test_vuqadd_s32( +// CIR-LABEL: @vuqadd_s32( +int32x2_t test_vuqadd_s32(int32x2_t a, uint32x2_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.suqadd" + +// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <2 x i32> @llvm.aarch64.neon.suqadd.v2i32(<2 x i32> [[A]], <2 x i32> [[B]]) +// LLVM: ret <2 x i32> [[RES]] + return vuqadd_s32(a, b); +} + +// LLVM-LABEL: @test_vuqadd_s64( +// CIR-LABEL: @vuqadd_s64( +int64x1_t test_vuqadd_s64(int64x1_t a, uint64x1_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.suqadd" + +// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <1 x i64> @llvm.aarch64.neon.suqadd.v1i64(<1 x i64> [[A]], <1 x i64> [[B]]) +// LLVM: ret <1 x i64> [[RES]] + return vuqadd_s64(a, b); +} + +// LLVM-LABEL: @test_vuqaddq_s8( +// CIR-LABEL: @vuqaddq_s8( +int8x16_t test_vuqaddq_s8(int8x16_t a, uint8x16_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.suqadd" + +// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <16 x i8> @llvm.aarch64.neon.suqadd.v16i8(<16 x i8> [[A]], <16 x i8> [[B]]) +// LLVM: ret <16 x i8> [[RES]] + return vuqaddq_s8(a, b); +} + +// LLVM-LABEL: @test_vuqaddq_s16( +// CIR-LABEL: @vuqaddq_s16( +int16x8_t test_vuqaddq_s16(int16x8_t a, uint16x8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.suqadd" + +// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <8 x i16> @llvm.aarch64.neon.suqadd.v8i16(<8 x i16> [[A]], <8 x i16> [[B]]) +// LLVM: ret <8 x i16> [[RES]] + return vuqaddq_s16(a, b); +} + +// LLVM-LABEL: @test_vuqaddq_s32( +// CIR-LABEL: @vuqaddq_s32( +int32x4_t test_vuqaddq_s32(int32x4_t a, uint32x4_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.suqadd" + +// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <4 x i32> @llvm.aarch64.neon.suqadd.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) +// LLVM: ret <4 x i32> [[RES]] + return vuqaddq_s32(a, b); +} + +// LLVM-LABEL: @test_vuqaddq_s64( +// CIR-LABEL: @vuqaddq_s64( +int64x2_t test_vuqaddq_s64(int64x2_t a, uint64x2_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.suqadd" + +// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call <2 x i64> @llvm.aarch64.neon.suqadd.v2i64(<2 x i64> [[A]], <2 x i64> [[B]]) +// LLVM: ret <2 x i64> [[RES]] + return vuqaddq_s64(a, b); +} + +// LLVM-LABEL: @test_vuqaddb_s8( +// CIR-LABEL: @vuqaddb_s8( +int8_t test_vuqaddb_s8(int8_t a, uint8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.suqadd" + +// LLVM-SAME: i8 {{.*}}[[A:%.*]], i8 {{.*}}[[B:%.*]]) +// LLVM: [[V0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 +// LLVM: [[V1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 +// LLVM: [[RES:%.*]] = call <8 x i8> @llvm.aarch64.neon.suqadd.v8i8(<8 x i8> [[V0]], <8 x i8> [[V1]]) +// LLVM: [[EXT:%.*]] = extractelement <8 x i8> [[RES]], i64 0 +// LLVM: ret i8 [[EXT]] + return (int8_t)vuqaddb_s8(a, b); +} + +// LLVM-LABEL: @test_vuqaddh_s16( +// CIR-LABEL: @vuqaddh_s16( +int16_t test_vuqaddh_s16(int16_t a, uint16_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.suqadd" + +// LLVM-SAME: i16 {{.*}}[[A:%.*]], i16 {{.*}}[[B:%.*]]) +// LLVM: [[V0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 +// LLVM: [[V1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 +// LLVM: [[RES:%.*]] = call <4 x i16> @llvm.aarch64.neon.suqadd.v4i16(<4 x i16> [[V0]], <4 x i16> [[V1]]) +// LLVM: [[EXT:%.*]] = extractelement <4 x i16> [[RES]], i64 0 +// LLVM: ret i16 [[EXT]] + return (int16_t)vuqaddh_s16(a, b); +} + +// LLVM-LABEL: @test_vuqadds_s32( +// CIR-LABEL: @vuqadds_s32( +int32_t test_vuqadds_s32(int32_t a, uint32_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.suqadd" + +// LLVM-SAME: i32 {{.*}}[[A:%.*]], i32 {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call i32 @llvm.aarch64.neon.suqadd.i32(i32 [[A]], i32 [[B]]) +// LLVM: ret i32 [[RES]] + return (int32_t)vuqadds_s32(a, b); +} + +// LLVM-LABEL: @test_vuqaddd_s64( +// CIR-LABEL: @vuqaddd_s64( +int64_t test_vuqaddd_s64(int64_t a, uint64_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.suqadd" + +// LLVM-SAME: i64 {{.*}}[[A:%.*]], i64 {{.*}}[[B:%.*]]) +// LLVM: [[RES:%.*]] = call i64 @llvm.aarch64.neon.suqadd.i64(i64 [[A]], i64 [[B]]) +// LLVM: ret i64 [[RES]] + return (int64_t)vuqaddd_s64(a, b); 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