Author: Andy Kaylor Date: 2026-08-06T09:15:09-07:00 New Revision: 3bace2206a56e39766a0697d1d63b05f537793a6
URL: https://github.com/llvm/llvm-project/commit/3bace2206a56e39766a0697d1d63b05f537793a6 DIFF: https://github.com/llvm/llvm-project/commit/3bace2206a56e39766a0697d1d63b05f537793a6.diff LOG: [CIR][AArch64] Update builtin handlers to use emitNeonCallToOp (#214075) This is another change to prepare AArch64 builtin handling for the transition to constrained FP handling. It replaces a number of places where we were creating CIR operations directly with calls to emitNeonCallToOp so that we will be able to centralize the constrained FP handling. This also updates the vrndns_f32 to eliminate a redundant load of the operand, which is the only part of this change with a visible difference in the output. Assisted-by: Cursor / Grok 4.5 Added: Modified: clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp clang/test/CodeGen/AArch64/neon/intrinsics.c Removed: ################################################################################ diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index cbea215de83a2..838d5af867c8d 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -2567,7 +2567,9 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, default: break; case NEON::BI__builtin_neon_vabsh_f16: { - return cir::FAbsOp::create(builder, loc, ops); + mlir::Type halfTy = builder.getFp16Ty(); + return emitNeonCallToOp<cir::FAbsOp>(cgm, builder, {halfTy}, ops, + std::nullopt, halfTy, loc); } case NEON::BI__builtin_neon_vaddq_p128: { cir::VectorType byteTy = cir::VectorType::get(builder.getUInt8Ty(), 16); @@ -3135,28 +3137,40 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, return emitNeonCall(cgm, builder, {argTy, sInt32Ty}, ops, intrName, ty, loc); } - case NEON::BI__builtin_neon_vrndah_f16: + case NEON::BI__builtin_neon_vrndah_f16: { assert(!cir::MissingFeatures::emitConstrainedFPCall()); - return cir::RoundOp::create(builder, loc, ops[0]); + mlir::Type halfTy = builder.getFp16Ty(); + return emitNeonCallToOp<cir::RoundOp>(cgm, builder, {halfTy}, ops, + std::nullopt, halfTy, loc); + } case NEON::BI__builtin_neon_vrnda_v: case NEON::BI__builtin_neon_vrndaq_v: assert(!cir::MissingFeatures::emitConstrainedFPCall()); return emitNeonCallToOp<cir::RoundOp>(cgm, builder, {ty}, ops, std::nullopt, ty, loc); - case NEON::BI__builtin_neon_vrndih_f16: + case NEON::BI__builtin_neon_vrndih_f16: { assert(!cir::MissingFeatures::emitConstrainedFPCall()); - return cir::NearbyintOp::create(builder, loc, ops[0]); - case NEON::BI__builtin_neon_vrndmh_f16: + mlir::Type halfTy = builder.getFp16Ty(); + return emitNeonCallToOp<cir::NearbyintOp>(cgm, builder, {halfTy}, ops, + std::nullopt, halfTy, loc); + } + case NEON::BI__builtin_neon_vrndmh_f16: { assert(!cir::MissingFeatures::emitConstrainedFPCall()); - return cir::FloorOp::create(builder, loc, ops[0]); + mlir::Type halfTy = builder.getFp16Ty(); + return emitNeonCallToOp<cir::FloorOp>(cgm, builder, {halfTy}, ops, + std::nullopt, halfTy, loc); + } case NEON::BI__builtin_neon_vrndm_v: case NEON::BI__builtin_neon_vrndmq_v: assert(!cir::MissingFeatures::emitConstrainedFPCall()); return emitNeonCallToOp<cir::FloorOp>(cgm, builder, {ty}, ops, std::nullopt, ty, loc); - case NEON::BI__builtin_neon_vrndnh_f16: + case NEON::BI__builtin_neon_vrndnh_f16: { assert(!cir::MissingFeatures::emitConstrainedFPCall()); - return cir::RoundEvenOp::create(builder, loc, ops[0]); + mlir::Type halfTy = builder.getFp16Ty(); + return emitNeonCallToOp<cir::RoundEvenOp>(cgm, builder, {halfTy}, ops, + std::nullopt, halfTy, loc); + } case NEON::BI__builtin_neon_vrndn_v: case NEON::BI__builtin_neon_vrndnq_v: assert(!cir::MissingFeatures::emitConstrainedFPCall()); @@ -3164,28 +3178,38 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, std::nullopt, ty, loc); case NEON::BI__builtin_neon_vrndns_f32: { assert(!cir::MissingFeatures::emitConstrainedFPCall()); - mlir::Value arg0 = emitScalarExpr(expr->getArg(0)); - return cir::RoundEvenOp::create(builder, getLoc(expr->getExprLoc()), arg0); + mlir::Type floatTy = builder.getSingleTy(); + return emitNeonCallToOp<cir::RoundEvenOp>(cgm, builder, {floatTy}, ops, + std::nullopt, floatTy, loc); } - case NEON::BI__builtin_neon_vrndph_f16: + case NEON::BI__builtin_neon_vrndph_f16: { assert(!cir::MissingFeatures::emitConstrainedFPCall()); - return cir::CeilOp::create(builder, loc, ops[0]); + mlir::Type halfTy = builder.getFp16Ty(); + return emitNeonCallToOp<cir::CeilOp>(cgm, builder, {halfTy}, ops, + std::nullopt, halfTy, loc); + } case NEON::BI__builtin_neon_vrndp_v: case NEON::BI__builtin_neon_vrndpq_v: assert(!cir::MissingFeatures::emitConstrainedFPCall()); return emitNeonCallToOp<cir::CeilOp>(cgm, builder, {ty}, ops, std::nullopt, ty, loc); - case NEON::BI__builtin_neon_vrndxh_f16: + case NEON::BI__builtin_neon_vrndxh_f16: { assert(!cir::MissingFeatures::emitConstrainedFPCall()); - return cir::RintOp::create(builder, loc, ops[0]); + mlir::Type halfTy = builder.getFp16Ty(); + return emitNeonCallToOp<cir::RintOp>(cgm, builder, {halfTy}, ops, + std::nullopt, halfTy, loc); + } case NEON::BI__builtin_neon_vrndx_v: case NEON::BI__builtin_neon_vrndxq_v: assert(!cir::MissingFeatures::emitConstrainedFPCall()); return emitNeonCallToOp<cir::RintOp>(cgm, builder, {ty}, ops, std::nullopt, ty, loc); - case NEON::BI__builtin_neon_vrndh_f16: + case NEON::BI__builtin_neon_vrndh_f16: { assert(!cir::MissingFeatures::emitConstrainedFPCall()); - return cir::TruncOp::create(builder, loc, ops[0]); + mlir::Type halfTy = builder.getFp16Ty(); + return emitNeonCallToOp<cir::TruncOp>(cgm, builder, {halfTy}, ops, + std::nullopt, halfTy, loc); + } case NEON::BI__builtin_neon_vrnd_v: case NEON::BI__builtin_neon_vrndq_v: assert(!cir::MissingFeatures::emitConstrainedFPCall()); diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index d401a3223d926..465d775926851 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -7251,7 +7251,6 @@ float64x2_t test_vrndnq_f64(float64x2_t a) { // LLVM-LABEL: @test_vrndns_f32( // CIR-LABEL: @vrndns_f32( float32_t test_vrndns_f32(float32_t a) { -// CIR: cir.load {{.*}} : !cir.ptr<!cir.float>, !cir.float // CIR: [[LOAD:%.*]] = cir.load {{.*}} : !cir.ptr<!cir.float>, !cir.float // CIR: cir.roundeven [[LOAD]] : !cir.float _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
