https://github.com/Men-cotton created https://github.com/llvm/llvm-project/pull/215722
Add a test for `__atomic_compare_exchange_n` when both success and failure memory orders are runtime values. Check the nested CIR switches across every generated memory-order combination. Partially addresses #156747. >From e998d544744956a856caffb6ee1afafb02978af5 Mon Sep 17 00:00:00 2001 From: mencotton <[email protected]> Date: Wed, 12 Aug 2026 12:28:05 +0900 Subject: [PATCH] [CIR][NFC] Add atomic compare-exchange runtime order test Add a test for `__atomic_compare_exchange_n` when both success and failure memory orders are runtime values. Check the nested CIR switches across every generated memory-order combination. Partially addresses #156747. --- clang/test/CIR/CodeGen/atomic.c | 60 +++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/clang/test/CIR/CodeGen/atomic.c b/clang/test/CIR/CodeGen/atomic.c index f9d6f3c4b54e1..91ad2cd592cb5 100644 --- a/clang/test/CIR/CodeGen/atomic.c +++ b/clang/test/CIR/CodeGen/atomic.c @@ -3354,6 +3354,66 @@ int atomic_load_and_store_dynamic_order(int *ptr, int order) { // OGCG-NEXT: %{{.+}} = load i32, ptr %[[RES_SLOT]], align 4 } +_Bool atomic_compare_exchange_n(int *ptr, int *expected, int desired, + int success, int failure) { + // CIR-LABEL: @atomic_compare_exchange_n + // LLVM-LABEL: @atomic_compare_exchange_n + // OGCG-LABEL: @atomic_compare_exchange_n + + // CIR: %[[SUCCESS_ADDR:.+]] = cir.alloca "success" + // CIR: %[[FAILURE_ADDR:.+]] = cir.alloca "failure" + // CIR: %[[SUCCESS:.+]] = cir.load align(4) %[[SUCCESS_ADDR]] + // CIR: cir.switch(%[[SUCCESS]] : !s32i) + // CIR-NEXT: cir.case(default, []) + // CIR-NEXT: %[[FAILURE:.+]] = cir.load align(4) %[[FAILURE_ADDR]] + // CIR-NEXT: cir.switch(%[[FAILURE]] : !s32i) + // CIR-NEXT: cir.case(default, []) + // CIR: cir.atomic.cmpxchg success(relaxed) failure(relaxed) + // CIR: cir.case(anyof, [#cir.int<1> : !s32i, #cir.int<2> : !s32i]) + // CIR: cir.atomic.cmpxchg success(relaxed) failure(acquire) + // CIR: cir.case(anyof, [#cir.int<5> : !s32i]) + // CIR: cir.atomic.cmpxchg success(relaxed) failure(seq_cst) + // CIR: cir.case(anyof, [#cir.int<1> : !s32i, #cir.int<2> : !s32i]) + // CIR-NEXT: %[[FAILURE:.+]] = cir.load align(4) %[[FAILURE_ADDR]] + // CIR-NEXT: cir.switch(%[[FAILURE]] : !s32i) + // CIR-NEXT: cir.case(default, []) + // CIR: cir.atomic.cmpxchg success(acquire) failure(relaxed) + // CIR: cir.case(anyof, [#cir.int<1> : !s32i, #cir.int<2> : !s32i]) + // CIR: cir.atomic.cmpxchg success(acquire) failure(acquire) + // CIR: cir.case(anyof, [#cir.int<5> : !s32i]) + // CIR: cir.atomic.cmpxchg success(acquire) failure(seq_cst) + // CIR: cir.case(anyof, [#cir.int<3> : !s32i]) + // CIR-NEXT: %[[FAILURE:.+]] = cir.load align(4) %[[FAILURE_ADDR]] + // CIR-NEXT: cir.switch(%[[FAILURE]] : !s32i) + // CIR-NEXT: cir.case(default, []) + // CIR: cir.atomic.cmpxchg success(release) failure(relaxed) + // CIR: cir.case(anyof, [#cir.int<1> : !s32i, #cir.int<2> : !s32i]) + // CIR: cir.atomic.cmpxchg success(release) failure(acquire) + // CIR: cir.case(anyof, [#cir.int<5> : !s32i]) + // CIR: cir.atomic.cmpxchg success(release) failure(seq_cst) + // CIR: cir.case(anyof, [#cir.int<4> : !s32i]) + // CIR-NEXT: %[[FAILURE:.+]] = cir.load align(4) %[[FAILURE_ADDR]] + // CIR-NEXT: cir.switch(%[[FAILURE]] : !s32i) + // CIR-NEXT: cir.case(default, []) + // CIR: cir.atomic.cmpxchg success(acq_rel) failure(relaxed) + // CIR: cir.case(anyof, [#cir.int<1> : !s32i, #cir.int<2> : !s32i]) + // CIR: cir.atomic.cmpxchg success(acq_rel) failure(acquire) + // CIR: cir.case(anyof, [#cir.int<5> : !s32i]) + // CIR: cir.atomic.cmpxchg success(acq_rel) failure(seq_cst) + // CIR: cir.case(anyof, [#cir.int<5> : !s32i]) + // CIR-NEXT: %[[FAILURE:.+]] = cir.load align(4) %[[FAILURE_ADDR]] + // CIR-NEXT: cir.switch(%[[FAILURE]] : !s32i) + // CIR-NEXT: cir.case(default, []) + // CIR: cir.atomic.cmpxchg success(seq_cst) failure(relaxed) + // CIR: cir.case(anyof, [#cir.int<1> : !s32i, #cir.int<2> : !s32i]) + // CIR: cir.atomic.cmpxchg success(seq_cst) failure(acquire) + // CIR: cir.case(anyof, [#cir.int<5> : !s32i]) + // CIR: cir.atomic.cmpxchg success(seq_cst) failure(seq_cst) + + return __atomic_compare_exchange_n(ptr, expected, desired, 0, success, + failure); +} + int atomic_fetch_uinc(int *ptr, int value) { // CIR-LABEL: @atomic_fetch_uinc // LLVM-LABEL: @atomic_fetch_uinc _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
