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<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Zeyi Xu (zeyi2) <details> <summary>Changes</summary> The SiFive CLIC interrupt values may be combined with each other and with the machine value, but the interrupt attribute previously accepted at most two arguments. This commit allows three arguments for the combination of machine, SiFive-CLIC-preemptible, and SiFive-CLIC-stack-swap. Fixes #<!-- -->216138 --- Full diff: https://github.com/llvm/llvm-project/pull/216159.diff 4 Files Affected: - (modified) clang/docs/ReleaseNotes.md (+3) - (modified) clang/lib/Sema/SemaRISCV.cpp (+13-4) - (modified) clang/test/Sema/riscv-interrupt-attr-sifive.c (+14-1) - (modified) clang/test/Sema/riscv-interrupt-attr.c (+3-1) ``````````diff diff --git a/clang/docs/ReleaseNotes.md b/clang/docs/ReleaseNotes.md index e4a6f72f8fec5..b2a2fb2c43386 100644 --- a/clang/docs/ReleaseNotes.md +++ b/clang/docs/ReleaseNotes.md @@ -535,6 +535,9 @@ features cannot lower the translation-unit ABI level; #### RISC-V Support +- Fixed a bug where the `interrupt` attribute did not accept `machine` together + with both `SiFive-CLIC-preemptible` and `SiFive-CLIC-stack-swap`. + #### CUDA/HIP Language Changes - HIP compilations now add the `include/libhipcxx` directory from the selected diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp index 9647a7d913744..3feabb1d1e6e7 100644 --- a/clang/lib/Sema/SemaRISCV.cpp +++ b/clang/lib/Sema/SemaRISCV.cpp @@ -1618,7 +1618,7 @@ void SemaRISCV::handleInterruptAttr(Decl *D, const ParsedAttr &AL) { // - Must be a function. // - Must have no parameters. // - Must have the 'void' return type. - // - The attribute itself must have at most 2 arguments + // - The attribute itself must have at most 3 arguments // - The attribute arguments must be string literals, and valid choices. // - The attribute arguments must be a valid combination // - The current target must support the right extensions for the combination. @@ -1641,13 +1641,13 @@ void SemaRISCV::handleInterruptAttr(Decl *D, const ParsedAttr &AL) { return; } - if (!AL.checkAtMostNumArgs(SemaRef, 2)) + if (!AL.checkAtMostNumArgs(SemaRef, 3)) return; bool HasSiFiveCLICType = false; bool HasUnaryType = false; - SmallSet<RISCVInterruptAttr::InterruptType, 2> Types; + SmallSet<RISCVInterruptAttr::InterruptType, 3> Types; for (unsigned ArgIndex = 0; ArgIndex < AL.getNumArgs(); ++ArgIndex) { RISCVInterruptAttr::InterruptType Type; StringRef TypeString; @@ -1686,6 +1686,15 @@ void SemaRISCV::handleInterruptAttr(Decl *D, const ParsedAttr &AL) { Types.insert(Type); } + const bool IsSiFiveCLICTriple = + Types.size() == 3 && Types.contains(RISCVInterruptAttr::machine) && + Types.contains(RISCVInterruptAttr::SiFiveCLICPreemptible) && + Types.contains(RISCVInterruptAttr::SiFiveCLICStackSwap); + if (AL.getNumArgs() == 3 && !IsSiFiveCLICTriple) { + Diag(AL.getLoc(), diag::err_riscv_attribute_interrupt_invalid_combination); + return; + } + if (HasUnaryType && Types.size() > 1) { Diag(AL.getLoc(), diag::err_riscv_attribute_interrupt_invalid_combination); return; @@ -1745,7 +1754,7 @@ void SemaRISCV::handleInterruptAttr(Decl *D, const ParsedAttr &AL) { } } - SmallVector<RISCVInterruptAttr::InterruptType, 2> TypesVec(Types.begin(), + SmallVector<RISCVInterruptAttr::InterruptType, 3> TypesVec(Types.begin(), Types.end()); D->addAttr(::new (getASTContext()) RISCVInterruptAttr( diff --git a/clang/test/Sema/riscv-interrupt-attr-sifive.c b/clang/test/Sema/riscv-interrupt-attr-sifive.c index 9b41e38664d8d..f2256241a0a37 100644 --- a/clang/test/Sema/riscv-interrupt-attr-sifive.c +++ b/clang/test/Sema/riscv-interrupt-attr-sifive.c @@ -56,6 +56,17 @@ void foo_preemptible_machine(void) {} __attribute__((interrupt("machine", "SiFive-CLIC-preemptible"))) void foo_machine_preemptible(void) {} +// CHECK-LABEL: @foo_machine_stack_swap_preemptible() #2 +// CHECK: ret void +__attribute__((interrupt("machine", "SiFive-CLIC-stack-swap", + "SiFive-CLIC-preemptible"))) +void foo_machine_stack_swap_preemptible(void) {} + +// CHECK-LABEL: @foo_preemptible_stack_swap_machine() #2 +// CHECK: ret void +__attribute__((interrupt("SiFive-CLIC-preemptible", + "SiFive-CLIC-stack-swap", "machine"))) +void foo_preemptible_stack_swap_machine(void) {} // CHECK: attributes #0 // CHECK: "interrupt"="SiFive-CLIC-stack-swap" @@ -77,8 +88,10 @@ __attribute__((interrupt("machine", "SiFive-CLIC-preemptible"))) void foo15(void __attribute__((interrupt("SiFive-CLIC-preemptible", "SiFive-CLIC-stack-swap"))) void foo16(void) {} // disabled-error {{RISC-V 'interrupt' attribute 'SiFive-CLIC-preemptible' requires extension 'XSfmclic'}} __attribute__((interrupt("SiFive-CLIC-stack-swap", "SiFive-CLIC-preemptible"))) void foo17(void) {} // disabled-error {{RISC-V 'interrupt' attribute 'SiFive-CLIC-stack-swap' requires extension 'XSfmclic'}} +__attribute__((interrupt("machine", "SiFive-CLIC-stack-swap", "SiFive-CLIC-preemptible"))) void foo18(void) {} // disabled-error {{requires extension 'XSfmclic'}} -__attribute__((interrupt("machine", "machine", "SiFive-CLIC-preemptible"))) void foo24(void) {} // both-error {{'interrupt' attribute takes no more than 2 arguments}} +__attribute__((interrupt("machine", "machine", "SiFive-CLIC-preemptible"))) void foo24(void) {} // both-error {{RISC-V 'interrupt' attribute contains invalid combination of interrupt types}} +__attribute__((interrupt("machine", "machine", "SiFive-CLIC-preemptible", "SiFive-CLIC-stack-swap"))) void foo25(void) {} // both-error {{'interrupt' attribute takes no more than 3 arguments}} __attribute__((interrupt("SiFive-CLIC-preemptible", "supervisor"))) void foo27(void) {} // both-error {{RISC-V 'interrupt' attribute contains invalid combination of interrupt types}} diff --git a/clang/test/Sema/riscv-interrupt-attr.c b/clang/test/Sema/riscv-interrupt-attr.c index f46723e892fb6..1bef80def6424 100644 --- a/clang/test/Sema/riscv-interrupt-attr.c +++ b/clang/test/Sema/riscv-interrupt-attr.c @@ -42,7 +42,9 @@ struct a test __attribute__((interrupt)); // expected-warning {{'interrupt' attr __attribute__((interrupt)) int foo3(void) {return 0;} // expected-warning {{RISC-V 'interrupt' attribute only applies to functions that have a 'void' return type}} __attribute__((interrupt())) void foo5(int a) {} // expected-warning {{RISC-V 'interrupt' attribute only applies to functions that have no parameters}} -__attribute__((interrupt("machine", "supervisor", "machine"))) void foo15(void) {} // expected-error {{'interrupt' attribute takes no more than 2 arguments}} +__attribute__((interrupt("machine", "supervisor", "machine"))) void foo15(void) {} // expected-error {{RISC-V 'interrupt' attribute contains invalid combination of interrupt types}} +__attribute__((interrupt("machine", "machine", "machine"))) void foo_three_machine_args(void) {} // expected-error {{RISC-V 'interrupt' attribute contains invalid combination of interrupt types}} +__attribute__((interrupt("machine", "machine", "machine", "machine"))) void foo_too_many_args(void) {} // expected-error {{'interrupt' attribute takes no more than 3 arguments}} __attribute__((interrupt(42))) void foo0(void) {} // expected-error {{expected string literal as argument of 'interrupt' attribute}} __attribute__((interrupt("machine", 1))) void foo2(void) {} // expected-error {{expected string literal as argument of 'interrupt' attribute}} `````````` </details> https://github.com/llvm/llvm-project/pull/216159 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
