https://github.com/TelGome updated https://github.com/llvm/llvm-project/pull/215779
>From 3a4f83d438d51f512b0f48095b0b76d438eb9346 Mon Sep 17 00:00:00 2001 From: Dongyan Chen <[email protected]> Date: Wed, 12 Aug 2026 09:00:24 +0000 Subject: [PATCH 1/4] [RISCV][P-ext] Support Packed Narrowing Clip Pair --- clang/include/clang/Basic/BuiltinsRISCV.td | 14 ++ clang/lib/CodeGen/TargetBuiltins/RISCV.cpp | 27 ++- clang/lib/Headers/riscv_packed_simd.h | 14 ++ clang/test/CodeGen/RISCV/rvp-intrinsics.c | 208 ++++++++++++++++++ .../riscv_packed_simd.c | 76 +++++++ llvm/include/llvm/IR/IntrinsicsRISCV.td | 8 + llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 97 ++++++++ llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 28 +++ llvm/test/CodeGen/RISCV/rvp-simd-32.ll | 103 +++++++++ llvm/test/CodeGen/RISCV/rvp-simd-64.ll | 99 +++++++++ 10 files changed, 673 insertions(+), 1 deletion(-) diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td index c7ee68415d001..b91b356d7a25d 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.td +++ b/clang/include/clang/Basic/BuiltinsRISCV.td @@ -309,6 +309,20 @@ def pzext_b_u16x4 : RISCVBuiltin<"_Vector<4, unsigned short>(_Vector<4, unsigned def pzext_h_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(_Vector<2, unsigned int>)">; +// Packed Narrowing Clip Pair (32-bit) +def pnclipp_i8x4 : RISCVBuiltin<"_Vector<4, signed char>(_Vector<2, short>, _Vector<2, short>)">; +def pnclipup_u8x4 : RISCVBuiltin<"_Vector<4, unsigned char>(_Vector<2, unsigned short>, _Vector<2, unsigned short>)">; +def pnclipp_i16x2 : RISCVBuiltin<"_Vector<2, short>(int, int)">; +def pnclipup_u16x2 : RISCVBuiltin<"_Vector<2, unsigned short>(unsigned int, unsigned int)">; + +// Packed Narrowing Clip Pair (64-bit) +def pnclipp_i8x8 : RISCVBuiltin<"_Vector<8, signed char>(_Vector<4, short>, _Vector<4, short>)">; +def pnclipup_u8x8 : RISCVBuiltin<"_Vector<8, unsigned char>(_Vector<4, unsigned short>, _Vector<4, unsigned short>)">; +def pnclipp_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<2, int>, _Vector<2, int>)">; +def pnclipup_u16x4 : RISCVBuiltin<"_Vector<4, unsigned short>(_Vector<2, unsigned int>, _Vector<2, unsigned int>)">; +def pnclipp_i32x2 : RISCVBuiltin<"_Vector<2, int>(int64_t, int64_t)">; +def pnclipup_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(uint64_t, uint64_t)">; + } // Features = "experimental-p" //===----------------------------------------------------------------------===// diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp index a97f11223e6ae..eb98b38974b21 100644 --- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp @@ -1463,7 +1463,18 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, case RISCV::BI__builtin_riscv_predsumu_u16x4_u32: case RISCV::BI__builtin_riscv_predsumu_u8x8_u64: case RISCV::BI__builtin_riscv_predsumu_u16x4_u64: - case RISCV::BI__builtin_riscv_predsumu_u32x2_u64: { + case RISCV::BI__builtin_riscv_predsumu_u32x2_u64: + // Packed Narrowing Clip Pair + case RISCV::BI__builtin_riscv_pnclipp_i8x4: + case RISCV::BI__builtin_riscv_pnclipp_i8x8: + case RISCV::BI__builtin_riscv_pnclipp_i16x2: + case RISCV::BI__builtin_riscv_pnclipp_i16x4: + case RISCV::BI__builtin_riscv_pnclipp_i32x2: + case RISCV::BI__builtin_riscv_pnclipup_u8x4: + case RISCV::BI__builtin_riscv_pnclipup_u8x8: + case RISCV::BI__builtin_riscv_pnclipup_u16x2: + case RISCV::BI__builtin_riscv_pnclipup_u16x4: + case RISCV::BI__builtin_riscv_pnclipup_u32x2: { switch (BuiltinID) { default: llvm_unreachable("unexpected builtin ID"); @@ -1485,6 +1496,20 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, case RISCV::BI__builtin_riscv_predsumu_u32x2_u64: ID = Intrinsic::riscv_predsumu; break; + case RISCV::BI__builtin_riscv_pnclipp_i8x4: + case RISCV::BI__builtin_riscv_pnclipp_i8x8: + case RISCV::BI__builtin_riscv_pnclipp_i16x2: + case RISCV::BI__builtin_riscv_pnclipp_i16x4: + case RISCV::BI__builtin_riscv_pnclipp_i32x2: + ID = Intrinsic::riscv_pnclipp; + break; + case RISCV::BI__builtin_riscv_pnclipup_u8x4: + case RISCV::BI__builtin_riscv_pnclipup_u8x8: + case RISCV::BI__builtin_riscv_pnclipup_u16x2: + case RISCV::BI__builtin_riscv_pnclipup_u16x4: + case RISCV::BI__builtin_riscv_pnclipup_u32x2: + ID = Intrinsic::riscv_pnclipup; + break; } IntrinsicTypes = {ResultType, Ops[0]->getType()}; diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h index efec0dd9568f3..491e219bec297 100644 --- a/clang/lib/Headers/riscv_packed_simd.h +++ b/clang/lib/Headers/riscv_packed_simd.h @@ -781,6 +781,20 @@ __packed_binary_builtin(pmulqr_i16x4, int16x4_t, __builtin_riscv_pmulqr_i16x4) __packed_binary_builtin(pmulq_i32x2, int32x2_t, __builtin_riscv_pmulq_i32x2) __packed_binary_builtin(pmulqr_i32x2, int32x2_t, __builtin_riscv_pmulqr_i32x2) +/* Packed Narrowing Clip Pair (32-bit) */ +__packed_binary_builtin_cast(pnclipp_i8x4, int16x2_t, int8x4_t, __builtin_riscv_pnclipp_i8x4) +__packed_binary_builtin_cast(pnclipup_u8x4, uint16x2_t, uint8x4_t, __builtin_riscv_pnclipup_u8x4) +__packed_binary_builtin_cast(pnclipp_i16x2, int, int16x2_t, __builtin_riscv_pnclipp_i16x2) +__packed_binary_builtin_cast(pnclipup_u16x2, unsigned int, uint16x2_t, __builtin_riscv_pnclipup_u16x2) + +/* Packed Narrowing Clip Pair (64-bit) */ +__packed_binary_builtin_cast(pnclipp_i8x8, int16x4_t, int8x8_t, __builtin_riscv_pnclipp_i8x8) +__packed_binary_builtin_cast(pnclipup_u8x8, uint16x4_t, uint8x8_t, __builtin_riscv_pnclipup_u8x8) +__packed_binary_builtin_cast(pnclipp_i16x4, int32x2_t, int16x4_t, __builtin_riscv_pnclipp_i16x4) +__packed_binary_builtin_cast(pnclipup_u16x4, uint32x2_t, uint16x4_t, __builtin_riscv_pnclipup_u16x4) +__packed_binary_builtin_cast(pnclipp_i32x2, int64_t, int32x2_t, __builtin_riscv_pnclipp_i32x2) +__packed_binary_builtin_cast(pnclipup_u32x2, uint64_t, uint32x2_t, __builtin_riscv_pnclipup_u32x2) + /* Reinterpret Casts, Packed <-> Scalar (32-bit) */ __packed_reinterpret(u8x4_u32, uint32_t, uint8x4_t) __packed_reinterpret(u16x2_u32, uint32_t, uint16x2_t) diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c index 97100deccb3d0..d6afc4d18cc6a 100644 --- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c +++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c @@ -9497,3 +9497,211 @@ int16x4_t test_pnziph_i16x4(int32x2_t rs1, int32x2_t rs2) { uint16x4_t test_pnziph_u16x4(uint32x2_t rs1, uint32x2_t rs2) { return __riscv_pnziph_u16x4(rs1, rs2); } + +/* Packed Narrowing Clip Pair (32-bit) */ + +// RV32-LABEL: define dso_local i32 @test_pnclipp_i8x4( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pnclipp.v4i8.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32 +// RV32-NEXT: ret i32 [[TMP3]] +// +// RV64-LABEL: define dso_local i32 @test_pnclipp_i8x4( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pnclipp.v4i8.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32 +// RV64-NEXT: ret i32 [[TMP3]] +// +int8x4_t test_pnclipp_i8x4(int16x2_t rs1, int16x2_t rs2) { + return __riscv_pnclipp_i8x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pnclipup_u8x4( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pnclipup.v4i8.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32 +// RV32-NEXT: ret i32 [[TMP3]] +// +// RV64-LABEL: define dso_local i32 @test_pnclipup_u8x4( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pnclipup.v4i8.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32 +// RV64-NEXT: ret i32 [[TMP3]] +// +uint8x4_t test_pnclipup_u8x4(uint16x2_t rs1, uint16x2_t rs2) { + return __riscv_pnclipup_u8x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pnclipp_i16x2( +// RV32-SAME: i32 noundef [[RS1:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.riscv.pnclipp.v2i16.i32(i32 [[RS1]], i32 [[RS2]]) +// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[TMP0]] to i32 +// RV32-NEXT: ret i32 [[TMP1]] +// +// RV64-LABEL: define dso_local i32 @test_pnclipp_i16x2( +// RV64-SAME: i32 noundef signext [[RS1:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.riscv.pnclipp.v2i16.i32(i32 [[RS1]], i32 [[RS2]]) +// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[TMP0]] to i32 +// RV64-NEXT: ret i32 [[TMP1]] +// +int16x2_t test_pnclipp_i16x2(int32_t rs1, int32_t rs2) { + return __riscv_pnclipp_i16x2(rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pnclipup_u16x2( +// RV32-SAME: i32 noundef [[RS1:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.riscv.pnclipup.v2i16.i32(i32 [[RS1]], i32 [[RS2]]) +// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[TMP0]] to i32 +// RV32-NEXT: ret i32 [[TMP1]] +// +// RV64-LABEL: define dso_local i32 @test_pnclipup_u16x2( +// RV64-SAME: i32 noundef signext [[RS1:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.riscv.pnclipup.v2i16.i32(i32 [[RS1]], i32 [[RS2]]) +// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[TMP0]] to i32 +// RV64-NEXT: ret i32 [[TMP1]] +// +uint16x2_t test_pnclipup_u16x2(uint32_t rs1, uint32_t rs2) { + return __riscv_pnclipup_u16x2(rs1, rs2); +} + +/* Packed Narrowing Clip Pair (64-bit) */ + +// RV32-LABEL: define dso_local i64 @test_pnclipp_i8x8( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pnclipp.v8i8.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) +// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64 +// RV32-NEXT: ret i64 [[TMP3]] +// +// RV64-LABEL: define dso_local i64 @test_pnclipp_i8x8( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pnclipp.v8i8.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) +// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64 +// RV64-NEXT: ret i64 [[TMP3]] +// +int8x8_t test_pnclipp_i8x8(int16x4_t rs1, int16x4_t rs2) { + return __riscv_pnclipp_i8x8(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pnclipup_u8x8( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pnclipup.v8i8.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) +// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64 +// RV32-NEXT: ret i64 [[TMP3]] +// +// RV64-LABEL: define dso_local i64 @test_pnclipup_u8x8( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pnclipup.v8i8.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) +// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64 +// RV64-NEXT: ret i64 [[TMP3]] +// +uint8x8_t test_pnclipup_u8x8(uint16x4_t rs1, uint16x4_t rs2) { + return __riscv_pnclipup_u8x8(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pnclipp_i16x4( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> +// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pnclipp.v4i16.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64 +// RV32-NEXT: ret i64 [[TMP3]] +// +// RV64-LABEL: define dso_local i64 @test_pnclipp_i16x4( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> +// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pnclipp.v4i16.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64 +// RV64-NEXT: ret i64 [[TMP3]] +// +int16x4_t test_pnclipp_i16x4(int32x2_t rs1, int32x2_t rs2) { + return __riscv_pnclipp_i16x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pnclipup_u16x4( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> +// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pnclipup.v4i16.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64 +// RV32-NEXT: ret i64 [[TMP3]] +// +// RV64-LABEL: define dso_local i64 @test_pnclipup_u16x4( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> +// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pnclipup.v4i16.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64 +// RV64-NEXT: ret i64 [[TMP3]] +// +uint16x4_t test_pnclipup_u16x4(uint32x2_t rs1, uint32x2_t rs2) { + return __riscv_pnclipup_u16x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pnclipp_i32x2( +// RV32-SAME: i64 noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64 [[RS1]], i64 [[RS2]]) +// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64 +// RV32-NEXT: ret i64 [[TMP1]] +// +// RV64-LABEL: define dso_local i64 @test_pnclipp_i32x2( +// RV64-SAME: i64 noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64 [[RS1]], i64 [[RS2]]) +// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64 +// RV64-NEXT: ret i64 [[TMP1]] +// +int32x2_t test_pnclipp_i32x2(int64_t rs1, int64_t rs2) { + return __riscv_pnclipp_i32x2(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pnclipup_u32x2( +// RV32-SAME: i64 noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64 [[RS1]], i64 [[RS2]]) +// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64 +// RV32-NEXT: ret i64 [[TMP1]] +// +// RV64-LABEL: define dso_local i64 @test_pnclipup_u32x2( +// RV64-SAME: i64 noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64 [[RS1]], i64 [[RS2]]) +// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64 +// RV64-NEXT: ret i64 [[TMP1]] +// +uint32x2_t test_pnclipup_u32x2(uint64_t rs1, uint64_t rs2) { + return __riscv_pnclipup_u32x2(rs1, rs2); +} diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c index 079ab22339780..eac091c66bba0 100644 --- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c +++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c @@ -3000,3 +3000,79 @@ uint16x2_t test_punzipe_u16x2(uint16x4_t a) { return __riscv_punzipe_u16x2(a); } // RV32: pncvth.h // RV64: pncvth.wh uint16x2_t test_punzipo_u16x2(uint16x4_t a) { return __riscv_punzipo_u16x2(a); } + +// CHECK-LABEL: test_pnclipp_i8x4: +// RV32: pnclipi.b +// RV64: pnclipp.b +int8x4_t test_pnclipp_i8x4(int16x2_t a, int16x2_t b) { + return __riscv_pnclipp_i8x4(a, b); +} + +// CHECK-LABEL: test_pnclipup_u8x4: +// RV32: pnclipiu.b +// RV64: pnclipup.b +uint8x4_t test_pnclipup_u8x4(uint16x2_t a, uint16x2_t b) { + return __riscv_pnclipup_u8x4(a, b); +} + +// CHECK-LABEL: test_pnclipp_i16x2: +// RV32: pnclipi.h +// RV64: pnclipp.h +int16x2_t test_pnclipp_i16x2(int32_t a, int32_t b) { + return __riscv_pnclipp_i16x2(a, b); +} + +// CHECK-LABEL: test_pnclipup_u16x2: +// RV32: pnclipiu.h +// RV64: pnclipup.h +uint16x2_t test_pnclipup_u16x2(uint32_t a, uint32_t b) { + return __riscv_pnclipup_u16x2(a, b); +} + +// CHECK-LABEL: test_pnclipp_i8x8: +// RV32: pnclipi.b +// RV32: pnclipi.b +// RV64: pnclipp.b +int8x8_t test_pnclipp_i8x8(int16x4_t a, int16x4_t b) { + return __riscv_pnclipp_i8x8(a, b); +} + +// CHECK-LABEL: test_pnclipup_u8x8: +// RV32: pnclipiu.b +// RV32: pnclipiu.b +// RV64: pnclipup.b +uint8x8_t test_pnclipup_u8x8(uint16x4_t a, uint16x4_t b) { + return __riscv_pnclipup_u8x8(a, b); +} + +// CHECK-LABEL: test_pnclipp_i16x4: +// RV32: pnclipi.h +// RV32: pnclipi.h +// RV64: pnclipp.h +int16x4_t test_pnclipp_i16x4(int32x2_t a, int32x2_t b) { + return __riscv_pnclipp_i16x4(a, b); +} + +// CHECK-LABEL: test_pnclipup_u16x4: +// RV32: pnclipiu.h +// RV32: pnclipiu.h +// RV64: pnclipup.h +uint16x4_t test_pnclipup_u16x4(uint32x2_t a, uint32x2_t b) { + return __riscv_pnclipup_u16x4(a, b); +} + +// CHECK-LABEL: test_pnclipp_i32x2: +// RV32: nclipi +// RV32: nclipi +// RV64: pnclipp.w +int32x2_t test_pnclipp_i32x2(int64_t a, int64_t b) { + return __riscv_pnclipp_i32x2(a, b); +} + +// CHECK-LABEL: test_pnclipup_u32x2: +// RV32: nclipiu +// RV32: nclipiu +// RV64: pnclipup.w +uint32x2_t test_pnclipup_u32x2(uint64_t a, uint64_t b) { + return __riscv_pnclipup_u32x2(a, b); +} diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index 517d0e51ec406..d5bd6243bd1a6 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -2134,6 +2134,14 @@ class RVPBinaryIntrinsic [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]>; def int_riscv_psabs : RVPUnaryIntrinsic; + + // Packed Narrowing Clip Pair + class RVPNarrowingClipIntrinsic + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], + [llvm_any_ty, LLVMMatchType<1>], + [IntrNoMem, IntrSpeculatable]>; + def int_riscv_pnclipp : RVPNarrowingClipIntrinsic; + def int_riscv_pnclipup : RVPNarrowingClipIntrinsic; } // TargetPrefix = "riscv" //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 9affe23298969..1cd48e4a1ec61 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -12302,6 +12302,77 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, return DAG.getNode(Opc, DL, Op.getValueType(), Op.getOperand(1), Op.getOperand(2)); } + case Intrinsic::riscv_pnclipp: + case Intrinsic::riscv_pnclipup: { + EVT VT = Op.getValueType(); + SDValue Rs1 = Op.getOperand(1); + SDValue Rs2 = Op.getOperand(2); + unsigned Opc = IntNo == Intrinsic::riscv_pnclipp ? RISCVISD::PNCLIPP + : RISCVISD::PNCLIPUP; + + if (Subtarget.is64Bit()) { + if (VT == MVT::v2i32 && !Rs1.getValueType().isVector()) { + unsigned WOpc = IntNo == Intrinsic::riscv_pnclipp + ? RISCVISD::PNCLIPP_W + : RISCVISD::PNCLIPUP_W; + return DAG.getNode(WOpc, DL, VT, Rs1, Rs2); + } + return DAG.getNode(Opc, DL, VT, Rs1, Rs2); + } + + auto BuildPair = [&](SDValue Lo, SDValue Hi, MVT PairVT) { + return DAG.getNode(RISCVISD::BuildPairGPRVec, DL, PairVT, Lo, Hi); + }; + + MVT XLenVT = Subtarget.getXLenVT(); + if (VT == MVT::v4i8) { + SDValue Pair = BuildPair(Rs1, Rs2, MVT::v4i16); + SDVTList VTs = DAG.getVTList(MVT::v4i8); + unsigned ClipOpc = IntNo == Intrinsic::riscv_pnclipp ? RISCV::PNCLIPI_B + : RISCV::PNCLIPIU_B; + SDValue Ops[] = {Pair, DAG.getTargetConstant(0, DL, MVT::i32)}; + return SDValue(DAG.getMachineNode(ClipOpc, DL, VTs, Ops), 0); + } + if (VT == MVT::v2i16) { + unsigned HOpc = IntNo == Intrinsic::riscv_pnclipp ? RISCV::PNCLIPI_H + : RISCV::PNCLIPIU_H; + SDVTList VTs = DAG.getVTList(MVT::v2i16); + SDValue Pair = BuildPair(Rs1, Rs2, MVT::v2i32); + SDValue Ops[] = {Pair, DAG.getTargetConstant(0, DL, MVT::i32)}; + return SDValue(DAG.getMachineNode(HOpc, DL, VTs, Ops), 0); + } + if (VT == MVT::v2i32) { + unsigned NOpc = + IntNo == Intrinsic::riscv_pnclipp ? RISCV::NCLIPI : RISCV::NCLIPIU; + SDVTList VTs = DAG.getVTList(XLenVT); + SDValue Zero = DAG.getTargetConstant(0, DL, MVT::i32); + auto BuildPairFromI64 = [&](SDValue I64) { + SDValue Vec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, I64); + SDValue Lo = DAG.getExtractVectorElt(DL, XLenVT, Vec, 0); + SDValue Hi = DAG.getExtractVectorElt(DL, XLenVT, Vec, 1); + return DAG.getNode(RISCVISD::BuildGPRPair, DL, MVT::Untyped, Lo, Hi); + }; + SDValue Pair1 = BuildPairFromI64(Rs1); + SDValue Pair2 = BuildPairFromI64(Rs2); + SDValue Lo = SDValue(DAG.getMachineNode(NOpc, DL, VTs, {Pair1, Zero}), 0); + SDValue Hi = SDValue(DAG.getMachineNode(NOpc, DL, VTs, {Pair2, Zero}), 0); + return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Lo, Hi); + } + if (VT == MVT::v8i8 || VT == MVT::v4i16) { + unsigned HOpc = + IntNo == Intrinsic::riscv_pnclipp + ? (VT == MVT::v8i8 ? RISCV::PNCLIPI_B : RISCV::PNCLIPI_H) + : (VT == MVT::v8i8 ? RISCV::PNCLIPIU_B : RISCV::PNCLIPIU_H); + MVT HalfVT = VT == MVT::v8i8 ? MVT::v4i8 : MVT::v2i16; + SDVTList VTs = DAG.getVTList(HalfVT); + SDValue Zero = DAG.getTargetConstant(0, DL, MVT::i32); + SDValue Lo = SDValue(DAG.getMachineNode(HOpc, DL, VTs, {Rs1, Zero}), 0); + SDValue Hi = SDValue(DAG.getMachineNode(HOpc, DL, VTs, {Rs2, Zero}), 0); + return DAG.getNode(RISCVISD::BuildPairGPRVec, DL, VT, Lo, Hi); + } + + return DAG.getNode(Opc, DL, VT, Rs1, Rs2); + } case Intrinsic::riscv_pmulq: case Intrinsic::riscv_pmulqr: { unsigned Opc; @@ -16595,6 +16666,32 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, DAG.getVectorIdxConstant(0, DL))); return; } + case Intrinsic::riscv_pnclipp: + case Intrinsic::riscv_pnclipup: { + EVT VT = N->getValueType(0); + if (!Subtarget.is64Bit() || (VT != MVT::v4i8 && VT != MVT::v2i16)) + return; + unsigned Opc = IntNo == Intrinsic::riscv_pnclipp ? RISCVISD::PNCLIPP + : RISCVISD::PNCLIPUP; + SDValue Src1 = N->getOperand(1); + SDValue Src2 = N->getOperand(2); + if (VT == MVT::v4i8) { + MVT WideSrcVT = MVT::v4i16; + SDValue Packed = + DAG.getNode(ISD::CONCAT_VECTORS, DL, WideSrcVT, {Src1, Src2}); + SDValue Res = DAG.getNode(Opc, DL, MVT::v8i8, {Packed, Packed}); + Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res, + DAG.getVectorIdxConstant(0, DL))); + } else { + MVT WideSrcVT = MVT::v2i32; + SDValue Packed = + DAG.getNode(ISD::BUILD_VECTOR, DL, WideSrcVT, {Src1, Src2}); + SDValue Res = DAG.getNode(Opc, DL, MVT::v4i16, {Packed, Packed}); + Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res, + DAG.getVectorIdxConstant(0, DL))); + } + return; + } case Intrinsic::riscv_pssha: case Intrinsic::riscv_psshar: case Intrinsic::riscv_psshl: diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td index b5cd4c1aad196..70686f51f4156 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td @@ -1908,6 +1908,20 @@ def SDT_RISCVPackedNarrowingShift SDTCisVT<2, XLenVT>]>; def riscv_pnsrl : RVSDNode<"PNSRL", SDT_RISCVPackedNarrowingShift>; +// Packed narrowing clip pair. +def SDT_RISCVPackedNarrowingClip + : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisSameAs<1, 2>]>; +def riscv_pnclipp : RVSDNode<"PNCLIPP", SDT_RISCVPackedNarrowingClip>; +def riscv_pnclipup : RVSDNode<"PNCLIPUP", SDT_RISCVPackedNarrowingClip>; + +def SDT_RISCVPackedNarrowingClipW + : SDTypeProfile<1, 2, [SDTCisVT<0, v2i32>, + SDTCisVT<1, XLenVT>, + SDTCisSameAs<1, 2>]>; +def riscv_pnclipp_w : RVSDNode<"PNCLIPP_W", SDT_RISCVPackedNarrowingClipW>; +def riscv_pnclipup_w : RVSDNode<"PNCLIPUP_W", SDT_RISCVPackedNarrowingClipW>; + // The immediate for these is the number of trailing ones in the max value. def riscv_sati : RVSDNode<"SATI", SDTIntBinOp>; def riscv_usati : RVSDNode<"USATI", SDTIntBinOp>; @@ -2639,6 +2653,20 @@ let append Predicates = [IsRV64] in { def : PatGpr<bitreverse, REV_RV64>; + // Packed narrowing clip pair. + def : Pat<(v8i8 (riscv_pnclipp (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))), + (PNCLIPP_B GPR:$rs1, GPR:$rs2)>; + def : Pat<(v4i16 (riscv_pnclipp (v2i32 GPR:$rs1), (v2i32 GPR:$rs2))), + (PNCLIPP_H GPR:$rs1, GPR:$rs2)>; + def : Pat<(v8i8 (riscv_pnclipup (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))), + (PNCLIPUP_B GPR:$rs1, GPR:$rs2)>; + def : Pat<(v4i16 (riscv_pnclipup (v2i32 GPR:$rs1), (v2i32 GPR:$rs2))), + (PNCLIPUP_H GPR:$rs1, GPR:$rs2)>; + def : Pat<(v2i32 (riscv_pnclipp_w GPR:$rs1, GPR:$rs2)), + (PNCLIPP_W GPR:$rs1, GPR:$rs2)>; + def : Pat<(v2i32 (riscv_pnclipup_w GPR:$rs1, GPR:$rs2)), + (PNCLIPUP_W GPR:$rs1, GPR:$rs2)>; + def : Pat<(XLenVT (riscv_sati GPR:$rs1, timm:$imm)), (SATI_RV64 GPR:$rs1, (IncImm timm:$imm))>; def : Pat<(XLenVT (riscv_usati GPR:$rs1, timm:$imm)), diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll index 26213eb659e4d..58ce754c73c24 100644 --- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll +++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll @@ -2883,3 +2883,106 @@ define <2 x i16> @test_pmulqr_v2i16(<2 x i16> %a, <2 x i16> %b) { %res = call <2 x i16> @llvm.riscv.pmulqr.v2i16(<2 x i16> %a, <2 x i16> %b) ret <2 x i16> %res } + +define <4 x i8> @test_pnclipp_v4i8(<2 x i16> %a, <2 x i16> %b) { +; RV32-LABEL: test_pnclipp_v4i8: +; RV32: # %bb.0: +; RV32-NEXT: pnclipi.b a0, a0, 0 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipp_v4i8: +; RV64: # %bb.0: +; RV64-NEXT: srli a2, a1, 16 +; RV64-NEXT: srli a3, a0, 16 +; RV64-NEXT: ppaire.h a1, a1, a2 +; RV64-NEXT: ppaire.h a0, a0, a3 +; RV64-NEXT: pack a0, a0, a1 +; RV64-NEXT: pnclipp.b a0, a0, a0 +; RV64-NEXT: ret + %r = call <4 x i8> @llvm.riscv.pnclipp.v4i8.v2i16(<2 x i16> %a, <2 x i16> %b) + ret <4 x i8> %r +} + +define <4 x i8> @test_pnclipup_v4i8(<2 x i16> %a, <2 x i16> %b) { +; RV32-LABEL: test_pnclipup_v4i8: +; RV32: # %bb.0: +; RV32-NEXT: pnclipiu.b a0, a0, 0 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipup_v4i8: +; RV64: # %bb.0: +; RV64-NEXT: srli a2, a1, 16 +; RV64-NEXT: srli a3, a0, 16 +; RV64-NEXT: ppaire.h a1, a1, a2 +; RV64-NEXT: ppaire.h a0, a0, a3 +; RV64-NEXT: pack a0, a0, a1 +; RV64-NEXT: pnclipup.b a0, a0, a0 +; RV64-NEXT: ret + %r = call <4 x i8> @llvm.riscv.pnclipup.v4i8.v2i16(<2 x i16> %a, <2 x i16> %b) + ret <4 x i8> %r +} + +define <2 x i16> @test_pnclipp_v2i16(i32 %a, i32 %b) { +; RV32-LABEL: test_pnclipp_v2i16: +; RV32: # %bb.0: +; RV32-NEXT: pnclipi.h a0, a0, 0 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipp_v2i16: +; RV64: # %bb.0: +; RV64-NEXT: pack a0, a0, a1 +; RV64-NEXT: pnclipp.h a0, a0, a0 +; RV64-NEXT: ret + %r = call <2 x i16> @llvm.riscv.pnclipp.v2i16.i32(i32 %a, i32 %b) + ret <2 x i16> %r +} + +define <2 x i16> @test_pnclipup_v2i16(i32 %a, i32 %b) { +; RV32-LABEL: test_pnclipup_v2i16: +; RV32: # %bb.0: +; RV32-NEXT: pnclipiu.h a0, a0, 0 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipup_v2i16: +; RV64: # %bb.0: +; RV64-NEXT: pack a0, a0, a1 +; RV64-NEXT: pnclipup.h a0, a0, a0 +; RV64-NEXT: ret + %r = call <2 x i16> @llvm.riscv.pnclipup.v2i16.i32(i32 %a, i32 %b) + ret <2 x i16> %r +} + +declare <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64, i64) +declare <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64, i64) + +define i64 @test_pnclipp_v2i32_i64(i64 %a, i64 %b) { +; RV32-LABEL: test_pnclipp_v2i32_i64: +; RV32: # %bb.0: +; RV32-NEXT: nclipi a0, a0, 0 +; RV32-NEXT: nclipi a1, a2, 0 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipp_v2i32_i64: +; RV64: # %bb.0: +; RV64-NEXT: pnclipp.w a0, a0, a1 +; RV64-NEXT: ret + %r = call <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64 %a, i64 %b) + %s = bitcast <2 x i32> %r to i64 + ret i64 %s +} + +define i64 @test_pnclipup_v2i32_i64(i64 %a, i64 %b) { +; RV32-LABEL: test_pnclipup_v2i32_i64: +; RV32: # %bb.0: +; RV32-NEXT: nclipiu a0, a0, 0 +; RV32-NEXT: nclipiu a1, a2, 0 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipup_v2i32_i64: +; RV64: # %bb.0: +; RV64-NEXT: pnclipup.w a0, a0, a1 +; RV64-NEXT: ret + %r = call <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64 %a, i64 %b) + %s = bitcast <2 x i32> %r to i64 + ret i64 %s +} diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll index 490634197f29b..177c2ab488104 100644 --- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll +++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll @@ -6536,3 +6536,102 @@ define <8 x i8> @test_ppair_v2_used_twice_v8i8(<8 x i8> %a, <8 x i8> %b) { %res = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> ret <8 x i8> %res } + +define <8 x i8> @test_pnclipp_v8i8(<4 x i16> %a, <4 x i16> %b) { +; RV32-LABEL: test_pnclipp_v8i8: +; RV32: # %bb.0: +; RV32-NEXT: pnclipi.b a2, a2, 0 +; RV32-NEXT: pnclipi.b a0, a0, 0 +; RV32-NEXT: mv a1, a2 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipp_v8i8: +; RV64: # %bb.0: +; RV64-NEXT: pnclipp.b a0, a0, a1 +; RV64-NEXT: ret + %r = call <8 x i8> @llvm.riscv.pnclipp.v8i8.v4i16(<4 x i16> %a, <4 x i16> %b) + ret <8 x i8> %r +} + +define <8 x i8> @test_pnclipup_v8i8(<4 x i16> %a, <4 x i16> %b) { +; RV32-LABEL: test_pnclipup_v8i8: +; RV32: # %bb.0: +; RV32-NEXT: pnclipiu.b a2, a2, 0 +; RV32-NEXT: pnclipiu.b a0, a0, 0 +; RV32-NEXT: mv a1, a2 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipup_v8i8: +; RV64: # %bb.0: +; RV64-NEXT: pnclipup.b a0, a0, a1 +; RV64-NEXT: ret + %r = call <8 x i8> @llvm.riscv.pnclipup.v8i8.v4i16(<4 x i16> %a, <4 x i16> %b) + ret <8 x i8> %r +} + +define <4 x i16> @test_pnclipp_v4i16(<2 x i32> %a, <2 x i32> %b) { +; RV32-LABEL: test_pnclipp_v4i16: +; RV32: # %bb.0: +; RV32-NEXT: pnclipi.h a2, a2, 0 +; RV32-NEXT: pnclipi.h a0, a0, 0 +; RV32-NEXT: mv a1, a2 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipp_v4i16: +; RV64: # %bb.0: +; RV64-NEXT: pnclipp.h a0, a0, a1 +; RV64-NEXT: ret + %r = call <4 x i16> @llvm.riscv.pnclipp.v4i16.v2i32(<2 x i32> %a, <2 x i32> %b) + ret <4 x i16> %r +} + +define <4 x i16> @test_pnclipup_v4i16(<2 x i32> %a, <2 x i32> %b) { +; RV32-LABEL: test_pnclipup_v4i16: +; RV32: # %bb.0: +; RV32-NEXT: pnclipiu.h a2, a2, 0 +; RV32-NEXT: pnclipiu.h a0, a0, 0 +; RV32-NEXT: mv a1, a2 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipup_v4i16: +; RV64: # %bb.0: +; RV64-NEXT: pnclipup.h a0, a0, a1 +; RV64-NEXT: ret + %r = call <4 x i16> @llvm.riscv.pnclipup.v4i16.v2i32(<2 x i32> %a, <2 x i32> %b) + ret <4 x i16> %r +} + +declare <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64, i64) +declare <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64, i64) + +define i64 @test_pnclipp_v2i32(i64 %a, i64 %b) { +; RV32-LABEL: test_pnclipp_v2i32: +; RV32: # %bb.0: +; RV32-NEXT: nclipi a0, a0, 0 +; RV32-NEXT: nclipi a1, a2, 0 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipp_v2i32: +; RV64: # %bb.0: +; RV64-NEXT: pnclipp.w a0, a0, a1 +; RV64-NEXT: ret + %r = call <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64 %a, i64 %b) + %s = bitcast <2 x i32> %r to i64 + ret i64 %s +} + +define i64 @test_pnclipup_v2i32(i64 %a, i64 %b) { +; RV32-LABEL: test_pnclipup_v2i32: +; RV32: # %bb.0: +; RV32-NEXT: nclipiu a0, a0, 0 +; RV32-NEXT: nclipiu a1, a2, 0 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipup_v2i32: +; RV64: # %bb.0: +; RV64-NEXT: pnclipup.w a0, a0, a1 +; RV64-NEXT: ret + %r = call <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64 %a, i64 %b) + %s = bitcast <2 x i32> %r to i64 + ret i64 %s +} >From 8f3bd494bdfb9f18dd25b80454bff6efb17398e1 Mon Sep 17 00:00:00 2001 From: Dongyan Chen <[email protected]> Date: Thu, 13 Aug 2026 04:04:05 +0000 Subject: [PATCH 2/4] [RISCV][P-ext] Fix packed narrowing clip immediate lowering --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 67 +++++++++------------ llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 31 ++++++++++ 2 files changed, 58 insertions(+), 40 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 1cd48e4a1ec61..2047df3319d42 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -12304,70 +12304,57 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, } case Intrinsic::riscv_pnclipp: case Intrinsic::riscv_pnclipup: { + bool IsSigned = IntNo == Intrinsic::riscv_pnclipp; EVT VT = Op.getValueType(); SDValue Rs1 = Op.getOperand(1); SDValue Rs2 = Op.getOperand(2); - unsigned Opc = IntNo == Intrinsic::riscv_pnclipp ? RISCVISD::PNCLIPP - : RISCVISD::PNCLIPUP; + unsigned Opc = IsSigned ? RISCVISD::PNCLIPP : RISCVISD::PNCLIPUP; if (Subtarget.is64Bit()) { if (VT == MVT::v2i32 && !Rs1.getValueType().isVector()) { - unsigned WOpc = IntNo == Intrinsic::riscv_pnclipp - ? RISCVISD::PNCLIPP_W - : RISCVISD::PNCLIPUP_W; + unsigned WOpc = IsSigned ? RISCVISD::PNCLIPP_W : RISCVISD::PNCLIPUP_W; return DAG.getNode(WOpc, DL, VT, Rs1, Rs2); } return DAG.getNode(Opc, DL, VT, Rs1, Rs2); } - auto BuildPair = [&](SDValue Lo, SDValue Hi, MVT PairVT) { - return DAG.getNode(RISCVISD::BuildPairGPRVec, DL, PairVT, Lo, Hi); - }; - MVT XLenVT = Subtarget.getXLenVT(); if (VT == MVT::v4i8) { - SDValue Pair = BuildPair(Rs1, Rs2, MVT::v4i16); - SDVTList VTs = DAG.getVTList(MVT::v4i8); - unsigned ClipOpc = IntNo == Intrinsic::riscv_pnclipp ? RISCV::PNCLIPI_B - : RISCV::PNCLIPIU_B; - SDValue Ops[] = {Pair, DAG.getTargetConstant(0, DL, MVT::i32)}; - return SDValue(DAG.getMachineNode(ClipOpc, DL, VTs, Ops), 0); + unsigned ClipOpc = IsSigned ? RISCVISD::PNCLIPP_I : RISCVISD::PNCLIPUP_I; + SDValue Pair = + DAG.getNode(RISCVISD::BuildPairGPRVec, DL, MVT::v4i16, Rs1, Rs2); + return DAG.getNode(ClipOpc, DL, MVT::v4i8, Pair, + DAG.getConstant(0, DL, XLenVT)); } if (VT == MVT::v2i16) { - unsigned HOpc = IntNo == Intrinsic::riscv_pnclipp ? RISCV::PNCLIPI_H - : RISCV::PNCLIPIU_H; - SDVTList VTs = DAG.getVTList(MVT::v2i16); - SDValue Pair = BuildPair(Rs1, Rs2, MVT::v2i32); - SDValue Ops[] = {Pair, DAG.getTargetConstant(0, DL, MVT::i32)}; - return SDValue(DAG.getMachineNode(HOpc, DL, VTs, Ops), 0); + unsigned HOpc = IsSigned ? RISCVISD::PNCLIPP_I : RISCVISD::PNCLIPUP_I; + SDValue Pair = + DAG.getNode(RISCVISD::BuildPairGPRVec, DL, MVT::v2i32, Rs1, Rs2); + return DAG.getNode(HOpc, DL, MVT::v2i16, Pair, + DAG.getConstant(0, DL, XLenVT)); } if (VT == MVT::v2i32) { - unsigned NOpc = - IntNo == Intrinsic::riscv_pnclipp ? RISCV::NCLIPI : RISCV::NCLIPIU; - SDVTList VTs = DAG.getVTList(XLenVT); - SDValue Zero = DAG.getTargetConstant(0, DL, MVT::i32); + unsigned NOpc = IsSigned ? RISCVISD::NCLIPP_I : RISCVISD::NCLIPUP_I; + SDValue Zero = DAG.getConstant(0, DL, XLenVT); auto BuildPairFromI64 = [&](SDValue I64) { - SDValue Vec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, I64); - SDValue Lo = DAG.getExtractVectorElt(DL, XLenVT, Vec, 0); - SDValue Hi = DAG.getExtractVectorElt(DL, XLenVT, Vec, 1); + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, XLenVT, I64, + DAG.getConstant(0, DL, MVT::i32)); + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, XLenVT, I64, + DAG.getConstant(1, DL, MVT::i32)); return DAG.getNode(RISCVISD::BuildGPRPair, DL, MVT::Untyped, Lo, Hi); }; SDValue Pair1 = BuildPairFromI64(Rs1); SDValue Pair2 = BuildPairFromI64(Rs2); - SDValue Lo = SDValue(DAG.getMachineNode(NOpc, DL, VTs, {Pair1, Zero}), 0); - SDValue Hi = SDValue(DAG.getMachineNode(NOpc, DL, VTs, {Pair2, Zero}), 0); + SDValue Lo = DAG.getNode(NOpc, DL, XLenVT, Pair1, Zero); + SDValue Hi = DAG.getNode(NOpc, DL, XLenVT, Pair2, Zero); return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Lo, Hi); } if (VT == MVT::v8i8 || VT == MVT::v4i16) { - unsigned HOpc = - IntNo == Intrinsic::riscv_pnclipp - ? (VT == MVT::v8i8 ? RISCV::PNCLIPI_B : RISCV::PNCLIPI_H) - : (VT == MVT::v8i8 ? RISCV::PNCLIPIU_B : RISCV::PNCLIPIU_H); + unsigned HOpc = IsSigned ? RISCVISD::PNCLIPP_I : RISCVISD::PNCLIPUP_I; MVT HalfVT = VT == MVT::v8i8 ? MVT::v4i8 : MVT::v2i16; - SDVTList VTs = DAG.getVTList(HalfVT); - SDValue Zero = DAG.getTargetConstant(0, DL, MVT::i32); - SDValue Lo = SDValue(DAG.getMachineNode(HOpc, DL, VTs, {Rs1, Zero}), 0); - SDValue Hi = SDValue(DAG.getMachineNode(HOpc, DL, VTs, {Rs2, Zero}), 0); + SDValue Zero = DAG.getConstant(0, DL, XLenVT); + SDValue Lo = DAG.getNode(HOpc, DL, HalfVT, Rs1, Zero); + SDValue Hi = DAG.getNode(HOpc, DL, HalfVT, Rs2, Zero); return DAG.getNode(RISCVISD::BuildPairGPRVec, DL, VT, Lo, Hi); } @@ -16668,11 +16655,11 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, } case Intrinsic::riscv_pnclipp: case Intrinsic::riscv_pnclipup: { + bool IsSigned = IntNo == Intrinsic::riscv_pnclipp; EVT VT = N->getValueType(0); if (!Subtarget.is64Bit() || (VT != MVT::v4i8 && VT != MVT::v2i16)) return; - unsigned Opc = IntNo == Intrinsic::riscv_pnclipp ? RISCVISD::PNCLIPP - : RISCVISD::PNCLIPUP; + unsigned Opc = IsSigned ? RISCVISD::PNCLIPP : RISCVISD::PNCLIPUP; SDValue Src1 = N->getOperand(1); SDValue Src2 = N->getOperand(2); if (VT == MVT::v4i8) { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td index 70686f51f4156..c7aca498d3ac8 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td @@ -1915,6 +1915,18 @@ def SDT_RISCVPackedNarrowingClip def riscv_pnclipp : RVSDNode<"PNCLIPP", SDT_RISCVPackedNarrowingClip>; def riscv_pnclipup : RVSDNode<"PNCLIPUP", SDT_RISCVPackedNarrowingClip>; +def SDT_RISCVPackedNarrowingClipI + : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisVT<2, XLenVT>]>; +def riscv_pnclipp_i : RVSDNode<"PNCLIPP_I", SDT_RISCVPackedNarrowingClipI>; +def riscv_pnclipup_i : RVSDNode<"PNCLIPUP_I", SDT_RISCVPackedNarrowingClipI>; + +def SDT_RISCVNarrowingClipI + : SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>, SDTCisVT<1, GPRPairVT>, + SDTCisVT<2, XLenVT>]>; +def riscv_nclipp_i : RVSDNode<"NCLIPP_I", SDT_RISCVNarrowingClipI>; +def riscv_nclipup_i : RVSDNode<"NCLIPUP_I", SDT_RISCVNarrowingClipI>; + def SDT_RISCVPackedNarrowingClipW : SDTypeProfile<1, 2, [SDTCisVT<0, v2i32>, SDTCisVT<1, XLenVT>, @@ -2645,6 +2657,25 @@ let append Predicates = [IsRV32] in { (EXTRACT_SUBREG GPRPair:$vec, sub_gpr_even)>; def : Pat<(v4i8 (extract_subvector (v8i8 GPRPair:$vec), (i32 4))), (EXTRACT_SUBREG GPRPair:$vec, sub_gpr_odd)>; + + // Packed narrowing clip by immediate (RV32). shift=0 == plain clip. + def : Pat<(v4i8 (riscv_pnclipp_i (v4i16 GPRPair:$rs1), uimm4:$imm)), + (PNCLIPI_B GPRPair:$rs1, uimm4:$imm)>; + def : Pat<(v4i8 (riscv_pnclipup_i (v4i16 GPRPair:$rs1), uimm4:$imm)), + (PNCLIPIU_B GPRPair:$rs1, uimm4:$imm)>; + def : Pat<(v2i16 (riscv_pnclipp_i (v2i32 GPRPair:$rs1), uimm5:$imm)), + (PNCLIPI_H GPRPair:$rs1, uimm5:$imm)>; + def : Pat<(v2i16 (riscv_pnclipup_i (v2i32 GPRPair:$rs1), uimm5:$imm)), + (PNCLIPIU_H GPRPair:$rs1, uimm5:$imm)>; + + def : Pat<(XLenVT (riscv_nclipp_i + (riscv_build_gpr_pair GPR:$lo, GPR:$hi), + uimm6:$imm)), + (NCLIPI (BuildGPRPair GPR:$lo, GPR:$hi), uimm6:$imm)>; + def : Pat<(XLenVT (riscv_nclipup_i + (riscv_build_gpr_pair GPR:$lo, GPR:$hi), + uimm6:$imm)), + (NCLIPIU (BuildGPRPair GPR:$lo, GPR:$hi), uimm6:$imm)>; } // append Predicates = [IsRV32] let append Predicates = [IsRV64] in { >From db415cbb1f3bbf162407e58cbbe8fb420f7eceb2 Mon Sep 17 00:00:00 2001 From: Dongyan Chen <[email protected]> Date: Thu, 13 Aug 2026 09:20:50 +0000 Subject: [PATCH 3/4] [RISCV][P-ext] Resolve comment --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 57 ++++++++------------- llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 48 ++++++++--------- 2 files changed, 42 insertions(+), 63 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 2047df3319d42..f708f7ee32d0d 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -12319,46 +12319,36 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, } MVT XLenVT = Subtarget.getXLenVT(); + auto ToXLen = [&](SDValue V) { return DAG.getBitcast(XLenVT, V); }; + SDValue Shift = DAG.getTargetConstant(0, DL, XLenVT); if (VT == MVT::v4i8) { - unsigned ClipOpc = IsSigned ? RISCVISD::PNCLIPP_I : RISCVISD::PNCLIPUP_I; - SDValue Pair = - DAG.getNode(RISCVISD::BuildPairGPRVec, DL, MVT::v4i16, Rs1, Rs2); - return DAG.getNode(ClipOpc, DL, MVT::v4i8, Pair, - DAG.getConstant(0, DL, XLenVT)); + unsigned ClipOpc = IsSigned ? RISCVISD::PNCLIP : RISCVISD::PNCLIPU; + SDValue Pair = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i16, Rs1, Rs2); + return DAG.getNode(ClipOpc, DL, VT, Pair, Shift); } if (VT == MVT::v2i16) { - unsigned HOpc = IsSigned ? RISCVISD::PNCLIPP_I : RISCVISD::PNCLIPUP_I; - SDValue Pair = - DAG.getNode(RISCVISD::BuildPairGPRVec, DL, MVT::v2i32, Rs1, Rs2); - return DAG.getNode(HOpc, DL, MVT::v2i16, Pair, - DAG.getConstant(0, DL, XLenVT)); + unsigned ClipOpc = IsSigned ? RISCVISD::PNCLIP : RISCVISD::PNCLIPU; + SDValue Pair = DAG.getNode(RISCVISD::BuildPairGPRVec, DL, MVT::v2i32, + ToXLen(Rs1), ToXLen(Rs2)); + return DAG.getNode(ClipOpc, DL, VT, Pair, Shift); } if (VT == MVT::v2i32) { - unsigned NOpc = IsSigned ? RISCVISD::NCLIPP_I : RISCVISD::NCLIPUP_I; - SDValue Zero = DAG.getConstant(0, DL, XLenVT); - auto BuildPairFromI64 = [&](SDValue I64) { - SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, XLenVT, I64, - DAG.getConstant(0, DL, MVT::i32)); - SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, XLenVT, I64, - DAG.getConstant(1, DL, MVT::i32)); - return DAG.getNode(RISCVISD::BuildGPRPair, DL, MVT::Untyped, Lo, Hi); - }; - SDValue Pair1 = BuildPairFromI64(Rs1); - SDValue Pair2 = BuildPairFromI64(Rs2); - SDValue Lo = DAG.getNode(NOpc, DL, XLenVT, Pair1, Zero); - SDValue Hi = DAG.getNode(NOpc, DL, XLenVT, Pair2, Zero); + unsigned ClipOpc = IsSigned ? RISCVISD::NCLIP : RISCVISD::NCLIPU; + auto [Rs1Lo, Rs1Hi] = DAG.SplitScalar(Rs1, DL, XLenVT, XLenVT); + auto [Rs2Lo, Rs2Hi] = DAG.SplitScalar(Rs2, DL, XLenVT, XLenVT); + SDValue Lo = DAG.getNode(ClipOpc, DL, XLenVT, Rs1Lo, Rs1Hi, Shift); + SDValue Hi = DAG.getNode(ClipOpc, DL, XLenVT, Rs2Lo, Rs2Hi, Shift); return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Lo, Hi); } if (VT == MVT::v8i8 || VT == MVT::v4i16) { - unsigned HOpc = IsSigned ? RISCVISD::PNCLIPP_I : RISCVISD::PNCLIPUP_I; + unsigned ClipOpc = IsSigned ? RISCVISD::PNCLIP : RISCVISD::PNCLIPU; MVT HalfVT = VT == MVT::v8i8 ? MVT::v4i8 : MVT::v2i16; - SDValue Zero = DAG.getConstant(0, DL, XLenVT); - SDValue Lo = DAG.getNode(HOpc, DL, HalfVT, Rs1, Zero); - SDValue Hi = DAG.getNode(HOpc, DL, HalfVT, Rs2, Zero); - return DAG.getNode(RISCVISD::BuildPairGPRVec, DL, VT, Lo, Hi); + SDValue Lo = DAG.getNode(ClipOpc, DL, HalfVT, Rs1, Shift); + SDValue Hi = DAG.getNode(ClipOpc, DL, HalfVT, Rs2, Shift); + return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi); } - return DAG.getNode(Opc, DL, VT, Rs1, Rs2); + llvm_unreachable("unexpected VT for pnclipp/pnclipup on RV32"); } case Intrinsic::riscv_pmulq: case Intrinsic::riscv_pmulqr: { @@ -16649,8 +16639,7 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, Res = DAG.getNode(Opc, DL, WideVT, Ops); else Res = DAG.getNode(Opc, DL, WideVT, ArrayRef(Ops).slice(1)); - Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res, - DAG.getVectorIdxConstant(0, DL))); + Results.push_back(DAG.getExtractSubvector(DL, VT, Res, 0)); return; } case Intrinsic::riscv_pnclipp: @@ -16667,15 +16656,13 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, SDValue Packed = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideSrcVT, {Src1, Src2}); SDValue Res = DAG.getNode(Opc, DL, MVT::v8i8, {Packed, Packed}); - Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res, - DAG.getVectorIdxConstant(0, DL))); + Results.push_back(DAG.getExtractSubvector(DL, VT, Res, 0)); } else { MVT WideSrcVT = MVT::v2i32; SDValue Packed = DAG.getNode(ISD::BUILD_VECTOR, DL, WideSrcVT, {Src1, Src2}); SDValue Res = DAG.getNode(Opc, DL, MVT::v4i16, {Packed, Packed}); - Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res, - DAG.getVectorIdxConstant(0, DL))); + Results.push_back(DAG.getExtractSubvector(DL, VT, Res, 0)); } return; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td index c7aca498d3ac8..f09df843e0c40 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td @@ -1907,6 +1907,8 @@ def SDT_RISCVPackedNarrowingShift : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, XLenVT>]>; def riscv_pnsrl : RVSDNode<"PNSRL", SDT_RISCVPackedNarrowingShift>; +def riscv_pnclip : RVSDNode<"PNCLIP", SDT_RISCVPackedNarrowingShift>; +def riscv_pnclipu : RVSDNode<"PNCLIPU", SDT_RISCVPackedNarrowingShift>; // Packed narrowing clip pair. def SDT_RISCVPackedNarrowingClip @@ -1915,17 +1917,11 @@ def SDT_RISCVPackedNarrowingClip def riscv_pnclipp : RVSDNode<"PNCLIPP", SDT_RISCVPackedNarrowingClip>; def riscv_pnclipup : RVSDNode<"PNCLIPUP", SDT_RISCVPackedNarrowingClip>; -def SDT_RISCVPackedNarrowingClipI - : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, - SDTCisVT<2, XLenVT>]>; -def riscv_pnclipp_i : RVSDNode<"PNCLIPP_I", SDT_RISCVPackedNarrowingClipI>; -def riscv_pnclipup_i : RVSDNode<"PNCLIPUP_I", SDT_RISCVPackedNarrowingClipI>; - -def SDT_RISCVNarrowingClipI - : SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>, SDTCisVT<1, GPRPairVT>, - SDTCisVT<2, XLenVT>]>; -def riscv_nclipp_i : RVSDNode<"NCLIPP_I", SDT_RISCVNarrowingClipI>; -def riscv_nclipup_i : RVSDNode<"NCLIPUP_I", SDT_RISCVNarrowingClipI>; +def SDT_RISCVNarrowingClip + : SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>, SDTCisVT<1, XLenVT>, + SDTCisVT<2, XLenVT>, SDTCisVT<3, XLenVT>]>; +def riscv_nclip : RVSDNode<"NCLIP", SDT_RISCVNarrowingClip>; +def riscv_nclipu : RVSDNode<"NCLIPU", SDT_RISCVNarrowingClip>; def SDT_RISCVPackedNarrowingClipW : SDTypeProfile<1, 2, [SDTCisVT<0, v2i32>, @@ -2659,23 +2655,19 @@ let append Predicates = [IsRV32] in { (EXTRACT_SUBREG GPRPair:$vec, sub_gpr_odd)>; // Packed narrowing clip by immediate (RV32). shift=0 == plain clip. - def : Pat<(v4i8 (riscv_pnclipp_i (v4i16 GPRPair:$rs1), uimm4:$imm)), - (PNCLIPI_B GPRPair:$rs1, uimm4:$imm)>; - def : Pat<(v4i8 (riscv_pnclipup_i (v4i16 GPRPair:$rs1), uimm4:$imm)), - (PNCLIPIU_B GPRPair:$rs1, uimm4:$imm)>; - def : Pat<(v2i16 (riscv_pnclipp_i (v2i32 GPRPair:$rs1), uimm5:$imm)), - (PNCLIPI_H GPRPair:$rs1, uimm5:$imm)>; - def : Pat<(v2i16 (riscv_pnclipup_i (v2i32 GPRPair:$rs1), uimm5:$imm)), - (PNCLIPIU_H GPRPair:$rs1, uimm5:$imm)>; - - def : Pat<(XLenVT (riscv_nclipp_i - (riscv_build_gpr_pair GPR:$lo, GPR:$hi), - uimm6:$imm)), - (NCLIPI (BuildGPRPair GPR:$lo, GPR:$hi), uimm6:$imm)>; - def : Pat<(XLenVT (riscv_nclipup_i - (riscv_build_gpr_pair GPR:$lo, GPR:$hi), - uimm6:$imm)), - (NCLIPIU (BuildGPRPair GPR:$lo, GPR:$hi), uimm6:$imm)>; + def : Pat<(v4i8 (riscv_pnclip (v4i16 GPRPair:$rs1), timm:$imm)), + (PNCLIPI_B GPRPair:$rs1, timm:$imm)>; + def : Pat<(v4i8 (riscv_pnclipu (v4i16 GPRPair:$rs1), timm:$imm)), + (PNCLIPIU_B GPRPair:$rs1, timm:$imm)>; + def : Pat<(v2i16 (riscv_pnclip (v2i32 GPRPair:$rs1), timm:$imm)), + (PNCLIPI_H GPRPair:$rs1, timm:$imm)>; + def : Pat<(v2i16 (riscv_pnclipu (v2i32 GPRPair:$rs1), timm:$imm)), + (PNCLIPIU_H GPRPair:$rs1, timm:$imm)>; + + def : Pat<(XLenVT (riscv_nclip XLenVT:$lo, XLenVT:$hi, timm:$imm)), + (NCLIPI (BuildGPRPair GPR:$lo, GPR:$hi), timm:$imm)>; + def : Pat<(XLenVT (riscv_nclipu XLenVT:$lo, XLenVT:$hi, timm:$imm)), + (NCLIPIU (BuildGPRPair GPR:$lo, GPR:$hi), timm:$imm)>; } // append Predicates = [IsRV32] let append Predicates = [IsRV64] in { >From 1ea7ad8137b411aac8df9c1749f2f6e599e074bd Mon Sep 17 00:00:00 2001 From: Dongyan Chen <[email protected]> Date: Fri, 14 Aug 2026 07:24:07 +0000 Subject: [PATCH 4/4] resolve comments --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 7 ++--- llvm/test/CodeGen/RISCV/rvp-simd-32.ll | 35 --------------------- llvm/test/CodeGen/RISCV/rvp-simd-64.ll | 3 -- 3 files changed, 2 insertions(+), 43 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index f708f7ee32d0d..f4b10139bdaa6 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -12308,18 +12308,16 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, EVT VT = Op.getValueType(); SDValue Rs1 = Op.getOperand(1); SDValue Rs2 = Op.getOperand(2); - unsigned Opc = IsSigned ? RISCVISD::PNCLIPP : RISCVISD::PNCLIPUP; - if (Subtarget.is64Bit()) { if (VT == MVT::v2i32 && !Rs1.getValueType().isVector()) { unsigned WOpc = IsSigned ? RISCVISD::PNCLIPP_W : RISCVISD::PNCLIPUP_W; return DAG.getNode(WOpc, DL, VT, Rs1, Rs2); } + unsigned Opc = IsSigned ? RISCVISD::PNCLIPP : RISCVISD::PNCLIPUP; return DAG.getNode(Opc, DL, VT, Rs1, Rs2); } MVT XLenVT = Subtarget.getXLenVT(); - auto ToXLen = [&](SDValue V) { return DAG.getBitcast(XLenVT, V); }; SDValue Shift = DAG.getTargetConstant(0, DL, XLenVT); if (VT == MVT::v4i8) { unsigned ClipOpc = IsSigned ? RISCVISD::PNCLIP : RISCVISD::PNCLIPU; @@ -12328,8 +12326,7 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, } if (VT == MVT::v2i16) { unsigned ClipOpc = IsSigned ? RISCVISD::PNCLIP : RISCVISD::PNCLIPU; - SDValue Pair = DAG.getNode(RISCVISD::BuildPairGPRVec, DL, MVT::v2i32, - ToXLen(Rs1), ToXLen(Rs2)); + SDValue Pair = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Rs1, Rs2); return DAG.getNode(ClipOpc, DL, VT, Pair, Shift); } if (VT == MVT::v2i32) { diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll index 58ce754c73c24..8f96ec6e8a811 100644 --- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll +++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll @@ -2951,38 +2951,3 @@ define <2 x i16> @test_pnclipup_v2i16(i32 %a, i32 %b) { %r = call <2 x i16> @llvm.riscv.pnclipup.v2i16.i32(i32 %a, i32 %b) ret <2 x i16> %r } - -declare <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64, i64) -declare <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64, i64) - -define i64 @test_pnclipp_v2i32_i64(i64 %a, i64 %b) { -; RV32-LABEL: test_pnclipp_v2i32_i64: -; RV32: # %bb.0: -; RV32-NEXT: nclipi a0, a0, 0 -; RV32-NEXT: nclipi a1, a2, 0 -; RV32-NEXT: ret -; -; RV64-LABEL: test_pnclipp_v2i32_i64: -; RV64: # %bb.0: -; RV64-NEXT: pnclipp.w a0, a0, a1 -; RV64-NEXT: ret - %r = call <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64 %a, i64 %b) - %s = bitcast <2 x i32> %r to i64 - ret i64 %s -} - -define i64 @test_pnclipup_v2i32_i64(i64 %a, i64 %b) { -; RV32-LABEL: test_pnclipup_v2i32_i64: -; RV32: # %bb.0: -; RV32-NEXT: nclipiu a0, a0, 0 -; RV32-NEXT: nclipiu a1, a2, 0 -; RV32-NEXT: ret -; -; RV64-LABEL: test_pnclipup_v2i32_i64: -; RV64: # %bb.0: -; RV64-NEXT: pnclipup.w a0, a0, a1 -; RV64-NEXT: ret - %r = call <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64 %a, i64 %b) - %s = bitcast <2 x i32> %r to i64 - ret i64 %s -} diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll index 177c2ab488104..fe067d8225fc3 100644 --- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll +++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll @@ -6601,9 +6601,6 @@ define <4 x i16> @test_pnclipup_v4i16(<2 x i32> %a, <2 x i32> %b) { ret <4 x i16> %r } -declare <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64, i64) -declare <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64, i64) - define i64 @test_pnclipp_v2i32(i64 %a, i64 %b) { ; RV32-LABEL: test_pnclipp_v2i32: ; RV32: # %bb.0: _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
