Author: Amr Hesham Date: 2026-08-18T13:16:46+02:00 New Revision: b13157e090be60c095a6ef2779b907fcdb96e195
URL: https://github.com/llvm/llvm-project/commit/b13157e090be60c095a6ef2779b907fcdb96e195 DIFF: https://github.com/llvm/llvm-project/commit/b13157e090be60c095a6ef2779b907fcdb96e195.diff LOG: [CIR] Support Vec of bool in VecTernaryOp (#216377) Support the Vector of bool in VecTernaryOp Added: Modified: clang/include/clang/CIR/Dialect/IR/CIROps.td clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp clang/test/CIR/CodeGen/vector-bool.cpp Removed: ################################################################################ diff --git a/clang/include/clang/CIR/Dialect/IR/CIROps.td b/clang/include/clang/CIR/Dialect/IR/CIROps.td index ccf0a21d56e04..fbb71206b2a89 100644 --- a/clang/include/clang/CIR/Dialect/IR/CIROps.td +++ b/clang/include/clang/CIR/Dialect/IR/CIROps.td @@ -6030,7 +6030,7 @@ def CIR_VecTernaryOp : CIR_Op<"vec.ternary", [ }]; let arguments = (ins - CIR_VectorOfIntType:$cond, + CIR_VectorOfIntOrBoolType:$cond, CIR_VectorType:$lhs, CIR_VectorType:$rhs ); diff --git a/clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td b/clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td index c8f3eff18ce5c..0975e25a15ad0 100644 --- a/clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td +++ b/clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td @@ -328,10 +328,12 @@ def IntegerVector : Type< } // Vector of type constraints +def CIR_VectorOfBoolType : CIR_VectorTypeOf<[CIR_AnyBoolType]>; def CIR_VectorOfIntType : CIR_VectorTypeOf<[CIR_AnyIntType]>; def CIR_VectorOfUIntType : CIR_VectorTypeOf<[CIR_AnyUIntType]>; def CIR_VectorOfSIntType : CIR_VectorTypeOf<[CIR_AnySIntType]>; def CIR_VectorOfFloatType : CIR_VectorTypeOf<[CIR_AnyFloatType]>; +def CIR_VectorOfIntOrBoolType : CIR_VectorTypeOf<[CIR_AnyBoolType, CIR_AnyIntType]>; // Vector or Scalar type constraints def CIR_AnyIntOrVecOfIntType diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp index e82f417c627f5..28d265f70616d 100644 --- a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp +++ b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp @@ -5021,12 +5021,17 @@ mlir::LogicalResult CIRToLLVMVecShuffleDynamicOpLowering::matchAndRewrite( mlir::LogicalResult CIRToLLVMVecTernaryOpLowering::matchAndRewrite( cir::VecTernaryOp op, OpAdaptor adaptor, mlir::ConversionPatternRewriter &rewriter) const { - // Convert `cond` into a vector of i1, then use that in a `select` op. - mlir::Value bitVec = mlir::LLVM::ICmpOp::create( - rewriter, op.getLoc(), mlir::LLVM::ICmpPredicate::ne, adaptor.getCond(), - mlir::LLVM::ZeroOp::create( - rewriter, op.getCond().getLoc(), - typeConverter->convertType(op.getCond().getType()))); + mlir::Value bitVec = adaptor.getCond(); + + if (!isa<cir::BoolType>(op.getCond().getType().getElementType())) { + // Convert `cond` into a vector of i1, then use that in a `select` op. + bitVec = mlir::LLVM::ICmpOp::create( + rewriter, op.getLoc(), mlir::LLVM::ICmpPredicate::ne, adaptor.getCond(), + mlir::LLVM::ZeroOp::create( + rewriter, op.getCond().getLoc(), + typeConverter->convertType(op.getCond().getType()))); + } + rewriter.replaceOpWithNewOp<mlir::LLVM::SelectOp>( op, bitVec, adaptor.getLhs(), adaptor.getRhs()); return mlir::success(); diff --git a/clang/test/CIR/CodeGen/vector-bool.cpp b/clang/test/CIR/CodeGen/vector-bool.cpp index dd4a5f65aec05..91fa366c0872e 100644 --- a/clang/test/CIR/CodeGen/vector-bool.cpp +++ b/clang/test/CIR/CodeGen/vector-bool.cpp @@ -149,3 +149,34 @@ void vec_bool_5_load_store_with_padding_needed() { // SHARED: %[[INSERT_VEC:.*]] = shufflevector <5 x i1> %[[EXTRACT_VEC]], <5 x i1> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 poison, i32 poison, i32 poison> // SHARED: %[[RESULT:.*]] = bitcast <8 x i1> %[[INSERT_VEC]] to i8 // SHARED: store i8 %[[RESULT]], ptr %[[A_ADDR]], align 1 + +void vec_bool_ternary_expr() { + v8b a; + v8b b; + v8b c; + v8b d = a ? b : c; +} + +// CIR: %[[A_ADDR:.*]] = cir.alloca "a" {{.*}} : !cir.ptr<!cir.vector<8 x !cir.bool>> +// CIR: %[[B_ADDR:.*]] = cir.alloca "b" {{.*}} : !cir.ptr<!cir.vector<8 x !cir.bool>> +// CIR: %[[C_ADDR:.*]] = cir.alloca "c" {{.*}} : !cir.ptr<!cir.vector<8 x !cir.bool>> +// CIR: %[[D_ADDR:.*]] = cir.alloca "d" {{.*}} init : !cir.ptr<!cir.vector<8 x !cir.bool>> +// CIR: %[[TMP_A:.*]] = cir.load {{.*}} %[[A_ADDR]] : !cir.ptr<!cir.vector<8 x !cir.bool>>, !cir.vector<8 x !cir.bool> +// CIR: %[[TMP_B:.*]] = cir.load {{.*}} %[[B_ADDR]] : !cir.ptr<!cir.vector<8 x !cir.bool>>, !cir.vector<8 x !cir.bool> +// CIR: %[[TMP_C:.*]] = cir.load {{.*}} %[[C_ADDR]] : !cir.ptr<!cir.vector<8 x !cir.bool>>, !cir.vector<8 x !cir.bool> +// CIR: %[[RESULT:.*]] = cir.vec.ternary(%[[TMP_A]], %[[TMP_B]], %[[TMP_C]]) : !cir.vector<8 x !cir.bool>, !cir.vector<8 x !cir.bool> +// CIR: cir.store {{.*}} %[[RESULT]], %[[D_ADDR]] : !cir.vector<8 x !cir.bool>, !cir.ptr<!cir.vector<8 x !cir.bool>> + +// SHARED: %[[A_ADDR:.*]] = alloca i8, align 1 +// SHARED: %[[B_ADDR:.*]] = alloca i8, align 1 +// SHARED: %[[C_ADDR:.*]] = alloca i8, align 1 +// SHARED: %[[D_ADDR:.*]] = alloca i8, align 1 +// SHARED: %[[TMP_A:.*]] = load i8, ptr %[[A_ADDR]], align 1 +// SHARED: %[[TMP_A_I8:.*]] = bitcast i8 %[[TMP_A]] to <8 x i1> +// SHARED: %[[TMP_B:.*]] = load i8, ptr %[[B_ADDR]], align 1 +// SHARED: %[[TMP_B_I8:.*]] = bitcast i8 %[[TMP_B]] to <8 x i1> +// SHARED: %[[TMP_C:.*]] = load i8, ptr %[[C_ADDR]], align 1 +// SHARED: %[[TMP_C_I8:.*]] = bitcast i8 %[[TMP_C]] to <8 x i1> +// SHARED: %[[RESULT:.*]] = select <8 x i1> %[[TMP_A_I8]], <8 x i1> %[[TMP_B_I8]], <8 x i1> %[[TMP_C_I8]] +// SHARED: %[[RESULT_I8:.*]] = bitcast <8 x i1> %[[RESULT]] to i8 +// SHARED: store i8 %[[RESULT_I8]], ptr %[[D_ADDR]], align 1 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
