github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
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:warning:
<details>
<summary>
You can test this locally with the following command:
</summary>
``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h,c --
clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
clang/lib/Headers/riscv_packed_simd.h
cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
llvm/lib/Target/RISCV/RISCVISelLowering.cpp --diff_from_common_commit
``````````
:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:
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<details>
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View the diff from clang-format here.
</summary>
``````````diff
diff --git a/clang/lib/Headers/riscv_packed_simd.h
b/clang/lib/Headers/riscv_packed_simd.h
index 0c0bcb2b8..7fb596113 100644
--- a/clang/lib/Headers/riscv_packed_simd.h
+++ b/clang/lib/Headers/riscv_packed_simd.h
@@ -78,14 +78,14 @@ typedef uint32_t uint32x2_t
__attribute__((__vector_size__(8)));
}
#define __packed_ternary_builtin(name, ty, builtin)
\
- static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(
\
- ty __rd, ty __rs1, ty __rs2) {
\
+ static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rd, ty __rs1,
\
+ ty __rs2) {
\
return builtin(__rd, __rs1, __rs2);
\
}
#define __packed_ternary_builtin_mixed(name, rty, ty1, ty2, builtin)
\
- static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(
\
- rty __rd, ty1 __rs1, ty2 __rs2) {
\
+ static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(rty __rd, ty1 __rs1,
\
+ ty2 __rs2) {
\
return builtin(__rd, __rs1, __rs2);
\
}
diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
index 9c76e228e..4268482d8 100644
--- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
@@ -2516,29 +2516,25 @@ int16x2_t test_pmhracc_i16x2(int16x2_t rd, int16x2_t
rs1, int16x2_t rs2) {
// CHECK-LABEL: test_pmhaccu_u16x2:
// CHECK: pmhaccu.h
-uint16x2_t test_pmhaccu_u16x2(uint16x2_t rd, uint16x2_t rs1,
- uint16x2_t rs2) {
+uint16x2_t test_pmhaccu_u16x2(uint16x2_t rd, uint16x2_t rs1, uint16x2_t rs2) {
return __riscv_pmhaccu_u16x2(rd, rs1, rs2);
}
// CHECK-LABEL: test_pmhraccu_u16x2:
// CHECK: pmhraccu.h
-uint16x2_t test_pmhraccu_u16x2(uint16x2_t rd, uint16x2_t rs1,
- uint16x2_t rs2) {
+uint16x2_t test_pmhraccu_u16x2(uint16x2_t rd, uint16x2_t rs1, uint16x2_t rs2) {
return __riscv_pmhraccu_u16x2(rd, rs1, rs2);
}
// CHECK-LABEL: test_pmhaccsu_i16x2:
// CHECK: pmhaccsu.h
-int16x2_t test_pmhaccsu_i16x2(int16x2_t rd, int16x2_t rs1,
- uint16x2_t rs2) {
+int16x2_t test_pmhaccsu_i16x2(int16x2_t rd, int16x2_t rs1, uint16x2_t rs2) {
return __riscv_pmhaccsu_i16x2(rd, rs1, rs2);
}
// CHECK-LABEL: test_pmhraccsu_i16x2:
// CHECK: pmhraccsu.h
-int16x2_t test_pmhraccsu_i16x2(int16x2_t rd, int16x2_t rs1,
- uint16x2_t rs2) {
+int16x2_t test_pmhraccsu_i16x2(int16x2_t rd, int16x2_t rs1, uint16x2_t rs2) {
return __riscv_pmhraccsu_i16x2(rd, rs1, rs2);
}
@@ -2559,32 +2555,28 @@ int16x4_t test_pmhracc_i16x4(int16x4_t rd, int16x4_t
rs1, int16x4_t rs2) {
// CHECK-LABEL: test_pmhaccu_u16x4:
// RV32-COUNT-2: pmhaccu.h
// RV64: pmhaccu.h
-uint16x4_t test_pmhaccu_u16x4(uint16x4_t rd, uint16x4_t rs1,
- uint16x4_t rs2) {
+uint16x4_t test_pmhaccu_u16x4(uint16x4_t rd, uint16x4_t rs1, uint16x4_t rs2) {
return __riscv_pmhaccu_u16x4(rd, rs1, rs2);
}
// CHECK-LABEL: test_pmhraccu_u16x4:
// RV32-COUNT-2: pmhraccu.h
// RV64: pmhraccu.h
-uint16x4_t test_pmhraccu_u16x4(uint16x4_t rd, uint16x4_t rs1,
- uint16x4_t rs2) {
+uint16x4_t test_pmhraccu_u16x4(uint16x4_t rd, uint16x4_t rs1, uint16x4_t rs2) {
return __riscv_pmhraccu_u16x4(rd, rs1, rs2);
}
// CHECK-LABEL: test_pmhaccsu_i16x4:
// RV32-COUNT-2: pmhaccsu.h
// RV64: pmhaccsu.h
-int16x4_t test_pmhaccsu_i16x4(int16x4_t rd, int16x4_t rs1,
- uint16x4_t rs2) {
+int16x4_t test_pmhaccsu_i16x4(int16x4_t rd, int16x4_t rs1, uint16x4_t rs2) {
return __riscv_pmhaccsu_i16x4(rd, rs1, rs2);
}
// CHECK-LABEL: test_pmhraccsu_i16x4:
// RV32-COUNT-2: pmhraccsu.h
// RV64: pmhraccsu.h
-int16x4_t test_pmhraccsu_i16x4(int16x4_t rd, int16x4_t rs1,
- uint16x4_t rs2) {
+int16x4_t test_pmhraccsu_i16x4(int16x4_t rd, int16x4_t rs1, uint16x4_t rs2) {
return __riscv_pmhraccsu_i16x4(rd, rs1, rs2);
}
@@ -2605,16 +2597,14 @@ int32x2_t test_pmhracc_i32x2(int32x2_t rd, int32x2_t
rs1, int32x2_t rs2) {
// CHECK-LABEL: test_pmhaccu_u32x2:
// RV32-COUNT-2: mhaccu
// RV64: pmhaccu.w
-uint32x2_t test_pmhaccu_u32x2(uint32x2_t rd, uint32x2_t rs1,
- uint32x2_t rs2) {
+uint32x2_t test_pmhaccu_u32x2(uint32x2_t rd, uint32x2_t rs1, uint32x2_t rs2) {
return __riscv_pmhaccu_u32x2(rd, rs1, rs2);
}
// CHECK-LABEL: test_pmhraccu_u32x2:
// RV32-COUNT-2: mhraccu
// RV64: pmhraccu.w
-uint32x2_t test_pmhraccu_u32x2(uint32x2_t rd, uint32x2_t rs1,
- uint32x2_t rs2) {
+uint32x2_t test_pmhraccu_u32x2(uint32x2_t rd, uint32x2_t rs1, uint32x2_t rs2) {
return __riscv_pmhraccu_u32x2(rd, rs1, rs2);
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 789ffbabd..54a0145f5 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -12603,10 +12603,8 @@ SDValue
RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
auto [RdLo, RdHi] = DAG.SplitVector(Rd, DL);
auto [Rs1Lo, Rs1Hi] = DAG.SplitVector(Rs1, DL);
auto [Rs2Lo, Rs2Hi] = DAG.SplitVector(Rs2, DL);
- SDValue Lo =
- DAG.getNode(MulOpc, DL, MVT::v2i16, RdLo, Rs1Lo, Rs2Lo);
- SDValue Hi =
- DAG.getNode(MulOpc, DL, MVT::v2i16, RdHi, Rs1Hi, Rs2Hi);
+ SDValue Lo = DAG.getNode(MulOpc, DL, MVT::v2i16, RdLo, Rs1Lo, Rs2Lo);
+ SDValue Hi = DAG.getNode(MulOpc, DL, MVT::v2i16, RdHi, Rs1Hi, Rs2Hi);
return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
}
@@ -12615,9 +12613,9 @@ SDValue
RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return DAG.getExtractVectorElt(DL, MVT::i32, V, Idx);
};
SDValue Lo = DAG.getNode(MulOpc, DL, MVT::i32, Extract(Rd, 0),
- Extract(Rs1, 0), Extract(Rs2, 0));
+ Extract(Rs1, 0), Extract(Rs2, 0));
SDValue Hi = DAG.getNode(MulOpc, DL, MVT::i32, Extract(Rd, 1),
- Extract(Rs1, 1), Extract(Rs2, 1));
+ Extract(Rs1, 1), Extract(Rs2, 1));
return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Lo, Hi);
}
@@ -16703,15 +16701,14 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode
*N,
EVT WideVT = MVT::v4i16;
SDValue Undef = DAG.getUNDEF(VT);
- SDValue Rd = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideVT,
- N->getOperand(1), Undef);
- SDValue Rs1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideVT,
- N->getOperand(2), Undef);
- SDValue Rs2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideVT,
- N->getOperand(3), Undef);
- SDValue Res =
- DAG.getNode(getRVPMulHighAccumulateOpcode(IntNo), DL, WideVT, Rd,
- Rs1, Rs2);
+ SDValue Rd =
+ DAG.getNode(ISD::CONCAT_VECTORS, DL, WideVT, N->getOperand(1),
Undef);
+ SDValue Rs1 =
+ DAG.getNode(ISD::CONCAT_VECTORS, DL, WideVT, N->getOperand(2),
Undef);
+ SDValue Rs2 =
+ DAG.getNode(ISD::CONCAT_VECTORS, DL, WideVT, N->getOperand(3),
Undef);
+ SDValue Res = DAG.getNode(getRVPMulHighAccumulateOpcode(IntNo), DL,
+ WideVT, Rd, Rs1, Rs2);
Results.push_back(DAG.getExtractSubvector(DL, VT, Res, 0));
return;
}
``````````
</details>
https://github.com/llvm/llvm-project/pull/217591
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