llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Hongyu Chen (XChy) <details> <summary>Changes</summary> See also https://github.com/riscv/riscv-p-spec/blob/master/P-ext-intrinsics.adoc#packed-multiplication-with-horizontal-addition. --- Patch is 53.97 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/218430.diff 9 Files Affected: - (modified) clang/include/clang/Basic/BuiltinsRISCV.td (+41) - (modified) clang/lib/CodeGen/TargetBuiltins/RISCV.cpp (+110) - (modified) clang/lib/Headers/riscv_packed_simd.h (+41) - (modified) cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c (+285) - (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+19) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+100) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoP.td (+140) - (modified) llvm/test/CodeGen/RISCV/rvp-simd-32.ll (+117) - (modified) llvm/test/CodeGen/RISCV/rvp-simd-64.ll (+375) ``````````diff diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td index 89dbf736f4435..9cddafd659af1 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.td +++ b/clang/include/clang/Basic/BuiltinsRISCV.td @@ -291,6 +291,47 @@ def pmhaccsu_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2, i def pmhraccsu_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<4, short>, _Vector<4, unsigned short>)">; def pmhraccsu_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2, int>, _Vector<2, unsigned int>)">; +// Packed Multiplication with Horizontal Addition (32-bit) +def pm4add_i8x4 : RISCVBuiltin<"int(_Vector<4, signed char>, _Vector<4, signed char>)">; +def pm2add_i16x2 : RISCVBuiltin<"int(_Vector<2, short>, _Vector<2, short>)">; +def pm2add_x_i16x2 : RISCVBuiltin<"int(_Vector<2, short>, _Vector<2, short>)">; +def pm4addu_u8x4 : RISCVBuiltin<"unsigned int(_Vector<4, unsigned char>, _Vector<4, unsigned char>)">; +def pm2addu_u16x2 : RISCVBuiltin<"unsigned int(_Vector<2, unsigned short>, _Vector<2, unsigned short>)">; +def pmq2add_i16x2 : RISCVBuiltin<"int(_Vector<2, short>, _Vector<2, short>)">; +def pmqr2add_i16x2 : RISCVBuiltin<"int(_Vector<2, short>, _Vector<2, short>)">; +def pm2sadd_i16x2 : RISCVBuiltin<"int(_Vector<2, short>, _Vector<2, short>)">; +def pm2sadd_x_i16x2 : RISCVBuiltin<"int(_Vector<2, short>, _Vector<2, short>)">; +def pm2sub_i16x2 : RISCVBuiltin<"int(_Vector<2, short>, _Vector<2, short>)">; +def pm2sub_x_i16x2 : RISCVBuiltin<"int(_Vector<2, short>, _Vector<2, short>)">; +def pm4addsu_i8x4 : RISCVBuiltin<"int(_Vector<4, signed char>, _Vector<4, unsigned char>)">; +def pm2addsu_i16x2 : RISCVBuiltin<"int(_Vector<2, short>, _Vector<2, unsigned short>)">; + +// Packed Multiplication with Horizontal Addition (64-bit) +def pm4add_i8x8 : RISCVBuiltin<"_Vector<2, int>(_Vector<8, signed char>, _Vector<8, signed char>)">; +def pm2add_i16x4 : RISCVBuiltin<"_Vector<2, int>(_Vector<4, short>, _Vector<4, short>)">; +def pm2add_x_i16x4 : RISCVBuiltin<"_Vector<2, int>(_Vector<4, short>, _Vector<4, short>)">; +def pm4addu_u8x8 : RISCVBuiltin<"_Vector<2, unsigned int>(_Vector<8, unsigned char>, _Vector<8, unsigned char>)">; +def pm2addu_u16x4 : RISCVBuiltin<"_Vector<2, unsigned int>(_Vector<4, unsigned short>, _Vector<4, unsigned short>)">; +def pmq2add_i16x4 : RISCVBuiltin<"_Vector<2, int>(_Vector<4, short>, _Vector<4, short>)">; +def pmqr2add_i16x4 : RISCVBuiltin<"_Vector<2, int>(_Vector<4, short>, _Vector<4, short>)">; +def pm2sadd_i16x4 : RISCVBuiltin<"_Vector<2, int>(_Vector<4, short>, _Vector<4, short>)">; +def pm2sadd_x_i16x4 : RISCVBuiltin<"_Vector<2, int>(_Vector<4, short>, _Vector<4, short>)">; +def pm2sub_i16x4 : RISCVBuiltin<"_Vector<2, int>(_Vector<4, short>, _Vector<4, short>)">; +def pm2sub_x_i16x4 : RISCVBuiltin<"_Vector<2, int>(_Vector<4, short>, _Vector<4, short>)">; +def pm4addsu_i8x8 : RISCVBuiltin<"_Vector<2, int>(_Vector<8, signed char>, _Vector<8, unsigned char>)">; +def pm2addsu_i16x4 : RISCVBuiltin<"_Vector<2, int>(_Vector<4, short>, _Vector<4, unsigned short>)">; +def pm2add_i32x2 : RISCVBuiltin<"int64_t(_Vector<2, int>, _Vector<2, int>)">; +def pm2add_x_i32x2 : RISCVBuiltin<"int64_t(_Vector<2, int>, _Vector<2, int>)">; +def pm2addu_u32x2 : RISCVBuiltin<"uint64_t(_Vector<2, unsigned int>, _Vector<2, unsigned int>)">; +def pmq2add_i32x2 : RISCVBuiltin<"int64_t(_Vector<2, int>, _Vector<2, int>)">; +def pm2sub_i32x2 : RISCVBuiltin<"int64_t(_Vector<2, int>, _Vector<2, int>)">; +def pm2sub_x_i32x2 : RISCVBuiltin<"int64_t(_Vector<2, int>, _Vector<2, int>)">; +def pm2addsu_i32x2 : RISCVBuiltin<"int64_t(_Vector<2, int>, _Vector<2, unsigned int>)">; +def pmqr2add_i32x2 : RISCVBuiltin<"int64_t(_Vector<2, int>, _Vector<2, int>)">; +def pm4add_i16x4 : RISCVBuiltin<"int64_t(_Vector<4, short>, _Vector<4, short>)">; +def pm4addu_u16x4 : RISCVBuiltin<"uint64_t(_Vector<4, unsigned short>, _Vector<4, unsigned short>)">; +def pm4addsu_i16x4 : RISCVBuiltin<"int64_t(_Vector<4, short>, _Vector<4, unsigned short>)">; + // Packed Absolute Difference Sum (32-bit) def pabdsumu_u8x4_u32 : RISCVBuiltin<"unsigned int(_Vector<4, unsigned char>, _Vector<4, unsigned char>)">; def pabdsumau_u8x4_u32 : RISCVBuiltin<"unsigned int(unsigned int, _Vector<4, unsigned char>, _Vector<4, unsigned char>)">; diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp index 88fedecbee504..5c5ed9083057f 100644 --- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp @@ -1531,6 +1531,116 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, break; } + // Packed Multiplication with Horizontal Addition + case RISCV::BI__builtin_riscv_pm4add_i8x4: + case RISCV::BI__builtin_riscv_pm4add_i8x8: + case RISCV::BI__builtin_riscv_pm4add_i16x4: + case RISCV::BI__builtin_riscv_pm2add_i16x2: + case RISCV::BI__builtin_riscv_pm2add_i16x4: + case RISCV::BI__builtin_riscv_pm2add_i32x2: + case RISCV::BI__builtin_riscv_pm2add_x_i16x2: + case RISCV::BI__builtin_riscv_pm2add_x_i16x4: + case RISCV::BI__builtin_riscv_pm2add_x_i32x2: + case RISCV::BI__builtin_riscv_pm4addu_u8x4: + case RISCV::BI__builtin_riscv_pm4addu_u8x8: + case RISCV::BI__builtin_riscv_pm4addu_u16x4: + case RISCV::BI__builtin_riscv_pm2addu_u16x2: + case RISCV::BI__builtin_riscv_pm2addu_u16x4: + case RISCV::BI__builtin_riscv_pm2addu_u32x2: + case RISCV::BI__builtin_riscv_pmq2add_i16x2: + case RISCV::BI__builtin_riscv_pmq2add_i16x4: + case RISCV::BI__builtin_riscv_pmq2add_i32x2: + case RISCV::BI__builtin_riscv_pmqr2add_i16x2: + case RISCV::BI__builtin_riscv_pmqr2add_i16x4: + case RISCV::BI__builtin_riscv_pmqr2add_i32x2: + case RISCV::BI__builtin_riscv_pm2sadd_i16x2: + case RISCV::BI__builtin_riscv_pm2sadd_i16x4: + case RISCV::BI__builtin_riscv_pm2sadd_x_i16x2: + case RISCV::BI__builtin_riscv_pm2sadd_x_i16x4: + case RISCV::BI__builtin_riscv_pm2sub_i16x2: + case RISCV::BI__builtin_riscv_pm2sub_i16x4: + case RISCV::BI__builtin_riscv_pm2sub_i32x2: + case RISCV::BI__builtin_riscv_pm2sub_x_i16x2: + case RISCV::BI__builtin_riscv_pm2sub_x_i16x4: + case RISCV::BI__builtin_riscv_pm2sub_x_i32x2: + case RISCV::BI__builtin_riscv_pm4addsu_i8x4: + case RISCV::BI__builtin_riscv_pm4addsu_i8x8: + case RISCV::BI__builtin_riscv_pm4addsu_i16x4: + case RISCV::BI__builtin_riscv_pm2addsu_i16x2: + case RISCV::BI__builtin_riscv_pm2addsu_i16x4: + case RISCV::BI__builtin_riscv_pm2addsu_i32x2: { + switch (BuiltinID) { + default: + llvm_unreachable("unexpected builtin ID"); + case RISCV::BI__builtin_riscv_pm4add_i8x4: + case RISCV::BI__builtin_riscv_pm4add_i8x8: + case RISCV::BI__builtin_riscv_pm4add_i16x4: + ID = Intrinsic::riscv_pm4add; + break; + case RISCV::BI__builtin_riscv_pm2add_i16x2: + case RISCV::BI__builtin_riscv_pm2add_i16x4: + case RISCV::BI__builtin_riscv_pm2add_i32x2: + ID = Intrinsic::riscv_pm2add; + break; + case RISCV::BI__builtin_riscv_pm2add_x_i16x2: + case RISCV::BI__builtin_riscv_pm2add_x_i16x4: + case RISCV::BI__builtin_riscv_pm2add_x_i32x2: + ID = Intrinsic::riscv_pm2add_x; + break; + case RISCV::BI__builtin_riscv_pm4addu_u8x4: + case RISCV::BI__builtin_riscv_pm4addu_u8x8: + case RISCV::BI__builtin_riscv_pm4addu_u16x4: + ID = Intrinsic::riscv_pm4addu; + break; + case RISCV::BI__builtin_riscv_pm2addu_u16x2: + case RISCV::BI__builtin_riscv_pm2addu_u16x4: + case RISCV::BI__builtin_riscv_pm2addu_u32x2: + ID = Intrinsic::riscv_pm2addu; + break; + case RISCV::BI__builtin_riscv_pmq2add_i16x2: + case RISCV::BI__builtin_riscv_pmq2add_i16x4: + case RISCV::BI__builtin_riscv_pmq2add_i32x2: + ID = Intrinsic::riscv_pmq2add; + break; + case RISCV::BI__builtin_riscv_pmqr2add_i16x2: + case RISCV::BI__builtin_riscv_pmqr2add_i16x4: + case RISCV::BI__builtin_riscv_pmqr2add_i32x2: + ID = Intrinsic::riscv_pmqr2add; + break; + case RISCV::BI__builtin_riscv_pm2sadd_i16x2: + case RISCV::BI__builtin_riscv_pm2sadd_i16x4: + ID = Intrinsic::riscv_pm2sadd; + break; + case RISCV::BI__builtin_riscv_pm2sadd_x_i16x2: + case RISCV::BI__builtin_riscv_pm2sadd_x_i16x4: + ID = Intrinsic::riscv_pm2sadd_x; + break; + case RISCV::BI__builtin_riscv_pm2sub_i16x2: + case RISCV::BI__builtin_riscv_pm2sub_i16x4: + case RISCV::BI__builtin_riscv_pm2sub_i32x2: + ID = Intrinsic::riscv_pm2sub; + break; + case RISCV::BI__builtin_riscv_pm2sub_x_i16x2: + case RISCV::BI__builtin_riscv_pm2sub_x_i16x4: + case RISCV::BI__builtin_riscv_pm2sub_x_i32x2: + ID = Intrinsic::riscv_pm2sub_x; + break; + case RISCV::BI__builtin_riscv_pm4addsu_i8x4: + case RISCV::BI__builtin_riscv_pm4addsu_i8x8: + case RISCV::BI__builtin_riscv_pm4addsu_i16x4: + ID = Intrinsic::riscv_pm4addsu; + break; + case RISCV::BI__builtin_riscv_pm2addsu_i16x2: + case RISCV::BI__builtin_riscv_pm2addsu_i16x4: + case RISCV::BI__builtin_riscv_pm2addsu_i32x2: + ID = Intrinsic::riscv_pm2addsu; + break; + } + + IntrinsicTypes = {ResultType, Ops[0]->getType()}; + break; + } + // Packed Reduction Sum case RISCV::BI__builtin_riscv_predsum_i8x4_i32: case RISCV::BI__builtin_riscv_predsum_i16x2_i32: diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h index 318900805043c..92d01e0868c1c 100644 --- a/clang/lib/Headers/riscv_packed_simd.h +++ b/clang/lib/Headers/riscv_packed_simd.h @@ -813,6 +813,47 @@ __packed_ternary_builtin_mixed(pmhaccsu_i32x2, int32x2_t, int32x2_t, uint32x2_t, __packed_ternary_builtin_mixed(pmhraccsu_i16x4, int16x4_t, int16x4_t, uint16x4_t, __builtin_riscv_pmhraccsu_i16x4) __packed_ternary_builtin_mixed(pmhraccsu_i32x2, int32x2_t, int32x2_t, uint32x2_t, __builtin_riscv_pmhraccsu_i32x2) +/* Packed Multiplication with Horizontal Addition (32-bit) */ +__packed_binary_builtin_mixed(pm4add_i8x4, int32_t, int8x4_t, int8x4_t, __builtin_riscv_pm4add_i8x4) +__packed_binary_builtin_mixed(pm2add_i16x2, int32_t, int16x2_t, int16x2_t, __builtin_riscv_pm2add_i16x2) +__packed_binary_builtin_mixed(pm2add_x_i16x2, int32_t, int16x2_t, int16x2_t, __builtin_riscv_pm2add_x_i16x2) +__packed_binary_builtin_mixed(pm4addu_u8x4, uint32_t, uint8x4_t, uint8x4_t, __builtin_riscv_pm4addu_u8x4) +__packed_binary_builtin_mixed(pm2addu_u16x2, uint32_t, uint16x2_t, uint16x2_t, __builtin_riscv_pm2addu_u16x2) +__packed_binary_builtin_mixed(pmq2add_i16x2, int32_t, int16x2_t, int16x2_t, __builtin_riscv_pmq2add_i16x2) +__packed_binary_builtin_mixed(pmqr2add_i16x2, int32_t, int16x2_t, int16x2_t, __builtin_riscv_pmqr2add_i16x2) +__packed_binary_builtin_mixed(pm2sadd_i16x2, int32_t, int16x2_t, int16x2_t, __builtin_riscv_pm2sadd_i16x2) +__packed_binary_builtin_mixed(pm2sadd_x_i16x2, int32_t, int16x2_t, int16x2_t, __builtin_riscv_pm2sadd_x_i16x2) +__packed_binary_builtin_mixed(pm2sub_i16x2, int32_t, int16x2_t, int16x2_t, __builtin_riscv_pm2sub_i16x2) +__packed_binary_builtin_mixed(pm2sub_x_i16x2, int32_t, int16x2_t, int16x2_t, __builtin_riscv_pm2sub_x_i16x2) +__packed_binary_builtin_mixed(pm4addsu_i8x4, int32_t, int8x4_t, uint8x4_t, __builtin_riscv_pm4addsu_i8x4) +__packed_binary_builtin_mixed(pm2addsu_i16x2, int32_t, int16x2_t, uint16x2_t, __builtin_riscv_pm2addsu_i16x2) + +/* Packed Multiplication with Horizontal Addition (64-bit) */ +__packed_binary_builtin_mixed(pm4add_i8x8, int32x2_t, int8x8_t, int8x8_t, __builtin_riscv_pm4add_i8x8) +__packed_binary_builtin_mixed(pm2add_i16x4, int32x2_t, int16x4_t, int16x4_t, __builtin_riscv_pm2add_i16x4) +__packed_binary_builtin_mixed(pm2add_x_i16x4, int32x2_t, int16x4_t, int16x4_t, __builtin_riscv_pm2add_x_i16x4) +__packed_binary_builtin_mixed(pm4addu_u8x8, uint32x2_t, uint8x8_t, uint8x8_t, __builtin_riscv_pm4addu_u8x8) +__packed_binary_builtin_mixed(pm2addu_u16x4, uint32x2_t, uint16x4_t, uint16x4_t, __builtin_riscv_pm2addu_u16x4) +__packed_binary_builtin_mixed(pmq2add_i16x4, int32x2_t, int16x4_t, int16x4_t, __builtin_riscv_pmq2add_i16x4) +__packed_binary_builtin_mixed(pmqr2add_i16x4, int32x2_t, int16x4_t, int16x4_t, __builtin_riscv_pmqr2add_i16x4) +__packed_binary_builtin_mixed(pm2sadd_i16x4, int32x2_t, int16x4_t, int16x4_t, __builtin_riscv_pm2sadd_i16x4) +__packed_binary_builtin_mixed(pm2sadd_x_i16x4, int32x2_t, int16x4_t, int16x4_t, __builtin_riscv_pm2sadd_x_i16x4) +__packed_binary_builtin_mixed(pm2sub_i16x4, int32x2_t, int16x4_t, int16x4_t, __builtin_riscv_pm2sub_i16x4) +__packed_binary_builtin_mixed(pm2sub_x_i16x4, int32x2_t, int16x4_t, int16x4_t, __builtin_riscv_pm2sub_x_i16x4) +__packed_binary_builtin_mixed(pm4addsu_i8x8, int32x2_t, int8x8_t, uint8x8_t, __builtin_riscv_pm4addsu_i8x8) +__packed_binary_builtin_mixed(pm2addsu_i16x4, int32x2_t, int16x4_t, uint16x4_t, __builtin_riscv_pm2addsu_i16x4) +__packed_binary_builtin_mixed(pm2add_i32x2, int64_t, int32x2_t, int32x2_t, __builtin_riscv_pm2add_i32x2) +__packed_binary_builtin_mixed(pm2add_x_i32x2, int64_t, int32x2_t, int32x2_t, __builtin_riscv_pm2add_x_i32x2) +__packed_binary_builtin_mixed(pm2addu_u32x2, uint64_t, uint32x2_t, uint32x2_t, __builtin_riscv_pm2addu_u32x2) +__packed_binary_builtin_mixed(pmq2add_i32x2, int64_t, int32x2_t, int32x2_t, __builtin_riscv_pmq2add_i32x2) +__packed_binary_builtin_mixed(pm2sub_i32x2, int64_t, int32x2_t, int32x2_t, __builtin_riscv_pm2sub_i32x2) +__packed_binary_builtin_mixed(pm2sub_x_i32x2, int64_t, int32x2_t, int32x2_t, __builtin_riscv_pm2sub_x_i32x2) +__packed_binary_builtin_mixed(pm2addsu_i32x2, int64_t, int32x2_t, uint32x2_t, __builtin_riscv_pm2addsu_i32x2) +__packed_binary_builtin_mixed(pmqr2add_i32x2, int64_t, int32x2_t, int32x2_t, __builtin_riscv_pmqr2add_i32x2) +__packed_binary_builtin_mixed(pm4add_i16x4, int64_t, int16x4_t, int16x4_t, __builtin_riscv_pm4add_i16x4) +__packed_binary_builtin_mixed(pm4addu_u16x4, uint64_t, uint16x4_t, uint16x4_t, __builtin_riscv_pm4addu_u16x4) +__packed_binary_builtin_mixed(pm4addsu_i16x4, int64_t, int16x4_t, uint16x4_t, __builtin_riscv_pm4addsu_i16x4) + /* Packed Absolute Difference Sum (32-bit) */ __packed_abdsum(pabdsumu_u8x4_u32, uint32_t, uint8x4_t, __builtin_riscv_pabdsumu_u8x4_u32) __packed_abdsum_acc(pabdsumau_u8x4_u32, uint32_t, uint8x4_t, __builtin_riscv_pabdsumau_u8x4_u32) diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c index 75dcb796b66cd..7a4d909968b23 100644 --- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c +++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c @@ -3406,3 +3406,288 @@ int32x2_t test_pnclipp_i32x2(int64_t a, int64_t b) { uint32x2_t test_pnclipup_u32x2(uint64_t a, uint64_t b) { return __riscv_pnclipup_u32x2(a, b); } + +// CHECK-LABEL: test_pm4add_i8x4: +// RV32: pm4add.b +// RV64: pm4add.b +int32_t test_pm4add_i8x4(int8x4_t rs1, int8x4_t rs2) { + return __riscv_pm4add_i8x4(rs1, rs2); +} + +// CHECK-LABEL: test_pm2add_i16x2: +// RV32: pm2add.h +// RV64: pm2add.h +int32_t test_pm2add_i16x2(int16x2_t rs1, int16x2_t rs2) { + return __riscv_pm2add_i16x2(rs1, rs2); +} + +// CHECK-LABEL: test_pm2add_x_i16x2: +// RV32: pm2add.hx +// RV64: pm2add.hx +int32_t test_pm2add_x_i16x2(int16x2_t rs1, int16x2_t rs2) { + return __riscv_pm2add_x_i16x2(rs1, rs2); +} + +// CHECK-LABEL: test_pm4addu_u8x4: +// RV32: pm4addu.b +// RV64: pm4addu.b +uint32_t test_pm4addu_u8x4(uint8x4_t rs1, uint8x4_t rs2) { + return __riscv_pm4addu_u8x4(rs1, rs2); +} + +// CHECK-LABEL: test_pm2addu_u16x2: +// RV32: pm2addu.h +// RV64: pm2addu.h +uint32_t test_pm2addu_u16x2(uint16x2_t rs1, uint16x2_t rs2) { + return __riscv_pm2addu_u16x2(rs1, rs2); +} + +// CHECK-LABEL: test_pmq2add_i16x2: +// RV32: pmq2add.h +// RV64: pmq2add.h +int32_t test_pmq2add_i16x2(int16x2_t rs1, int16x2_t rs2) { + return __riscv_pmq2add_i16x2(rs1, rs2); +} + +// CHECK-LABEL: test_pmqr2add_i16x2: +// RV32: pmqr2add.h +// RV64: pmqr2add.h +int32_t test_pmqr2add_i16x2(int16x2_t rs1, int16x2_t rs2) { + return __riscv_pmqr2add_i16x2(rs1, rs2); +} + +// CHECK-LABEL: test_pm2sadd_i16x2: +// RV32: pm2sadd.h +// RV64: pm2sadd.h +int32_t test_pm2sadd_i16x2(int16x2_t rs1, int16x2_t rs2) { + return __riscv_pm2sadd_i16x2(rs1, rs2); +} + +// CHECK-LABEL: test_pm2sadd_x_i16x2: +// RV32: pm2sadd.hx +// RV64: pm2sadd.hx +int32_t test_pm2sadd_x_i16x2(int16x2_t rs1, int16x2_t rs2) { + return __riscv_pm2sadd_x_i16x2(rs1, rs2); +} + +// CHECK-LABEL: test_pm2sub_i16x2: +// RV32: pm2sub.h +// RV64: pm2sub.h +int32_t test_pm2sub_i16x2(int16x2_t rs1, int16x2_t rs2) { + return __riscv_pm2sub_i16x2(rs1, rs2); +} + +// CHECK-LABEL: test_pm2sub_x_i16x2: +// RV32: pm2sub.hx +// RV64: pm2sub.hx +int32_t test_pm2sub_x_i16x2(int16x2_t rs1, int16x2_t rs2) { + return __riscv_pm2sub_x_i16x2(rs1, rs2); +} + +// CHECK-LABEL: test_pm4addsu_i8x4: +// RV32: pm4addsu.b +// RV64: pm4addsu.b +int32_t test_pm4addsu_i8x4(int8x4_t rs1, uint8x4_t rs2) { + return __riscv_pm4addsu_i8x4(rs1, rs2); +} + +// CHECK-LABEL: test_pm2addsu_i16x2: +// RV32: pm2addsu.h +// RV64: pm2addsu.h +int32_t test_pm2addsu_i16x2(int16x2_t rs1, uint16x2_t rs2) { + return __riscv_pm2addsu_i16x2(rs1, rs2); +} + +// CHECK-LABEL: test_pm4add_i8x8: +// RV32: pm4add.b +// RV32: pm4add.b +// RV64: pm4add.b +int32x2_t test_pm4add_i8x8(int8x8_t rs1, int8x8_t rs2) { + return __riscv_pm4add_i8x8(rs1, rs2); +} + +// CHECK-LABEL: test_pm2add_i16x4: +// RV32: pm2add.h +// RV32: pm2add.h +// RV64: pm2add.h +int32x2_t test_pm2add_i16x4(int16x4_t rs1, int16x4_t rs2) { + return __riscv_pm2add_i16x4(rs1, rs2); +} + +// CHECK-LABEL: test_pm2add_x_i16x4: +// RV32: pm2add.hx +// RV32: pm2add.hx +// RV64: pm2add.hx +int32x2_t test_pm2add_x_i16x4(int16x4_t rs1, int16x4_t rs2) { + return __riscv_pm2add_x_i16x4(rs1, rs2); +} + +// CHECK-LABEL: test_pm4addu_u8x8: +// RV32: pm4addu.b +// RV32: pm4addu.b +// RV64: pm4addu.b +uint32x2_t test_pm4addu_u8x8(uint8x8_t rs1, uint8x8_t rs2) { + return __riscv_pm4addu_u8x8(rs1, rs2); +} + +// CHECK-LABEL: test_pm2addu_u16x4: +// RV32: pm2addu.h +// RV32: pm2addu.h +// RV64: pm2addu.h +uint32x2_t test_pm2addu_u16x4(uint16x4_t rs1, uint16x4_t rs2) { + return __riscv_pm2addu_u16x4(rs1, rs2); +} + +// CHECK-LABEL: test_pmq2add_i16x4: +// RV32: pmq2add.h +// RV32: pmq2add.h +// RV64: pmq2add.h +int32x2_t test_pmq2add_i16x4(int16x4_t rs1, int16x4_t rs2) { + return __riscv_pmq2add_i16x4(rs1, rs2); +} + +// CHECK-LABEL: test_pmqr2add_i16x4: +// RV32: pmqr2add.h +// RV32: pmqr2add.h +// RV64: pmqr2add.h +int32x2_t test_pmqr2add_i16x4(int16x4_t rs1, int16x4_t rs2) { + return __riscv_pmqr2add_i16x4(rs1, rs2); +} + +// CHECK-LABEL: test_pm2sadd_i16x4: +// RV32: pm2sadd.h +// RV32: pm2sadd.h +// RV64: pm2sadd.h +int32x2_t test_pm2sadd_i16x4(int16x4_t rs1, int16x4_t rs2) { + return __riscv_pm2sadd_i16x4(rs1, rs2); +} + +// CHECK-LABEL: test_pm2sadd_x_i16x4: +// RV32: pm2sadd.hx +// RV32: pm2sadd.hx +// RV64: pm2sadd.hx +int32x2_t test_pm2sadd_x_i16x4(int16x4_t rs1, int16x4_t rs2) { + return __riscv_pm2sadd_x_i16x4(rs1, rs2); +} + +// CHECK-LABEL: test_pm2sub_i16x4: +// RV32: pm2sub.h +// RV32: pm2sub.h +// RV64: pm2sub.h +int32x2_t test_pm2sub_i16x4(int16x4_t rs1, int16x4_t rs2) { + return __riscv_pm2sub_i16x4(rs1, rs2); +} + +// CHECK-LABEL: test_pm2sub_x_i16x4: +// RV32: pm2sub.hx +// RV32: pm2sub.hx +// RV64: pm2sub.hx +int32x2_t test_pm2sub_x_i16x4(int16x4_t rs1, int16x4_t rs2) { + return __riscv_pm2sub_x_i16x4(rs1, rs2); +} + +// CHECK-LABEL: test_pm4addsu_i8x8: +// RV32: pm4addsu.b +// RV32: pm4addsu.b +// RV64: pm4addsu.b +int32x2_t test_pm4addsu_i8x8(int8x8_t rs1, uint8x8_t rs2) { + return __riscv_pm4addsu_i8x8(rs1, rs2); +} + +// CHECK-LABEL: test_pm2addsu_i16x4: +// RV32: pm2addsu.h +// RV32: pm2addsu.h +// RV64: pm2addsu.h +int32x2_t test_pm2addsu_i16x4(int16x4_t rs1, uint16x4_t rs2) { + return __riscv_pm2addsu_i16x4(rs1, rs2); +} + +// CHECK-LABEL: test_pm2add_i32x2: +// RV32: wmul +// RV32: wma... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/218430 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
