llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Bohan (Garth) Lei (garthlei) <details> <summary>Changes</summary> This commit includes support for the ARC approved version of Zvabd (https://github.com/riscv/riscv-isa-manual/pull/3233), including code generation support and intrinsic support. Intrinsic doc: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/pull/436. In addition, the constraint `DestEEW = EEWSEWx2` is now used for widening vwabda[u] instructions for correct metadata. Assisted-by: AI --- Patch is 1.17 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/218576.diff 34 Files Affected: - (modified) clang/include/clang/Basic/riscv_vector.td (+10-4) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c (+677-26) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c (+678-26) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c (+242) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c (+243) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c (+677-26) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c (+678-26) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c (+242) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c (+243) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c (+1472-105) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c (+1494-97) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c (+486) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c (+503) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c (+1460-93) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c (+1484-87) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c (+486) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c (+503) - (modified) clang/test/Driver/print-supported-extensions-riscv.c (+1-1) - (modified) clang/test/Preprocessor/riscv-target-features.c (+3-3) - (modified) llvm/docs/RISCVUsage.md (+1-1) - (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+31-4) - (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+1-1) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td (+106-47) - (modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp (+2-2) - (modified) llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp (+4-1) - (modified) llvm/test/CodeGen/RISCV/attributes.ll (+2-2) - (modified) llvm/test/CodeGen/RISCV/rvv/vabd.ll (+49) - (modified) llvm/test/CodeGen/RISCV/rvv/vabdu.ll (+49) - (modified) llvm/test/CodeGen/RISCV/rvv/vl-opt.mir (+2-2) - (modified) llvm/test/CodeGen/RISCV/rvv/vwabda.ll (+29) - (modified) llvm/test/CodeGen/RISCV/rvv/vwabdau.ll (+29) - (modified) llvm/test/MC/RISCV/rvv/zvabd-invalid.s (+8) - (modified) llvm/test/MC/RISCV/rvv/zvabd.s (+54-9) - (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+1-1) ``````````diff diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index c5ce8b7ae8fc1..52476cb9d0f86 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -2058,17 +2058,23 @@ let UnMaskedPolicyScheme = HasPassthruOperand in { // zvabd let RequiredFeatures = ["zvabd"] in { defm vabs : RVVOutBuiltinSet<"vabs", "csil", [["v", "Uv", "Uvv"]]>; - defm vabd : RVVOutBuiltinSet<"vabd", "cs", [["vv", "Uv", "Uvvv"]]>; - defm vabdu : RVVOutBuiltinSet<"vabdu", "cs", [["vv", "Uv", "UvUvUv"]]>; + defm vabd : RVVOutOp1BuiltinSet<"vabd", "csil", + [["vv", "Uv", "Uvvv"], + ["vx", "Uv", "Uvve"]]>; + defm vabdu : RVVOutOp1BuiltinSet<"vabdu", "csil", + [["vv", "Uv", "UvUvUv"], + ["vx", "Uv", "UvUvUe"]]>; } } let UnMaskedPolicyScheme = HasPolicyOperand, HasMaskedOffOperand = false in { let RequiredFeatures = ["zvabd"] in { defm vwabda : RVVOutOp1Op2BuiltinSet<"vwabda", "cs", - [["vv", "Uw", "UwUwvv"]]>; + [["vv", "Uw", "UwUwvv"], + ["vx", "Uw", "UwUwve"]]>; defm vwabdau : RVVOutOp1Op2BuiltinSet<"vwabdau", "cs", - [["vv", "Uw", "UwUwUvUv"]]>; + [["vv", "Uw", "UwUwUvUv"], + ["vx", "Uw", "UwUwUvUe"]]>; } } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c index abd605d9c4463..73336b295f5a5 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c @@ -9,137 +9,447 @@ // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8 // CHECK-RV64-SAME: (<vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], i64 [[VL]]) // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // vuint8mf8_t test_vabd_vv_u8mf8(vint8mf8_t vs2, vint8mf8_t vs1, size_t vl) { return __riscv_vabd_vv_u8mf8(vs2, vs1, vl); } +// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8 +// CHECK-RV64-SAME: (<vscale x 1 x i8> [[VS2:%.*]], i8 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[VS2]], i8 [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] +// +vuint8mf8_t test_vabd_vx_u8mf8(vint8mf8_t vs2, int8_t rs1, size_t vl) { + return __riscv_vabd_vx_u8mf8(vs2, rs1, vl); +} + // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4 // CHECK-RV64-SAME: (<vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], i64 [[VL]]) // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // vuint8mf4_t test_vabd_vv_u8mf4(vint8mf4_t vs2, vint8mf4_t vs1, size_t vl) { return __riscv_vabd_vv_u8mf4(vs2, vs1, vl); } +// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4 +// CHECK-RV64-SAME: (<vscale x 2 x i8> [[VS2:%.*]], i8 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[VS2]], i8 [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] +// +vuint8mf4_t test_vabd_vx_u8mf4(vint8mf4_t vs2, int8_t rs1, size_t vl) { + return __riscv_vabd_vx_u8mf4(vs2, rs1, vl); +} + // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2 // CHECK-RV64-SAME: (<vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]]) // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // vuint8mf2_t test_vabd_vv_u8mf2(vint8mf2_t vs2, vint8mf2_t vs1, size_t vl) { return __riscv_vabd_vv_u8mf2(vs2, vs1, vl); } +// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2 +// CHECK-RV64-SAME: (<vscale x 4 x i8> [[VS2:%.*]], i8 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[VS2]], i8 [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] +// +vuint8mf2_t test_vabd_vx_u8mf2(vint8mf2_t vs2, int8_t rs1, size_t vl) { + return __riscv_vabd_vx_u8mf2(vs2, rs1, vl); +} + // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1 // CHECK-RV64-SAME: (<vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]]) // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // vuint8m1_t test_vabd_vv_u8m1(vint8m1_t vs2, vint8m1_t vs1, size_t vl) { return __riscv_vabd_vv_u8m1(vs2, vs1, vl); } +// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1 +// CHECK-RV64-SAME: (<vscale x 8 x i8> [[VS2:%.*]], i8 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[VS2]], i8 [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] +// +vuint8m1_t test_vabd_vx_u8m1(vint8m1_t vs2, int8_t rs1, size_t vl) { + return __riscv_vabd_vx_u8m1(vs2, rs1, vl); +} + // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2 // CHECK-RV64-SAME: (<vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]]) // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // vuint8m2_t test_vabd_vv_u8m2(vint8m2_t vs2, vint8m2_t vs1, size_t vl) { return __riscv_vabd_vv_u8m2(vs2, vs1, vl); } +// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vabd_vx_u8m2 +// CHECK-RV64-SAME: (<vscale x 16 x i8> [[VS2:%.*]], i8 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[VS2]], i8 [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] +// +vuint8m2_t test_vabd_vx_u8m2(vint8m2_t vs2, int8_t rs1, size_t vl) { + return __riscv_vabd_vx_u8m2(vs2, rs1, vl); +} + // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vabd_vv_u8m4 // CHECK-RV64-SAME: (<vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]]) // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // vuint8m4_t test_vabd_vv_u8m4(vint8m4_t vs2, vint8m4_t vs1, size_t vl) { return __riscv_vabd_vv_u8m4(vs2, vs1, vl); } +// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vabd_vx_u8m4 +// CHECK-RV64-SAME: (<vscale x 32 x i8> [[VS2:%.*]], i8 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[VS2]], i8 [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] +// +vuint8m4_t test_vabd_vx_u8m4(vint8m4_t vs2, int8_t rs1, size_t vl) { + return __riscv_vabd_vx_u8m4(vs2, rs1, vl); +} + // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vabd_vv_u8m8 // CHECK-RV64-SAME: (<vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]]) // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // vuint8m8_t test_vabd_vv_u8m8(vint8m8_t vs2, vint8m8_t vs1, size_t vl) { return __riscv_vabd_vv_u8m8(vs2, vs1, vl); } +// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vabd_vx_u8m8 +// CHECK-RV64-SAME: (<vscale x 64 x i8> [[VS2:%.*]], i8 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[VS2]], i8 [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] +// +vuint8m8_t test_vabd_vx_u8m8(vint8m8_t vs2, int8_t rs1, size_t vl) { + return __riscv_vabd_vx_u8m8(vs2, rs1, vl); +} + // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vabd_vv_u16mf4 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], i64 [[VL]]) // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // vuint16mf4_t test_vabd_vv_u16mf4(vint16mf4_t vs2, vint16mf4_t vs1, size_t vl) { return __riscv_vabd_vv_u16mf4(vs2, vs1, vl); } +// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vabd_vx_u16mf4 +// CHECK-RV64-SAME: (<vscale x 1 x i16> [[VS2:%.*]], i16 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[VS2]], i16 [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] +// +vuint16mf4_t test_vabd_vx_u16mf4(vint16mf4_t vs2, int16_t rs1, size_t vl) { + return __riscv_vabd_vx_u16mf4(vs2, rs1, vl); +} + // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vabd_vv_u16mf2 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], i64 [[VL]]) // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // vuint16mf2_t test_vabd_vv_u16mf2(vint16mf2_t vs2, vint16mf2_t vs1, size_t vl) { return __riscv_vabd_vv_u16mf2(vs2, vs1, vl); } +// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vabd_vx_u16mf2 +// CHECK-RV64-SAME: (<vscale x 2 x i16> [[VS2:%.*]], i16 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[VS2]], i16 [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] +// +vuint16mf2_t test_vabd_vx_u16mf2(vint16mf2_t vs2, int16_t rs1, size_t vl) { + return __riscv_vabd_vx_u16mf2(vs2, rs1, vl); +} + // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vabd_vv_u16m1 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], i64 [[VL]]) // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // vuint16m1_t test_vabd_vv_u16m1(vint16m1_t vs2, vint16m1_t vs1, size_t vl) { return __riscv_vabd_vv_u16m1(vs2, vs1, vl); } +// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vabd_vx_u16m1 +// CHECK-RV64-SAME: (<vscale x 4 x i16> [[VS2:%.*]], i16 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[VS2]], i16 [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] +// +vuint16m1_t test_vabd_vx_u16m1(vint16m1_t vs2, int16_t rs1, size_t vl) { + return __riscv_vabd_vx_u16m1(vs2, rs1, vl); +} + // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vabd_vv_u16m2 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], i64 [[VL]]) // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // vuint16m2_t test_vabd_vv_u16m2(vint16m2_t vs2, vint16m2_t vs1, size_t vl) { return __riscv_vabd_vv_u16m2(vs2, vs1, vl); } +// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vabd_vx_u16m2 +// CHECK-RV64-SAME: (<vscale x 8 x i16> [[VS2:%.*]], i16 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[VS2]], i16 [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] +// +vuint16m2_t test_vabd_vx_u16m2(vint16m2_t vs2, int16_t rs1, size_t vl) { + return __riscv_vabd_vx_u16m2(vs2, rs1, vl); +} + // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vabd_vv_u16m4 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], i64 [[VL]]) // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // vuint16m4_t test_vabd_vv_u16m4(vint16m4_t vs2, vint16m4_t vs1, size_t vl) { return __riscv_vabd_vv_u16m4(vs2, vs1, vl); } +// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vabd_vx_u16m4 +// CHECK-RV64-SAME: (<vscale x 16 x i16> [[VS2:%.*]], i16 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[VS2]], i16 [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] +// +vuint16m4_t test_vabd_vx_u16m4(vint16m4_t vs2, int16_t rs1, size_t vl) { + return __riscv_vabd_vx_u16m4(vs2, rs1, vl); +} + // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vabd_vv_u16m8 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[VS2:%.*]], <vscale x 32 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vabd.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[VS2]], <vscale x 32 x i16> [[VS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vabd.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[VS2]], <vscale x 32 x i16> [[VS1]], i64 [[VL]]) // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // vuint16m8_t test_vabd_vv_u16m8(vint16m8_t vs2, vint16m8_t vs1, size_t vl) { return __riscv_vabd_vv_u16m8(vs2, vs1, vl); } +// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vabd_vx_u16m8 +// CHECK-RV64-SAME: (<vscale x 32 x i16> [[VS2:%.*]], i16 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vabd.nxv32i16.i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[VS2]], i16 [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] +// +vuint16m8_t test_vabd_vx_u16m8(vint16m8_t vs2, int16_t rs1, size_t vl) { + return __riscv_vabd_vx_u16m8(vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vabd_vv_u32mf2 +// CHECK-RV64-SAME: (<vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vabd.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison,... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/218576 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
