================
@@ -7048,24 +7071,67 @@ static SDValue combineF16AddWithNeg(SDNode *N,
SelectionDAG &DAG,
return SDValue();
}
- SDLoc DL(N);
- return DAG.getNode(getF16SubOpc(AddIntrinsicID), DL, N->getValueType(0),
- SubOp1, SubOp2);
+ return DAG.getNode(Opc, SDLoc(N), VT, SubOp1, SubOp2);
+}
+
+static bool isSupportedFAdd(EVT VT, const NVPTXSubtarget &STI,
+ Intrinsic::ID IID,
+ APFloat::roundingMode RoundingMode) {
+ if (VT.isVector() && VT.getVectorElementCount() != ElementCount::getFixed(2))
+ return false;
+
+ const bool IsRN = RoundingMode == APFloat::rmNearestTiesToEven;
+ const bool IsFTZ = nvvm::FAddShouldFTZ(IID);
+ const bool IsSat = nvvm::FAddShouldSaturate(IID);
+ switch (VT.getScalarType().getSimpleVT().SimpleTy) {
+ case MVT::f16:
+ return IsRN;
+ case MVT::bf16:
+ return IsRN && !IsSat && !IsFTZ && STI.hasNativeBF16Support(ISD::FADD);
+ case MVT::f32:
+ return !VT.isVector() || (!IsSat && STI.hasF32x2Instructions());
+ case MVT::f64:
+ return !VT.isVector() && !IsSat && !IsFTZ;
+ default:
+ return false;
+ }
+}
+
+static SDValue diagnoseInvalidFAdd(SDNode *N, SelectionDAG &DAG,
----------------
LewisCrawford wrote:
If we're going to block these invalid patterns here, should we add some checks
at the IRValidator level too?
Would llvm_unreachable or report_fatal_error be better here rather than
returning Poison? Or would it be better to try and add legalizer expansions for
the invalid flag/type combinations?
https://github.com/llvm/llvm-project/pull/217336
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