RKSimon wrote: Please consult the AMD APMs - IIRC VFRCZSS/SD are weird in that they zero the upper elements, not pass through the other argument like typical SSE scalar instructions. I don't have a XOP machine available at the moment to test this.....
Does GCC/MSVC respect this or do they perform a MOVSS/SD to blend with the result? https://github.com/llvm/llvm-project/pull/219863 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
