llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Hongyu Chen (XChy) <details> <summary>Changes</summary> See also https://github.com/riscv/riscv-p-spec/blob/master/P-ext-intrinsics.adoc#packed-element-extract. --- Full diff: https://github.com/llvm/llvm-project/pull/221565.diff 3 Files Affected: - (modified) clang/lib/Headers/riscv_packed_simd.h (+24) - (modified) clang/test/CodeGen/RISCV/rvp-intrinsics.c (+182) - (modified) cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c (+86) ``````````diff diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h index bb0e7624a50e9..7f75a5ef3e5fd 100644 --- a/clang/lib/Headers/riscv_packed_simd.h +++ b/clang/lib/Headers/riscv_packed_simd.h @@ -66,6 +66,15 @@ typedef uint32_t uint32x2_t __attribute__((__vector_size__(8))); return op __rs1; \ } +#define __packed_extract(name, rty, ty, max_idx) \ + static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name( \ + ty __v, const unsigned __idx) \ + __attribute__((__enable_if__( \ + __idx <= (max_idx), \ + "index must be a constant integer from 0 to " #max_idx))) { \ + return __v[__idx]; \ + } + #define __packed_binary_builtin(name, ty, builtin) \ static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \ return builtin(__rs1, __rs2); \ @@ -989,6 +998,20 @@ __packed_binary_builtin_cast(pnclipup_u16x4, uint32x2_t, uint16x4_t, __builtin_r __packed_binary_builtin_cast(pnclipp_i32x2, int64_t, int32x2_t, __builtin_riscv_pnclipp_i32x2) __packed_binary_builtin_cast(pnclipup_u32x2, uint64_t, uint32x2_t, __builtin_riscv_pnclipup_u32x2) +/* Packed Element Extract (32-bit) */ +__packed_extract(pget_i8x4_i8, int8_t, int8x4_t, 3) +__packed_extract(pget_u8x4_u8, uint8_t, uint8x4_t, 3) +__packed_extract(pget_i16x2_i16, int16_t, int16x2_t, 1) +__packed_extract(pget_u16x2_u16, uint16_t, uint16x2_t, 1) + +/* Packed Element Extract (64-bit) */ +__packed_extract(pget_i8x8_i8, int8_t, int8x8_t, 7) +__packed_extract(pget_u8x8_u8, uint8_t, uint8x8_t, 7) +__packed_extract(pget_i16x4_i16, int16_t, int16x4_t, 3) +__packed_extract(pget_u16x4_u16, uint16_t, uint16x4_t, 3) +__packed_extract(pget_i32x2_i32, int32_t, int32x2_t, 1) +__packed_extract(pget_u32x2_u32, uint32_t, uint32x2_t, 1) + /* Reinterpret Casts, Packed <-> Scalar (32-bit) */ __packed_reinterpret(u8x4_u32, uint32_t, uint8x4_t) __packed_reinterpret(u16x2_u32, uint32_t, uint16x2_t) @@ -1137,6 +1160,7 @@ __packed_reinterpret(u32x2_i32x2, int32x2_t, uint32x2_t) #undef __packed_nziph4 #undef __packed_abdsum #undef __packed_ternary_builtin_cast +#undef __packed_extract #undef __packed_reinterpret #undef __DEFAULT_FN_ATTRS diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c index 9453a07e89ce7..7589157c38754 100644 --- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c +++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c @@ -10701,3 +10701,185 @@ int64_t test_mqracc_w01_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { int64_t test_mqracc_w11_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { return __riscv_mqracc_w11_i64(rd, rs1, rs2); } + +/* Packed Element Extract */ + +// RV32-LABEL: define dso_local signext i8 @test_pget_i8x4_i8( +// RV32-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 24 +// RV32-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i8 +// RV32-NEXT: ret i8 [[VECEXT_I]] +// +// RV64-LABEL: define dso_local signext i8 @test_pget_i8x4_i8( +// RV64-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 24 +// RV64-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i8 +// RV64-NEXT: ret i8 [[VECEXT_I]] +// +int8_t test_pget_i8x4_i8(int8x4_t v) { + return __riscv_pget_i8x4_i8(v, 3); +} + +// RV32-LABEL: define dso_local zeroext i8 @test_pget_u8x4_u8( +// RV32-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 24 +// RV32-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i8 +// RV32-NEXT: ret i8 [[VECEXT_I]] +// +// RV64-LABEL: define dso_local zeroext i8 @test_pget_u8x4_u8( +// RV64-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 24 +// RV64-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i8 +// RV64-NEXT: ret i8 [[VECEXT_I]] +// +uint8_t test_pget_u8x4_u8(uint8x4_t v) { + return __riscv_pget_u8x4_u8(v, 3); +} + +// RV32-LABEL: define dso_local signext i16 @test_pget_i16x2_i16( +// RV32-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 16 +// RV32-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i16 +// RV32-NEXT: ret i16 [[VECEXT_I]] +// +// RV64-LABEL: define dso_local signext i16 @test_pget_i16x2_i16( +// RV64-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 16 +// RV64-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i16 +// RV64-NEXT: ret i16 [[VECEXT_I]] +// +int16_t test_pget_i16x2_i16(int16x2_t v) { + return __riscv_pget_i16x2_i16(v, 1); +} + +// RV32-LABEL: define dso_local zeroext i16 @test_pget_u16x2_u16( +// RV32-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 16 +// RV32-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i16 +// RV32-NEXT: ret i16 [[VECEXT_I]] +// +// RV64-LABEL: define dso_local zeroext i16 @test_pget_u16x2_u16( +// RV64-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[V_COERCE]], 16 +// RV64-NEXT: [[VECEXT_I:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i16 +// RV64-NEXT: ret i16 [[VECEXT_I]] +// +uint16_t test_pget_u16x2_u16(uint16x2_t v) { + return __riscv_pget_u16x2_u16(v, 1); +} + +// RV32-LABEL: define dso_local signext i8 @test_pget_i8x8_i8( +// RV32-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8> +// RV32-NEXT: [[VECEXT_I:%.*]] = extractelement <8 x i8> [[TMP0]], i64 7 +// RV32-NEXT: ret i8 [[VECEXT_I]] +// +// RV64-LABEL: define dso_local signext i8 @test_pget_i8x8_i8( +// RV64-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i64 [[V_COERCE]], 56 +// RV64-NEXT: [[VECEXT_I:%.*]] = trunc nuw i64 [[EXTELT_OFFSET]] to i8 +// RV64-NEXT: ret i8 [[VECEXT_I]] +// +int8_t test_pget_i8x8_i8(int8x8_t v) { + return __riscv_pget_i8x8_i8(v, 7); +} + +// RV32-LABEL: define dso_local zeroext i8 @test_pget_u8x8_u8( +// RV32-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8> +// RV32-NEXT: [[VECEXT_I:%.*]] = extractelement <8 x i8> [[TMP0]], i64 7 +// RV32-NEXT: ret i8 [[VECEXT_I]] +// +// RV64-LABEL: define dso_local zeroext i8 @test_pget_u8x8_u8( +// RV64-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i64 [[V_COERCE]], 56 +// RV64-NEXT: [[VECEXT_I:%.*]] = trunc nuw i64 [[EXTELT_OFFSET]] to i8 +// RV64-NEXT: ret i8 [[VECEXT_I]] +// +uint8_t test_pget_u8x8_u8(uint8x8_t v) { + return __riscv_pget_u8x8_u8(v, 7); +} + +// RV32-LABEL: define dso_local signext i16 @test_pget_i16x4_i16( +// RV32-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16> +// RV32-NEXT: [[VECEXT_I:%.*]] = extractelement <4 x i16> [[TMP0]], i64 3 +// RV32-NEXT: ret i16 [[VECEXT_I]] +// +// RV64-LABEL: define dso_local signext i16 @test_pget_i16x4_i16( +// RV64-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i64 [[V_COERCE]], 48 +// RV64-NEXT: [[VECEXT_I:%.*]] = trunc nuw i64 [[EXTELT_OFFSET]] to i16 +// RV64-NEXT: ret i16 [[VECEXT_I]] +// +int16_t test_pget_i16x4_i16(int16x4_t v) { + return __riscv_pget_i16x4_i16(v, 3); +} + +// RV32-LABEL: define dso_local zeroext i16 @test_pget_u16x4_u16( +// RV32-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16> +// RV32-NEXT: [[VECEXT_I:%.*]] = extractelement <4 x i16> [[TMP0]], i64 3 +// RV32-NEXT: ret i16 [[VECEXT_I]] +// +// RV64-LABEL: define dso_local zeroext i16 @test_pget_u16x4_u16( +// RV64-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i64 [[V_COERCE]], 48 +// RV64-NEXT: [[VECEXT_I:%.*]] = trunc nuw i64 [[EXTELT_OFFSET]] to i16 +// RV64-NEXT: ret i16 [[VECEXT_I]] +// +uint16_t test_pget_u16x4_u16(uint16x4_t v) { + return __riscv_pget_u16x4_u16(v, 3); +} + +// RV32-LABEL: define dso_local i32 @test_pget_i32x2_i32( +// RV32-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <2 x i32> +// RV32-NEXT: [[VECEXT_I:%.*]] = extractelement <2 x i32> [[TMP0]], i64 1 +// RV32-NEXT: ret i32 [[VECEXT_I]] +// +// RV64-LABEL: define dso_local signext i32 @test_pget_i32x2_i32( +// RV64-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i64 [[V_COERCE]], 32 +// RV64-NEXT: [[VECEXT_I:%.*]] = trunc nuw i64 [[EXTELT_OFFSET]] to i32 +// RV64-NEXT: ret i32 [[VECEXT_I]] +// +int32_t test_pget_i32x2_i32(int32x2_t v) { + return __riscv_pget_i32x2_i32(v, 1); +} + +// RV32-LABEL: define dso_local i32 @test_pget_u32x2_u32( +// RV32-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <2 x i32> +// RV32-NEXT: [[VECEXT_I:%.*]] = extractelement <2 x i32> [[TMP0]], i64 1 +// RV32-NEXT: ret i32 [[VECEXT_I]] +// +// RV64-LABEL: define dso_local signext i32 @test_pget_u32x2_u32( +// RV64-SAME: i64 noundef [[V_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i64 [[V_COERCE]], 32 +// RV64-NEXT: [[VECEXT_I:%.*]] = trunc nuw i64 [[EXTELT_OFFSET]] to i32 +// RV64-NEXT: ret i32 [[VECEXT_I]] +// +uint32_t test_pget_u32x2_u32(uint32x2_t v) { + return __riscv_pget_u32x2_u32(v, 1); +} diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c index d76b2b0a4c7db..3a1045a8b94f1 100644 --- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c +++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c @@ -4172,3 +4172,89 @@ int64_t test_mulsu_w00_i64(int32x2_t a, uint32x2_t b) { int64_t test_mulsu_w11_i64(int32x2_t a, uint32x2_t b) { return __riscv_mulsu_w11_i64(a, b); } + +// CHECK-LABEL: test_pget_i8x4_i8: +// CHECK: srai +int8_t test_pget_i8x4_i8(int8x4_t v) { + return __riscv_pget_i8x4_i8(v, 3); +} + +// CHECK-LABEL: test_pget_i8x4_i8_idx0: +// CHECK: sext.b +int8_t test_pget_i8x4_i8_idx0(int8x4_t v) { + return __riscv_pget_i8x4_i8(v, 0); +} + +// CHECK-LABEL: test_pget_u8x4_u8: +// CHECK: srli +uint8_t test_pget_u8x4_u8(uint8x4_t v) { + return __riscv_pget_u8x4_u8(v, 3); +} + +// CHECK-LABEL: test_pget_u8x4_u8_idx0: +// CHECK: zext.b +uint8_t test_pget_u8x4_u8_idx0(uint8x4_t v) { + return __riscv_pget_u8x4_u8(v, 0); +} + +// CHECK-LABEL: test_pget_i16x2_i16: +// CHECK: srai +int16_t test_pget_i16x2_i16(int16x2_t v) { + return __riscv_pget_i16x2_i16(v, 1); +} + +// CHECK-LABEL: test_pget_i16x2_i16_idx0: +// CHECK: sext.h +int16_t test_pget_i16x2_i16_idx0(int16x2_t v) { + return __riscv_pget_i16x2_i16(v, 0); +} + +// CHECK-LABEL: test_pget_u16x2_u16: +// CHECK: srli +uint16_t test_pget_u16x2_u16(uint16x2_t v) { + return __riscv_pget_u16x2_u16(v, 1); +} + +// CHECK-LABEL: test_pget_u16x2_u16_idx0: +// CHECK: zext.h +uint16_t test_pget_u16x2_u16_idx0(uint16x2_t v) { + return __riscv_pget_u16x2_u16(v, 0); +} + +// CHECK-LABEL: test_pget_i8x8_i8: +// CHECK: srai +int8_t test_pget_i8x8_i8(int8x8_t v) { + return __riscv_pget_i8x8_i8(v, 7); +} + +// CHECK-LABEL: test_pget_u8x8_u8: +// CHECK: srli +uint8_t test_pget_u8x8_u8(uint8x8_t v) { + return __riscv_pget_u8x8_u8(v, 7); +} + +// CHECK-LABEL: test_pget_i16x4_i16: +// CHECK: srai +int16_t test_pget_i16x4_i16(int16x4_t v) { + return __riscv_pget_i16x4_i16(v, 3); +} + +// CHECK-LABEL: test_pget_u16x4_u16: +// CHECK: srli +uint16_t test_pget_u16x4_u16(uint16x4_t v) { + return __riscv_pget_u16x4_u16(v, 3); +} + +// CHECK-LABEL: test_pget_i32x2_i32: +// RV32: mv +// RV64: srai +int32_t test_pget_i32x2_i32(int32x2_t v) { + return __riscv_pget_i32x2_i32(v, 1); +} + +// CHECK-LABEL: test_pget_u32x2_u32: +// RV32: mv +// RV64: srai +uint32_t test_pget_u32x2_u32(uint32x2_t v) { + return __riscv_pget_u32x2_u32(v, 1); +} `````````` </details> https://github.com/llvm/llvm-project/pull/221565 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
