https://github.com/TelGome created https://github.com/llvm/llvm-project/pull/222268
This pr support [Packed Element Insert](https://github.com/riscv/riscv-p-spec/blob/master/P-ext-intrinsics.adoc#packed-element-insert) >From 224e4a3a3facd911a72bd71971e392d2c37d8411 Mon Sep 17 00:00:00 2001 From: Dongyan Chen <[email protected]> Date: Wed, 9 Sep 2026 10:20:58 +0800 Subject: [PATCH] [RISCV][P-ext] Support Packed Element Insert --- clang/lib/Headers/riscv_packed_simd.h | 26 +++ clang/test/CodeGen/RISCV/rvp-intrinsics.c | 204 ++++++++++++++++++ .../test/Sema/riscv-pset-index-out-of-range.c | 33 +++ .../riscv_packed_simd.c | 66 ++++++ 4 files changed, 329 insertions(+) create mode 100644 clang/test/Sema/riscv-pset-index-out-of-range.c diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h index 37ac140780d02..3a5b33f8c5a77 100644 --- a/clang/lib/Headers/riscv_packed_simd.h +++ b/clang/lib/Headers/riscv_packed_simd.h @@ -312,6 +312,17 @@ typedef uint32_t uint32x2_t __attribute__((__vector_size__(8))); return __builtin_bit_cast(rty, __x); \ } +#define __packed_insert(name, ty, elt_ty, max_idx) \ + static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __v, elt_ty __e, \ + unsigned __idx) \ + __attribute__((__enable_if__( \ + __idx <= (max_idx), \ + "index must be a constant integer from 0 to " #max_idx))) { \ + ty __r = __v; \ + __r[__idx] = __e; \ + return __r; \ + } + // clang-format off: macro call sites have no trailing semicolons, which // confuses clang-format into a deeply nested expression. @@ -565,6 +576,20 @@ __packed_binary_builtin_mixed(psshl_s_u32x2, uint32x2_t, uint32x2_t, int, __buil __packed_binary_builtin_mixed(psshlr_s_u16x4, uint16x4_t, uint16x4_t, int, __builtin_riscv_psshlr_s_u16x4) __packed_binary_builtin_mixed(psshlr_s_u32x2, uint32x2_t, uint32x2_t, int, __builtin_riscv_psshlr_s_u32x2) +/* Packed Element Insert (32-bit) */ +__packed_insert(pset_i8_i8x4, int8x4_t, int8_t, 3) +__packed_insert(pset_u8_u8x4, uint8x4_t, uint8_t, 3) +__packed_insert(pset_i16_i16x2, int16x2_t, int16_t, 1) +__packed_insert(pset_u16_u16x2, uint16x2_t, uint16_t, 1) + +/* Packed Element Insert (64-bit) */ +__packed_insert(pset_i8_i8x8, int8x8_t, int8_t, 7) +__packed_insert(pset_u8_u8x8, uint8x8_t, uint8_t, 7) +__packed_insert(pset_i16_i16x4, int16x4_t, int16_t, 3) +__packed_insert(pset_u16_u16x4, uint16x4_t, uint16_t, 3) +__packed_insert(pset_i32_i32x2, int32x2_t, int32_t, 1) +__packed_insert(pset_u32_u32x2, uint32x2_t, uint32_t, 1) + /* Packed Logical Operations (32-bit) */ __packed_binary_op(pand_i8x4, int8x4_t, &) __packed_binary_op(pand_u8x4, uint8x4_t, &) @@ -1161,6 +1186,7 @@ __packed_reinterpret(u32x2_i32x2, int32x2_t, uint32x2_t) #undef __packed_abdsum #undef __packed_ternary_builtin_cast #undef __packed_extract +#undef __packed_insert #undef __packed_reinterpret #undef __DEFAULT_FN_ATTRS diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c index 7589157c38754..5a224a3079e79 100644 --- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c +++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c @@ -10883,3 +10883,207 @@ int32_t test_pget_i32x2_i32(int32x2_t v) { uint32_t test_pget_u32x2_u32(uint32x2_t v) { return __riscv_pget_u32x2_u32(v, 1); } + +/* Packed Element Insert (32-bit) */ + +// RV32-LABEL: define dso_local i32 @test_pset_i8_i8x4( +// RV32-SAME: i32 noundef [[V_COERCE:%.*]], i8 noundef signext [[E:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[V_COERCE]] to <4 x i8> +// RV32-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[E]], i64 2 +// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[VECINS_I]] to i32 +// RV32-NEXT: ret i32 [[TMP1]] +// +// RV64-LABEL: define dso_local i32 @test_pset_i8_i8x4( +// RV64-SAME: i32 noundef [[V_COERCE:%.*]], i8 noundef signext [[E:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[V_COERCE]] to <4 x i8> +// RV64-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[E]], i64 2 +// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[VECINS_I]] to i32 +// RV64-NEXT: ret i32 [[TMP1]] +// +int8x4_t test_pset_i8_i8x4(int8x4_t v, int8_t e) { + return __riscv_pset_i8_i8x4(v, e, 2); +} + +// RV32-LABEL: define dso_local i32 @test_pset_u8_u8x4( +// RV32-SAME: i32 noundef [[V_COERCE:%.*]], i8 noundef zeroext [[E:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[V_COERCE]] to <4 x i8> +// RV32-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[E]], i64 3 +// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[VECINS_I]] to i32 +// RV32-NEXT: ret i32 [[TMP1]] +// +// RV64-LABEL: define dso_local i32 @test_pset_u8_u8x4( +// RV64-SAME: i32 noundef [[V_COERCE:%.*]], i8 noundef zeroext [[E:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[V_COERCE]] to <4 x i8> +// RV64-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[E]], i64 3 +// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[VECINS_I]] to i32 +// RV64-NEXT: ret i32 [[TMP1]] +// +uint8x4_t test_pset_u8_u8x4(uint8x4_t v, uint8_t e) { + return __riscv_pset_u8_u8x4(v, e, 3); +} + +// RV32-LABEL: define dso_local i32 @test_pset_i16_i16x2( +// RV32-SAME: i32 noundef [[V_COERCE:%.*]], i16 noundef signext [[E:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[V_COERCE]] to <2 x i16> +// RV32-NEXT: [[VECINS_I:%.*]] = insertelement <2 x i16> [[TMP0]], i16 [[E]], i64 1 +// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[VECINS_I]] to i32 +// RV32-NEXT: ret i32 [[TMP1]] +// +// RV64-LABEL: define dso_local i32 @test_pset_i16_i16x2( +// RV64-SAME: i32 noundef [[V_COERCE:%.*]], i16 noundef signext [[E:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[V_COERCE]] to <2 x i16> +// RV64-NEXT: [[VECINS_I:%.*]] = insertelement <2 x i16> [[TMP0]], i16 [[E]], i64 1 +// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[VECINS_I]] to i32 +// RV64-NEXT: ret i32 [[TMP1]] +// +int16x2_t test_pset_i16_i16x2(int16x2_t v, int16_t e) { + return __riscv_pset_i16_i16x2(v, e, 1); +} + +// RV32-LABEL: define dso_local i32 @test_pset_u16_u16x2( +// RV32-SAME: i32 noundef [[V_COERCE:%.*]], i16 noundef zeroext [[E:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = and i32 [[V_COERCE]], -65536 +// RV32-NEXT: [[TMP1:%.*]] = zext i16 [[E]] to i32 +// RV32-NEXT: [[TMP2:%.*]] = or disjoint i32 [[TMP0]], [[TMP1]] +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local i32 @test_pset_u16_u16x2( +// RV64-SAME: i32 noundef [[V_COERCE:%.*]], i16 noundef zeroext [[E:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = and i32 [[V_COERCE]], -65536 +// RV64-NEXT: [[TMP1:%.*]] = zext i16 [[E]] to i32 +// RV64-NEXT: [[TMP2:%.*]] = or disjoint i32 [[TMP0]], [[TMP1]] +// RV64-NEXT: ret i32 [[TMP2]] +// +uint16x2_t test_pset_u16_u16x2(uint16x2_t v, uint16_t e) { + return __riscv_pset_u16_u16x2(v, e, 0); +} + +/* Packed Element Insert (64-bit) */ + +// RV32-LABEL: define dso_local i64 @test_pset_i8_i8x8( +// RV32-SAME: i64 noundef [[V_COERCE:%.*]], i8 noundef signext [[E:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8> +// RV32-NEXT: [[VECINS_I:%.*]] = insertelement <8 x i8> [[TMP0]], i8 [[E]], i64 5 +// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VECINS_I]] to i64 +// RV32-NEXT: ret i64 [[TMP1]] +// +// RV64-LABEL: define dso_local i64 @test_pset_i8_i8x8( +// RV64-SAME: i64 noundef [[V_COERCE:%.*]], i8 noundef signext [[E:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8> +// RV64-NEXT: [[VECINS_I:%.*]] = insertelement <8 x i8> [[TMP0]], i8 [[E]], i64 5 +// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VECINS_I]] to i64 +// RV64-NEXT: ret i64 [[TMP1]] +// +int8x8_t test_pset_i8_i8x8(int8x8_t v, int8_t e) { + return __riscv_pset_i8_i8x8(v, e, 5); +} + +// RV32-LABEL: define dso_local i64 @test_pset_u8_u8x8( +// RV32-SAME: i64 noundef [[V_COERCE:%.*]], i8 noundef zeroext [[E:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8> +// RV32-NEXT: [[VECINS_I:%.*]] = insertelement <8 x i8> [[TMP0]], i8 [[E]], i64 7 +// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VECINS_I]] to i64 +// RV32-NEXT: ret i64 [[TMP1]] +// +// RV64-LABEL: define dso_local i64 @test_pset_u8_u8x8( +// RV64-SAME: i64 noundef [[V_COERCE:%.*]], i8 noundef zeroext [[E:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <8 x i8> +// RV64-NEXT: [[VECINS_I:%.*]] = insertelement <8 x i8> [[TMP0]], i8 [[E]], i64 7 +// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[VECINS_I]] to i64 +// RV64-NEXT: ret i64 [[TMP1]] +// +uint8x8_t test_pset_u8_u8x8(uint8x8_t v, uint8_t e) { + return __riscv_pset_u8_u8x8(v, e, 7); +} + +// RV32-LABEL: define dso_local i64 @test_pset_i16_i16x4( +// RV32-SAME: i64 noundef [[V_COERCE:%.*]], i16 noundef signext [[E:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16> +// RV32-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i16> [[TMP0]], i16 [[E]], i64 3 +// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINS_I]] to i64 +// RV32-NEXT: ret i64 [[TMP1]] +// +// RV64-LABEL: define dso_local i64 @test_pset_i16_i16x4( +// RV64-SAME: i64 noundef [[V_COERCE:%.*]], i16 noundef signext [[E:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16> +// RV64-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i16> [[TMP0]], i16 [[E]], i64 3 +// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINS_I]] to i64 +// RV64-NEXT: ret i64 [[TMP1]] +// +int16x4_t test_pset_i16_i16x4(int16x4_t v, int16_t e) { + return __riscv_pset_i16_i16x4(v, e, 3); +} + +// RV32-LABEL: define dso_local i64 @test_pset_u16_u16x4( +// RV32-SAME: i64 noundef [[V_COERCE:%.*]], i16 noundef zeroext [[E:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16> +// RV32-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i16> [[TMP0]], i16 [[E]], i64 2 +// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINS_I]] to i64 +// RV32-NEXT: ret i64 [[TMP1]] +// +// RV64-LABEL: define dso_local i64 @test_pset_u16_u16x4( +// RV64-SAME: i64 noundef [[V_COERCE:%.*]], i16 noundef zeroext [[E:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <4 x i16> +// RV64-NEXT: [[VECINS_I:%.*]] = insertelement <4 x i16> [[TMP0]], i16 [[E]], i64 2 +// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[VECINS_I]] to i64 +// RV64-NEXT: ret i64 [[TMP1]] +// +uint16x4_t test_pset_u16_u16x4(uint16x4_t v, uint16_t e) { + return __riscv_pset_u16_u16x4(v, e, 2); +} + +// RV32-LABEL: define dso_local i64 @test_pset_i32_i32x2( +// RV32-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[E:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <2 x i32> +// RV32-NEXT: [[VECINS_I:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[E]], i64 1 +// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINS_I]] to i64 +// RV32-NEXT: ret i64 [[TMP1]] +// +// RV64-LABEL: define dso_local i64 @test_pset_i32_i32x2( +// RV64-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef signext [[E:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <2 x i32> +// RV64-NEXT: [[VECINS_I:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[E]], i64 1 +// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINS_I]] to i64 +// RV64-NEXT: ret i64 [[TMP1]] +// +int32x2_t test_pset_i32_i32x2(int32x2_t v, int32_t e) { + return __riscv_pset_i32_i32x2(v, e, 1); +} + +// RV32-LABEL: define dso_local i64 @test_pset_u32_u32x2( +// RV32-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef [[E:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[V_COERCE]] to <2 x i32> +// RV32-NEXT: [[VECINS_I:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[E]], i64 0 +// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[VECINS_I]] to i64 +// RV32-NEXT: ret i64 [[TMP1]] +// +// RV64-LABEL: define dso_local i64 @test_pset_u32_u32x2( +// RV64-SAME: i64 noundef [[V_COERCE:%.*]], i32 noundef signext [[E:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = and i64 [[V_COERCE]], -4294967296 +// RV64-NEXT: [[TMP1:%.*]] = zext i32 [[E]] to i64 +// RV64-NEXT: [[TMP2:%.*]] = or disjoint i64 [[TMP0]], [[TMP1]] +// RV64-NEXT: ret i64 [[TMP2]] +// +uint32x2_t test_pset_u32_u32x2(uint32x2_t v, uint32_t e) { + return __riscv_pset_u32_u32x2(v, e, 0); +} diff --git a/clang/test/Sema/riscv-pset-index-out-of-range.c b/clang/test/Sema/riscv-pset-index-out-of-range.c new file mode 100644 index 0000000000000..72bac2973c6f8 --- /dev/null +++ b/clang/test/Sema/riscv-pset-index-out-of-range.c @@ -0,0 +1,33 @@ +// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-p \ +// RUN: -fsyntax-only -verify -verify-ignore-unexpected=note %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-p \ +// RUN: -fsyntax-only -verify -verify-ignore-unexpected=note %s + +#include <riscv_packed_simd.h> + +// expected-note@*:* {{candidate disabled: index must be a constant integer from 0 to 3}} +// expected-note@*:* {{candidate disabled: index must be a constant integer from 0 to 1}} +// expected-note@*:* {{candidate disabled: index must be a constant integer from 0 to 7}} +int16x2_t test_pset_nonconstant(int16x2_t v, int16_t e, unsigned idx) { + // expected-error@+1 {{no matching function for call to '__riscv_pset_i16_i16x2'}} + return __riscv_pset_i16_i16x2(v, e, idx); +} + +int16x2_t test_pset_i16_i16x2_ok(int16x2_t v, int16_t e) { + return __riscv_pset_i16_i16x2(v, e, 1); +} + +int16x2_t test_pset_i16_i16x2_out_of_range(int16x2_t v, int16_t e) { + // expected-error@+1 {{no matching function for call to '__riscv_pset_i16_i16x2'}} + return __riscv_pset_i16_i16x2(v, e, 2); +} + +uint8x4_t test_pset_u8_u8x4_out_of_range(uint8x4_t v, uint8_t e) { + // expected-error@+1 {{no matching function for call to '__riscv_pset_u8_u8x4'}} + return __riscv_pset_u8_u8x4(v, e, 4); +} + +uint8x8_t test_pset_u8_u8x8_out_of_range(uint8x8_t v, uint8_t e) { + // expected-error@+1 {{no matching function for call to '__riscv_pset_u8_u8x8'}} + return __riscv_pset_u8_u8x8(v, e, 8); +} diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c index 48fcf036794ff..bfba1891432af 100644 --- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c +++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c @@ -4248,3 +4248,69 @@ int32_t test_pget_i32x2_i32(int32x2_t v) { uint32_t test_pget_u32x2_u32(uint32x2_t v) { return __riscv_pget_u32x2_u32(v, 1); } + +// CHECK-LABEL: test_pset_i8_i8x4: +// CHECK: mvm +int8x4_t test_pset_i8_i8x4(int8x4_t v, int8_t e) { + return __riscv_pset_i8_i8x4(v, e, 2); +} + +// CHECK-LABEL: test_pset_u8_u8x4: +// CHECK: mvm +uint8x4_t test_pset_u8_u8x4(uint8x4_t v, uint8_t e) { + return __riscv_pset_u8_u8x4(v, e, 3); +} + +// CHECK-LABEL: test_pset_i16_i16x2: +// RV32: pack +// RV64: mvm +int16x2_t test_pset_i16_i16x2(int16x2_t v, int16_t e) { + return __riscv_pset_i16_i16x2(v, e, 1); +} + +// CHECK-LABEL: test_pset_u16_u16x2: +// CHECK: and +// CHECK: or +uint16x2_t test_pset_u16_u16x2(uint16x2_t v, uint16_t e) { + return __riscv_pset_u16_u16x2(v, e, 0); +} + +// CHECK-LABEL: test_pset_i8_i8x8: +// CHECK: mvm +int8x8_t test_pset_i8_i8x8(int8x8_t v, int8_t e) { + return __riscv_pset_i8_i8x8(v, e, 5); +} + +// CHECK-LABEL: test_pset_u8_u8x8: +// CHECK: mvm +uint8x8_t test_pset_u8_u8x8(uint8x8_t v, uint8_t e) { + return __riscv_pset_u8_u8x8(v, e, 7); +} + +// CHECK-LABEL: test_pset_i16_i16x4: +// RV32: pack +// RV64: mvm +int16x4_t test_pset_i16_i16x4(int16x4_t v, int16_t e) { + return __riscv_pset_i16_i16x4(v, e, 3); +} + +// CHECK-LABEL: test_pset_u16_u16x4: +// RV32: pack +// RV64: mvm +uint16x4_t test_pset_u16_u16x4(uint16x4_t v, uint16_t e) { + return __riscv_pset_u16_u16x4(v, e, 2); +} + +// CHECK-LABEL: test_pset_i32_i32x2: +// RV32: mv{{[[:space:]]}} +// RV64: pack +int32x2_t test_pset_i32_i32x2(int32x2_t v, int32_t e) { + return __riscv_pset_i32_i32x2(v, e, 1); +} + +// CHECK-LABEL: test_pset_u32_u32x2: +// RV32: mv{{[[:space:]]}} +// RV64: add.uw +uint32x2_t test_pset_u32_u32x2(uint32x2_t v, uint32_t e) { + return __riscv_pset_u32_u32x2(v, e, 0); +} _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
