================
@@ -16,31 +16,76 @@ internally by the compiler. A thread that initiates one or
more async operations
An *asyncmark* created by a thread can be used to track async operations
initiated by that thread.
+### Stages
+
+A *stage* names a kind of async operation. Each async operation *belongs to*
the
+one stage determined by the instruction that initiates it.
+
+The stages are:
+
+| Bit | Stage | Async operations |
+|---|---|---|
+| 0 | `TENSOR` | tensor loads and stores |
+| 1 | `GLOBAL_LOAD_ASYNC_TO_LDS` | global loads async to LDS |
+| 2 | `GLOBAL_LOAD_ASYNC_TO_LDS_MCAST` | multicast (cluster) global loads
async to LDS |
+| 3 | `GLOBAL_STORE_ASYNC_FROM_LDS` | async global stores from LDS |
+| 5 | `BUFFER_GLOBAL_LOAD` | buffer loads to LDS and pre-gfx1250 global loads
to LDS |
+
+Bits 4 and 6 through 10 are reserved for future async operations, and no
+operation belongs to them yet.
+
+Which async operations a given subtarget actually has is described in
+{ref}`AMDGPU DMA Operations <amdgpu-dma-operations>`. A stage exists on every
+subtarget that supports asyncmarks, whether or not that subtarget has any
+operation belonging to it.
+
+### Stage Masks
+
+Both intrinsics take a *stage mask*: an 11-bit value in which a set bit means
+"do not participate". In particular, an asyncmark *omits* the stages its
+mask names, and a wait *ignores* them. The mask `0` therefore names no stage
+and so omits/ignores none.
+
+A mask may set the bit of a reserved stage. Leaving out a stage whose
operations
+do not exist yet is harmless, and lets a mask keep its meaning as the reserved
+bits are filled in. However, omitting/ignoring bits that are neither supported
+nor reserved is an error.
----------------
krzysz00 wrote:
I'd put this somewhat differently
```
Bits not specified in this table are reserved future use. While it is not
statically forbidden to set them, doing so risks the possibility that an async
operation currently assigned to one of the listed stages will be moved into a
reserved stage on a future architecture. Setting reserved bits is an acceptance
of that risk, but will also guarantee that the addition of future async stages
will not modify program behavior.
```
https://github.com/llvm/llvm-project/pull/220442
_______________________________________________
cfe-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
