llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: SiHuaN (sihuan) <details> <summary>Changes</summary> Depends on #<!-- -->222571, which adds the accumulate intrinsics this folds into. An add of a multiply-parts product now selects the accumulating instruction, so the natural way to write a dot product ```c int32_t sum = 0; for (int i = 0; i < n; ++i) sum += __riscv_mul_h00_i32(a[i], b[i]); ``` gets `macc.h00` in the loop rather than a separate `mul.h00` and `add`. The add is rewritten before type legalization, so the shapes whose result is illegal are covered by the existing accumulate lowering rather than needing patterns of their own. --- Patch is 59.75 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/222748.diff 11 Files Affected: - (modified) clang/include/clang/Basic/BuiltinsRISCV.td (+28) - (modified) clang/lib/CodeGen/TargetBuiltins/RISCV.cpp (+74) - (modified) clang/lib/Headers/riscv_packed_simd.h (+28) - (modified) cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c (+172) - (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+30) - (modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (+24-2) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+206) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoP.td (+63) - (added) llvm/test/CodeGen/RISCV/rvp-mul-parts-acc-fold.ll (+429) - (modified) llvm/test/CodeGen/RISCV/rvp-simd-32.ll (+122) - (modified) llvm/test/CodeGen/RISCV/rvp-simd-64.ll (+250) ``````````diff diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td index 58184479d3c27..ee840e45a65ba 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.td +++ b/clang/include/clang/Basic/BuiltinsRISCV.td @@ -426,6 +426,34 @@ def mqracc_w00_i64 : RISCVBuiltin<"int64_t(int64_t, _Vector<2, int>, _Vector<2, def mqracc_w01_i64 : RISCVBuiltin<"int64_t(int64_t, _Vector<2, int>, _Vector<2, int>)">; def mqracc_w11_i64 : RISCVBuiltin<"int64_t(int64_t, _Vector<2, int>, _Vector<2, int>)">; +// Packed Multiply Parts Accumulate (32-bit) +def macc_h00_i32 : RISCVBuiltin<"int(int, _Vector<2, short>, _Vector<2, short>)">; +def macc_h01_i32 : RISCVBuiltin<"int(int, _Vector<2, short>, _Vector<2, short>)">; +def macc_h11_i32 : RISCVBuiltin<"int(int, _Vector<2, short>, _Vector<2, short>)">; +def maccu_h00_u32 : RISCVBuiltin<"unsigned int(unsigned int, _Vector<2, unsigned short>, _Vector<2, unsigned short>)">; +def maccu_h01_u32 : RISCVBuiltin<"unsigned int(unsigned int, _Vector<2, unsigned short>, _Vector<2, unsigned short>)">; +def maccu_h11_u32 : RISCVBuiltin<"unsigned int(unsigned int, _Vector<2, unsigned short>, _Vector<2, unsigned short>)">; +def maccsu_h00_i32 : RISCVBuiltin<"int(int, _Vector<2, short>, _Vector<2, unsigned short>)">; +def maccsu_h11_i32 : RISCVBuiltin<"int(int, _Vector<2, short>, _Vector<2, unsigned short>)">; + +// Packed Multiply Parts Accumulate (64-bit) +def pmacc_h00_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, short>, _Vector<4, short>)">; +def pmacc_h01_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, short>, _Vector<4, short>)">; +def pmacc_h11_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, short>, _Vector<4, short>)">; +def pmaccu_h00_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(_Vector<2, unsigned int>, _Vector<4, unsigned short>, _Vector<4, unsigned short>)">; +def pmaccu_h01_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(_Vector<2, unsigned int>, _Vector<4, unsigned short>, _Vector<4, unsigned short>)">; +def pmaccu_h11_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(_Vector<2, unsigned int>, _Vector<4, unsigned short>, _Vector<4, unsigned short>)">; +def pmaccsu_h00_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, short>, _Vector<4, unsigned short>)">; +def pmaccsu_h11_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, short>, _Vector<4, unsigned short>)">; +def macc_w00_i64 : RISCVBuiltin<"int64_t(int64_t, _Vector<2, int>, _Vector<2, int>)">; +def macc_w01_i64 : RISCVBuiltin<"int64_t(int64_t, _Vector<2, int>, _Vector<2, int>)">; +def macc_w11_i64 : RISCVBuiltin<"int64_t(int64_t, _Vector<2, int>, _Vector<2, int>)">; +def maccu_w00_u64 : RISCVBuiltin<"uint64_t(uint64_t, _Vector<2, unsigned int>, _Vector<2, unsigned int>)">; +def maccu_w01_u64 : RISCVBuiltin<"uint64_t(uint64_t, _Vector<2, unsigned int>, _Vector<2, unsigned int>)">; +def maccu_w11_u64 : RISCVBuiltin<"uint64_t(uint64_t, _Vector<2, unsigned int>, _Vector<2, unsigned int>)">; +def maccsu_w00_i64 : RISCVBuiltin<"int64_t(int64_t, _Vector<2, int>, _Vector<2, unsigned int>)">; +def maccsu_w11_i64 : RISCVBuiltin<"int64_t(int64_t, _Vector<2, int>, _Vector<2, unsigned int>)">; + // Packed Sign and Zero Extend (32-bit) def psext_b_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>)">; def pzext_b_u16x2 : RISCVBuiltin<"_Vector<2, unsigned short>(_Vector<2, unsigned short>)">; diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp index 2e9fbf771bed1..f99a05ce673aa 100644 --- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp @@ -1938,6 +1938,80 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, break; } + // Packed Multiply Parts Accumulate. + case RISCV::BI__builtin_riscv_macc_h00_i32: + case RISCV::BI__builtin_riscv_pmacc_h00_i32x2: + case RISCV::BI__builtin_riscv_macc_w00_i64: + case RISCV::BI__builtin_riscv_macc_h01_i32: + case RISCV::BI__builtin_riscv_pmacc_h01_i32x2: + case RISCV::BI__builtin_riscv_macc_w01_i64: + case RISCV::BI__builtin_riscv_macc_h11_i32: + case RISCV::BI__builtin_riscv_pmacc_h11_i32x2: + case RISCV::BI__builtin_riscv_macc_w11_i64: + case RISCV::BI__builtin_riscv_maccu_h00_u32: + case RISCV::BI__builtin_riscv_pmaccu_h00_u32x2: + case RISCV::BI__builtin_riscv_maccu_w00_u64: + case RISCV::BI__builtin_riscv_maccu_h01_u32: + case RISCV::BI__builtin_riscv_pmaccu_h01_u32x2: + case RISCV::BI__builtin_riscv_maccu_w01_u64: + case RISCV::BI__builtin_riscv_maccu_h11_u32: + case RISCV::BI__builtin_riscv_pmaccu_h11_u32x2: + case RISCV::BI__builtin_riscv_maccu_w11_u64: + case RISCV::BI__builtin_riscv_maccsu_h00_i32: + case RISCV::BI__builtin_riscv_pmaccsu_h00_i32x2: + case RISCV::BI__builtin_riscv_maccsu_w00_i64: + case RISCV::BI__builtin_riscv_maccsu_h11_i32: + case RISCV::BI__builtin_riscv_pmaccsu_h11_i32x2: + case RISCV::BI__builtin_riscv_maccsu_w11_i64: { + switch (BuiltinID) { + default: + llvm_unreachable("unexpected builtin ID"); + case RISCV::BI__builtin_riscv_macc_h00_i32: + case RISCV::BI__builtin_riscv_pmacc_h00_i32x2: + case RISCV::BI__builtin_riscv_macc_w00_i64: + ID = Intrinsic::riscv_macc_00; + break; + case RISCV::BI__builtin_riscv_macc_h01_i32: + case RISCV::BI__builtin_riscv_pmacc_h01_i32x2: + case RISCV::BI__builtin_riscv_macc_w01_i64: + ID = Intrinsic::riscv_macc_01; + break; + case RISCV::BI__builtin_riscv_macc_h11_i32: + case RISCV::BI__builtin_riscv_pmacc_h11_i32x2: + case RISCV::BI__builtin_riscv_macc_w11_i64: + ID = Intrinsic::riscv_macc_11; + break; + case RISCV::BI__builtin_riscv_maccu_h00_u32: + case RISCV::BI__builtin_riscv_pmaccu_h00_u32x2: + case RISCV::BI__builtin_riscv_maccu_w00_u64: + ID = Intrinsic::riscv_maccu_00; + break; + case RISCV::BI__builtin_riscv_maccu_h01_u32: + case RISCV::BI__builtin_riscv_pmaccu_h01_u32x2: + case RISCV::BI__builtin_riscv_maccu_w01_u64: + ID = Intrinsic::riscv_maccu_01; + break; + case RISCV::BI__builtin_riscv_maccu_h11_u32: + case RISCV::BI__builtin_riscv_pmaccu_h11_u32x2: + case RISCV::BI__builtin_riscv_maccu_w11_u64: + ID = Intrinsic::riscv_maccu_11; + break; + case RISCV::BI__builtin_riscv_maccsu_h00_i32: + case RISCV::BI__builtin_riscv_pmaccsu_h00_i32x2: + case RISCV::BI__builtin_riscv_maccsu_w00_i64: + ID = Intrinsic::riscv_maccsu_00; + break; + case RISCV::BI__builtin_riscv_maccsu_h11_i32: + case RISCV::BI__builtin_riscv_pmaccsu_h11_i32x2: + case RISCV::BI__builtin_riscv_maccsu_w11_i64: + ID = Intrinsic::riscv_maccsu_11; + break; + } + + IntrinsicTypes = {ResultType, Ops[1]->getType()}; + break; + } + // Zk builtins // Zknh diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h index 37ac140780d02..5c359337d8b7f 100644 --- a/clang/lib/Headers/riscv_packed_simd.h +++ b/clang/lib/Headers/riscv_packed_simd.h @@ -984,6 +984,34 @@ __packed_ternary_builtin_cast(mqracc_w00_i64, int64_t, int32x2_t, __builtin_risc __packed_ternary_builtin_cast(mqracc_w01_i64, int64_t, int32x2_t, __builtin_riscv_mqracc_w01_i64) __packed_ternary_builtin_cast(mqracc_w11_i64, int64_t, int32x2_t, __builtin_riscv_mqracc_w11_i64) +/* Packed Multiply Parts Accumulate (32-bit) */ +__packed_ternary_builtin_mixed(macc_h00_i32, int32_t, int16x2_t, int16x2_t, __builtin_riscv_macc_h00_i32) +__packed_ternary_builtin_mixed(macc_h01_i32, int32_t, int16x2_t, int16x2_t, __builtin_riscv_macc_h01_i32) +__packed_ternary_builtin_mixed(macc_h11_i32, int32_t, int16x2_t, int16x2_t, __builtin_riscv_macc_h11_i32) +__packed_ternary_builtin_mixed(maccu_h00_u32, uint32_t, uint16x2_t, uint16x2_t, __builtin_riscv_maccu_h00_u32) +__packed_ternary_builtin_mixed(maccu_h01_u32, uint32_t, uint16x2_t, uint16x2_t, __builtin_riscv_maccu_h01_u32) +__packed_ternary_builtin_mixed(maccu_h11_u32, uint32_t, uint16x2_t, uint16x2_t, __builtin_riscv_maccu_h11_u32) +__packed_ternary_builtin_mixed(maccsu_h00_i32, int32_t, int16x2_t, uint16x2_t, __builtin_riscv_maccsu_h00_i32) +__packed_ternary_builtin_mixed(maccsu_h11_i32, int32_t, int16x2_t, uint16x2_t, __builtin_riscv_maccsu_h11_i32) + +/* Packed Multiply Parts Accumulate (64-bit) */ +__packed_ternary_builtin_mixed(pmacc_h00_i32x2, int32x2_t, int16x4_t, int16x4_t, __builtin_riscv_pmacc_h00_i32x2) +__packed_ternary_builtin_mixed(pmacc_h01_i32x2, int32x2_t, int16x4_t, int16x4_t, __builtin_riscv_pmacc_h01_i32x2) +__packed_ternary_builtin_mixed(pmacc_h11_i32x2, int32x2_t, int16x4_t, int16x4_t, __builtin_riscv_pmacc_h11_i32x2) +__packed_ternary_builtin_mixed(pmaccu_h00_u32x2, uint32x2_t, uint16x4_t, uint16x4_t, __builtin_riscv_pmaccu_h00_u32x2) +__packed_ternary_builtin_mixed(pmaccu_h01_u32x2, uint32x2_t, uint16x4_t, uint16x4_t, __builtin_riscv_pmaccu_h01_u32x2) +__packed_ternary_builtin_mixed(pmaccu_h11_u32x2, uint32x2_t, uint16x4_t, uint16x4_t, __builtin_riscv_pmaccu_h11_u32x2) +__packed_ternary_builtin_mixed(pmaccsu_h00_i32x2, int32x2_t, int16x4_t, uint16x4_t, __builtin_riscv_pmaccsu_h00_i32x2) +__packed_ternary_builtin_mixed(pmaccsu_h11_i32x2, int32x2_t, int16x4_t, uint16x4_t, __builtin_riscv_pmaccsu_h11_i32x2) +__packed_ternary_builtin_mixed(macc_w00_i64, int64_t, int32x2_t, int32x2_t, __builtin_riscv_macc_w00_i64) +__packed_ternary_builtin_mixed(macc_w01_i64, int64_t, int32x2_t, int32x2_t, __builtin_riscv_macc_w01_i64) +__packed_ternary_builtin_mixed(macc_w11_i64, int64_t, int32x2_t, int32x2_t, __builtin_riscv_macc_w11_i64) +__packed_ternary_builtin_mixed(maccu_w00_u64, uint64_t, uint32x2_t, uint32x2_t, __builtin_riscv_maccu_w00_u64) +__packed_ternary_builtin_mixed(maccu_w01_u64, uint64_t, uint32x2_t, uint32x2_t, __builtin_riscv_maccu_w01_u64) +__packed_ternary_builtin_mixed(maccu_w11_u64, uint64_t, uint32x2_t, uint32x2_t, __builtin_riscv_maccu_w11_u64) +__packed_ternary_builtin_mixed(maccsu_w00_i64, int64_t, int32x2_t, uint32x2_t, __builtin_riscv_maccsu_w00_i64) +__packed_ternary_builtin_mixed(maccsu_w11_i64, int64_t, int32x2_t, uint32x2_t, __builtin_riscv_maccsu_w11_i64) + /* Packed Narrowing Clip Pair (32-bit) */ __packed_binary_builtin_cast(pnclipp_i8x4, int16x2_t, int8x4_t, __builtin_riscv_pnclipp_i8x4) __packed_binary_builtin_cast(pnclipup_u8x4, uint16x2_t, uint8x4_t, __builtin_riscv_pnclipup_u8x4) diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c index 48fcf036794ff..df9623edfa71a 100644 --- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c +++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c @@ -4248,3 +4248,175 @@ int32_t test_pget_i32x2_i32(int32x2_t v) { uint32_t test_pget_u32x2_u32(uint32x2_t v) { return __riscv_pget_u32x2_u32(v, 1); } + +/* Packed Multiply Parts Accumulate (32-bit) */ + +// CHECK-LABEL: test_macc_h00_i32: +// RV32: macc.h00 +// RV64: pmacc.w.h00 +int32_t test_macc_h00_i32(int32_t rd, int16x2_t a, int16x2_t b) { + return __riscv_macc_h00_i32(rd, a, b); +} + +// CHECK-LABEL: test_macc_h01_i32: +// RV32: macc.h01 +// RV64: pmacc.w.h01 +int32_t test_macc_h01_i32(int32_t rd, int16x2_t a, int16x2_t b) { + return __riscv_macc_h01_i32(rd, a, b); +} + +// CHECK-LABEL: test_macc_h11_i32: +// RV32: macc.h11 +// RV64: pmacc.w.h11 +int32_t test_macc_h11_i32(int32_t rd, int16x2_t a, int16x2_t b) { + return __riscv_macc_h11_i32(rd, a, b); +} + +// CHECK-LABEL: test_maccu_h00_u32: +// RV32: maccu.h00 +// RV64: pmaccu.w.h00 +uint32_t test_maccu_h00_u32(uint32_t rd, uint16x2_t a, uint16x2_t b) { + return __riscv_maccu_h00_u32(rd, a, b); +} + +// CHECK-LABEL: test_maccu_h01_u32: +// RV32: maccu.h01 +// RV64: pmaccu.w.h01 +uint32_t test_maccu_h01_u32(uint32_t rd, uint16x2_t a, uint16x2_t b) { + return __riscv_maccu_h01_u32(rd, a, b); +} + +// CHECK-LABEL: test_maccu_h11_u32: +// RV32: maccu.h11 +// RV64: pmaccu.w.h11 +uint32_t test_maccu_h11_u32(uint32_t rd, uint16x2_t a, uint16x2_t b) { + return __riscv_maccu_h11_u32(rd, a, b); +} + +// CHECK-LABEL: test_maccsu_h00_i32: +// RV32: maccsu.h00 +// RV64: pmaccsu.w.h00 +int32_t test_maccsu_h00_i32(int32_t rd, int16x2_t a, uint16x2_t b) { + return __riscv_maccsu_h00_i32(rd, a, b); +} + +// CHECK-LABEL: test_maccsu_h11_i32: +// RV32: maccsu.h11 +// RV64: pmaccsu.w.h11 +int32_t test_maccsu_h11_i32(int32_t rd, int16x2_t a, uint16x2_t b) { + return __riscv_maccsu_h11_i32(rd, a, b); +} + +/* Packed Multiply Parts Accumulate (64-bit) */ + +// CHECK-LABEL: test_pmacc_h00_i32x2: +// RV32-COUNT-2: macc.h00 +// RV64: pmacc.w.h00 +int32x2_t test_pmacc_h00_i32x2(int32x2_t rd, int16x4_t a, int16x4_t b) { + return __riscv_pmacc_h00_i32x2(rd, a, b); +} + +// CHECK-LABEL: test_pmacc_h01_i32x2: +// RV32-COUNT-2: macc.h01 +// RV64: pmacc.w.h01 +int32x2_t test_pmacc_h01_i32x2(int32x2_t rd, int16x4_t a, int16x4_t b) { + return __riscv_pmacc_h01_i32x2(rd, a, b); +} + +// CHECK-LABEL: test_pmacc_h11_i32x2: +// RV32-COUNT-2: macc.h11 +// RV64: pmacc.w.h11 +int32x2_t test_pmacc_h11_i32x2(int32x2_t rd, int16x4_t a, int16x4_t b) { + return __riscv_pmacc_h11_i32x2(rd, a, b); +} + +// CHECK-LABEL: test_pmaccu_h00_u32x2: +// RV32-COUNT-2: maccu.h00 +// RV64: pmaccu.w.h00 +uint32x2_t test_pmaccu_h00_u32x2(uint32x2_t rd, uint16x4_t a, uint16x4_t b) { + return __riscv_pmaccu_h00_u32x2(rd, a, b); +} + +// CHECK-LABEL: test_pmaccu_h01_u32x2: +// RV32-COUNT-2: maccu.h01 +// RV64: pmaccu.w.h01 +uint32x2_t test_pmaccu_h01_u32x2(uint32x2_t rd, uint16x4_t a, uint16x4_t b) { + return __riscv_pmaccu_h01_u32x2(rd, a, b); +} + +// CHECK-LABEL: test_pmaccu_h11_u32x2: +// RV32-COUNT-2: maccu.h11 +// RV64: pmaccu.w.h11 +uint32x2_t test_pmaccu_h11_u32x2(uint32x2_t rd, uint16x4_t a, uint16x4_t b) { + return __riscv_pmaccu_h11_u32x2(rd, a, b); +} + +// CHECK-LABEL: test_pmaccsu_h00_i32x2: +// RV32-COUNT-2: maccsu.h00 +// RV64: pmaccsu.w.h00 +int32x2_t test_pmaccsu_h00_i32x2(int32x2_t rd, int16x4_t a, uint16x4_t b) { + return __riscv_pmaccsu_h00_i32x2(rd, a, b); +} + +// CHECK-LABEL: test_pmaccsu_h11_i32x2: +// RV32-COUNT-2: maccsu.h11 +// RV64: pmaccsu.w.h11 +int32x2_t test_pmaccsu_h11_i32x2(int32x2_t rd, int16x4_t a, uint16x4_t b) { + return __riscv_pmaccsu_h11_i32x2(rd, a, b); +} + +// CHECK-LABEL: test_macc_w00_i64: +// RV32: wmacc +// RV64: macc.w00 +int64_t test_macc_w00_i64(int64_t rd, int32x2_t a, int32x2_t b) { + return __riscv_macc_w00_i64(rd, a, b); +} + +// CHECK-LABEL: test_macc_w01_i64: +// RV32: wmacc +// RV64: macc.w01 +int64_t test_macc_w01_i64(int64_t rd, int32x2_t a, int32x2_t b) { + return __riscv_macc_w01_i64(rd, a, b); +} + +// CHECK-LABEL: test_macc_w11_i64: +// RV32: wmacc +// RV64: macc.w11 +int64_t test_macc_w11_i64(int64_t rd, int32x2_t a, int32x2_t b) { + return __riscv_macc_w11_i64(rd, a, b); +} + +// CHECK-LABEL: test_maccu_w00_u64: +// RV32: wmaccu +// RV64: maccu.w00 +uint64_t test_maccu_w00_u64(uint64_t rd, uint32x2_t a, uint32x2_t b) { + return __riscv_maccu_w00_u64(rd, a, b); +} + +// CHECK-LABEL: test_maccu_w01_u64: +// RV32: wmaccu +// RV64: maccu.w01 +uint64_t test_maccu_w01_u64(uint64_t rd, uint32x2_t a, uint32x2_t b) { + return __riscv_maccu_w01_u64(rd, a, b); +} + +// CHECK-LABEL: test_maccu_w11_u64: +// RV32: wmaccu +// RV64: maccu.w11 +uint64_t test_maccu_w11_u64(uint64_t rd, uint32x2_t a, uint32x2_t b) { + return __riscv_maccu_w11_u64(rd, a, b); +} + +// CHECK-LABEL: test_maccsu_w00_i64: +// RV32: wmaccsu +// RV64: maccsu.w00 +int64_t test_maccsu_w00_i64(int64_t rd, int32x2_t a, uint32x2_t b) { + return __riscv_maccsu_w00_i64(rd, a, b); +} + +// CHECK-LABEL: test_maccsu_w11_i64: +// RV32: wmaccsu +// RV64: maccsu.w11 +int64_t test_maccsu_w11_i64(int64_t rd, int32x2_t a, uint32x2_t b) { + return __riscv_maccsu_w11_i64(rd, a, b); +} diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index e4ec9e9beb5ee..e70caa8b09700 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -2186,6 +2186,36 @@ class RVPBinaryIntrinsic def int_riscv_mulsu_00 : RVPScalarMulPartsIntrinsic; def int_riscv_mulsu_11 : RVPScalarMulPartsIntrinsic; + // Packed Multiply Parts Accumulate. + class RVPPackedMulPartsAccIntrinsic + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], + [LLVMMatchType<0>, + LLVMSubdivide2VectorType<0>, + LLVMSubdivide2VectorType<0>], + [IntrNoMem, IntrSpeculatable]>; + def int_riscv_pmacc_00 : RVPPackedMulPartsAccIntrinsic; + def int_riscv_pmacc_01 : RVPPackedMulPartsAccIntrinsic; + def int_riscv_pmacc_11 : RVPPackedMulPartsAccIntrinsic; + def int_riscv_pmaccu_00 : RVPPackedMulPartsAccIntrinsic; + def int_riscv_pmaccu_01 : RVPPackedMulPartsAccIntrinsic; + def int_riscv_pmaccu_11 : RVPPackedMulPartsAccIntrinsic; + def int_riscv_pmaccsu_00 : RVPPackedMulPartsAccIntrinsic; + def int_riscv_pmaccsu_11 : RVPPackedMulPartsAccIntrinsic; + + class RVPScalarMulPartsAccIntrinsic + : DefaultAttrsIntrinsic<[llvm_anyint_ty], + [LLVMMatchType<0>, llvm_anyvector_ty, + LLVMMatchType<1>], + [IntrNoMem, IntrSpeculatable]>; + def int_riscv_macc_00 : RVPScalarMulPartsAccIntrinsic; + def int_riscv_macc_01 : RVPScalarMulPartsAccIntrinsic; + def int_riscv_macc_11 : RVPScalarMulPartsAccIntrinsic; + def int_riscv_maccu_00 : RVPScalarMulPartsAccIntrinsic; + def int_riscv_maccu_01 : RVPScalarMulPartsAccIntrinsic; + def int_riscv_maccu_11 : RVPScalarMulPartsAccIntrinsic; + def int_riscv_maccsu_00 : RVPScalarMulPartsAccIntrinsic; + def int_riscv_maccsu_11 : RVPScalarMulPartsAccIntrinsic; + // Packed Absolute Difference Sum. def int_riscv_pabdsumu : DefaultAttrsIntrinsic<[llvm_anyint_ty], diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index d263d0320839b..c1c7031a17e71 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -2073,13 +2073,35 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { return; } case RISCVISD::MQWACC: - case RISCVISD::MQRWACC: { + case RISCVISD::MQRWACC: + case RISCVISD::WMACC: + case RISCVISD::WMACCU: + case RISCVISD::WMACCSU: { assert(!Subtarget->is64Bit() && Subtarget->hasStdExtP() && "Unexpected opcode"); SDValue Op0 = buildGPRPair(CurDAG, DL, MVT::Untyped, Node->getOperand(0), Node->getOperand(1)); - unsigned Opc = Opcode == RISCVISD::MQRWACC ? RISCV::MQRWACC : RISCV::MQWACC; + unsigned Opc; + switch (Opcode) { + default: + llvm_unreachable("Unexpected opcode"); + case RISCVISD::MQWACC: + Opc = RISCV::MQWACC; + break; + case RISCVISD::MQRWACC: + Opc = RISCV::MQRWACC; + break; + case RISCVISD::WMACC: + Opc = RISCV::WMACC; + break; + case RISCVISD::WMACCU: + Opc = RISCV::WMACCU; + break; + case RISCVISD::WMACCSU: + Opc = RISCV::WMACCSU; + break; + } MachineSDNode *New = CurDAG->getMachineNode( Opc, DL, MVT::Untyped, Op0, Node->getOperand(2), Node->getOperand(3)); auto [Lo, Hi] = extractGPRPair(CurDAG, DL, SDValue(New, 0)); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 5f8ad5da42da1..20b45a9b011c1 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -12548,6 +12548,79 @@ static Intrinsic::ID getRVPScalarMulPartsIntrinsic(unsigned IntNo) { } } +/// Return the accumulate form of multiply-parts intrinsic \p IntNo, or +/// Intrinsic::not_intrinsic if there is none. +static Intrinsic::ID getRVPMulPartsAccIntrinsic(unsigned IntNo) { + switch (IntNo) { + default: + return Intrinsic::not_intrinsic; + case Intrinsic::riscv_mul_00: + return Intrinsic::riscv_macc_00; + case Intrinsic::riscv_pmul_00: + return Intrinsic::riscv_pmacc_00; + ca... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/222748 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
