https://github.com/iamvickynguyen updated https://github.com/llvm/llvm-project/pull/221507
>From ad3e9f064ef3e6ed454a0f187d77098f0456791a Mon Sep 17 00:00:00 2001 From: Vicky Nguyen <[email protected]> Date: Sat, 5 Sep 2026 17:45:07 -0700 Subject: [PATCH] [CIR][AArch64] Complete upstream vector saturating shift left NEON builtins --- .../include/clang/Basic/AArch64CodeGenUtils.h | 18 +- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 51 +- clang/test/CodeGen/AArch64/neon-intrinsics.c | 704 ---------------- clang/test/CodeGen/AArch64/neon/intrinsics.c | 796 +++++++++++++++++- 4 files changed, 849 insertions(+), 720 deletions(-) diff --git a/clang/include/clang/Basic/AArch64CodeGenUtils.h b/clang/include/clang/Basic/AArch64CodeGenUtils.h index 72b162ec45909..53870594d559e 100644 --- a/clang/include/clang/Basic/AArch64CodeGenUtils.h +++ b/clang/include/clang/Basic/AArch64CodeGenUtils.h @@ -46,6 +46,12 @@ enum { // the intrinsic's .td. ArgAsWidenedRetType = (1 << 9), + // The immediate operand is `LLVMMatchType<0>` in the intrinsic + // definition, so it is vectorized like a data operand (e.g. the `_n_` + // scalar saturating shifts: vqshlb_n_s8, vqshlub_n_s8, ...). + // ClangIR-only; classic code-gen derives this from the intrinsic's .td. + VectorizeImmArg = (1 << 10), + Vectorize1ArgType = Add1ArgType | VectorizeArgTypes, VectorRet = AddRetType | VectorizeRetType, VectorRetGetArgs01 = @@ -592,22 +598,22 @@ const inline ARMNeonVectorIntrinsicInfo AArch64SISDIntrinsicMap[] = { NEONMAP1(vqrshrund_n_s64, aarch64_neon_sqrshrun, AddRetType), NEONMAP1(vqrshrunh_n_s16, aarch64_neon_sqrshrun, VectorRet | Use64BitVectors | ArgAsWidenedRetType), NEONMAP1(vqrshruns_n_s32, aarch64_neon_sqrshrun, VectorRet | Use64BitVectors | ArgAsWidenedRetType), - NEONMAP1(vqshlb_n_s8, aarch64_neon_sqshl, Vectorize1ArgType | Use64BitVectors), - NEONMAP1(vqshlb_n_u8, aarch64_neon_uqshl, Vectorize1ArgType | Use64BitVectors), + NEONMAP1(vqshlb_n_s8, aarch64_neon_sqshl, Vectorize1ArgType | Use64BitVectors | VectorizeImmArg), + NEONMAP1(vqshlb_n_u8, aarch64_neon_uqshl, Vectorize1ArgType | Use64BitVectors | VectorizeImmArg), NEONMAP1(vqshlb_s8, aarch64_neon_sqshl, Vectorize1ArgType | Use64BitVectors), NEONMAP1(vqshlb_u8, aarch64_neon_uqshl, Vectorize1ArgType | Use64BitVectors), NEONMAP1(vqshld_s64, aarch64_neon_sqshl, Add1ArgType), NEONMAP1(vqshld_u64, aarch64_neon_uqshl, Add1ArgType), - NEONMAP1(vqshlh_n_s16, aarch64_neon_sqshl, Vectorize1ArgType | Use64BitVectors), - NEONMAP1(vqshlh_n_u16, aarch64_neon_uqshl, Vectorize1ArgType | Use64BitVectors), + NEONMAP1(vqshlh_n_s16, aarch64_neon_sqshl, Vectorize1ArgType | Use64BitVectors | VectorizeImmArg), + NEONMAP1(vqshlh_n_u16, aarch64_neon_uqshl, Vectorize1ArgType | Use64BitVectors | VectorizeImmArg), NEONMAP1(vqshlh_s16, aarch64_neon_sqshl, Vectorize1ArgType | Use64BitVectors), NEONMAP1(vqshlh_u16, aarch64_neon_uqshl, Vectorize1ArgType | Use64BitVectors), NEONMAP1(vqshls_n_s32, aarch64_neon_sqshl, Add1ArgType), NEONMAP1(vqshls_n_u32, aarch64_neon_uqshl, Add1ArgType), NEONMAP1(vqshls_s32, aarch64_neon_sqshl, Add1ArgType), NEONMAP1(vqshls_u32, aarch64_neon_uqshl, Add1ArgType), - NEONMAP1(vqshlub_n_s8, aarch64_neon_sqshlu, Vectorize1ArgType | Use64BitVectors), - NEONMAP1(vqshluh_n_s16, aarch64_neon_sqshlu, Vectorize1ArgType | Use64BitVectors), + NEONMAP1(vqshlub_n_s8, aarch64_neon_sqshlu, Vectorize1ArgType | Use64BitVectors | VectorizeImmArg), + NEONMAP1(vqshluh_n_s16, aarch64_neon_sqshlu, Vectorize1ArgType | Use64BitVectors | VectorizeImmArg), NEONMAP1(vqshlus_n_s32, aarch64_neon_sqshlu, Add1ArgType), NEONMAP1(vqshrnd_n_s64, aarch64_neon_sqshrn, AddRetType), NEONMAP1(vqshrnd_n_u64, aarch64_neon_uqshrn, AddRetType), diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index 7f59176bc6268..83cd4255a5bb4 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -321,15 +321,19 @@ deriveNeonSISDIntrinsicOperandTypes(CIRGenFunction &cgf, unsigned modifier, // `ArgAsWidenedRetType`. When set, wrap every non-immediate data operand // that has the same scalar type as arg0. Checking the ICE bitmap prevents // an i32 immediate from being vectorized when it has the same type as a - // data operand (e.g. vqshrns_n_s32). + // data operand (e.g. vqshrns_n_s32). `VectorizeImmArg` marks the entries + // whose trailing immediate must be widened as well. + const bool widenTrailingImm = vecArgTy && ops.size() == 2 && + (modifier & VectorizeImmArg) && + (iceArguments & (1U << 1)); llvm::SmallVector<mlir::Type> argTypes; argTypes.reserve(ops.size()); for (unsigned i = 0, e = ops.size(); i != e; ++i) { bool isImmediate = iceArguments & (1U << i); - if (vecArgTy && !isImmediate && matchesArg0Ty(ops[i].getType())) - argTypes.push_back(vecArgTy); - else - argTypes.push_back(ops[i].getType()); + bool asVector = + vecArgTy && ((!isImmediate && matchesArg0Ty(ops[i].getType())) || + (widenTrailingImm && i == 1)); + argTypes.push_back(asVector ? mlir::Type(vecArgTy) : ops[i].getType()); } return {funcResTy, std::move(argTypes)}; @@ -582,6 +586,23 @@ emitCommonNeonSISDBuiltinExpr(CIRGenFunction &cgf, case NEON::BI__builtin_neon_vqrshrnh_n_u16: case NEON::BI__builtin_neon_vqrshruns_n_s32: case NEON::BI__builtin_neon_vqrshrunh_n_s16: + case NEON::BI__builtin_neon_vqshlb_s8: + case NEON::BI__builtin_neon_vqshlb_u8: + case NEON::BI__builtin_neon_vqshlh_s16: + case NEON::BI__builtin_neon_vqshlh_u16: + case NEON::BI__builtin_neon_vqshls_s32: + case NEON::BI__builtin_neon_vqshls_u32: + case NEON::BI__builtin_neon_vqshld_s64: + case NEON::BI__builtin_neon_vqshld_u64: + case NEON::BI__builtin_neon_vqshlb_n_s8: + case NEON::BI__builtin_neon_vqshlb_n_u8: + case NEON::BI__builtin_neon_vqshlh_n_s16: + case NEON::BI__builtin_neon_vqshlh_n_u16: + case NEON::BI__builtin_neon_vqshls_n_s32: + case NEON::BI__builtin_neon_vqshls_n_u32: + case NEON::BI__builtin_neon_vqshlub_n_s8: + case NEON::BI__builtin_neon_vqshluh_n_s16: + case NEON::BI__builtin_neon_vqshlus_n_s32: break; } @@ -1201,10 +1222,24 @@ static mlir::Value emitCommonNeonBuiltinExpr( case NEON::BI__builtin_neon_vqdmulh_laneq_v: case NEON::BI__builtin_neon_vqrdmulhq_laneq_v: case NEON::BI__builtin_neon_vqrdmulh_laneq_v: + cgf.cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AArch64 builtin call: ") + + ctx.BuiltinInfo.getName(builtinID)); + return mlir::Value{}; case NEON::BI__builtin_neon_vqshl_n_v: - case NEON::BI__builtin_neon_vqshlq_n_v: + case NEON::BI__builtin_neon_vqshlq_n_v: { + llvm::StringRef intrName = + usgn ? "aarch64.neon.uqshl" : "aarch64.neon.sqshl"; + return emitNeonCall(cgf.cgm, cgf.getBuilder(), {ty, ty}, ops, intrName, ty, + loc, /*isConstrainedFPIntrinsic=*/false, /*shift=*/1, + /*rightshift=*/false); + } case NEON::BI__builtin_neon_vqshlu_n_v: case NEON::BI__builtin_neon_vqshluq_n_v: + return emitNeonCall(cgf.cgm, cgf.getBuilder(), {ty, ty}, ops, + "aarch64.neon.sqshlu", ty, loc, + /*isConstrainedFPIntrinsic=*/false, /*shift=*/1, + /*rightshift=*/false); case NEON::BI__builtin_neon_vrecpe_v: case NEON::BI__builtin_neon_vrecpeq_v: case NEON::BI__builtin_neon_vrsqrte_v: @@ -1392,7 +1427,9 @@ static mlir::Value emitCommonNeonBuiltinExpr( case NEON::BI__builtin_neon_vshl_v: case NEON::BI__builtin_neon_vshlq_v: case NEON::BI__builtin_neon_vraddhn_v: - case NEON::BI__builtin_neon_vrsubhn_v: { + case NEON::BI__builtin_neon_vrsubhn_v: + case NEON::BI__builtin_neon_vqshl_v: + case NEON::BI__builtin_neon_vqshlq_v: { // Pick the signed/unsigned intrinsic when the builtin has both // (UnsignedAlts); otherwise there is a single intrinsic. unsigned intrinsic = diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index 7a945abca9a80..2098abb097889 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -2325,240 +2325,6 @@ uint64x2_t test_vcltq_f64(float64x2_t v1, float64x2_t v2) { return vcltq_f64(v1, v2); } -// CHECK-LABEL: define dso_local <8 x i8> @test_vqshl_s8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHL_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> [[A]], <8 x i8> [[B]]) -// CHECK-NEXT: ret <8 x i8> [[VQSHL_V_I]] -// -int8x8_t test_vqshl_s8(int8x8_t a, int8x8_t b) { - return vqshl_s8(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vqshl_s16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VQSHL_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[VQSHL_V_I]], <4 x i16> [[VQSHL_V1_I]]) -// CHECK-NEXT: [[VQSHL_V3_I:%.*]] = bitcast <4 x i16> [[VQSHL_V2_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to <4 x i16> -// CHECK-NEXT: ret <4 x i16> [[TMP2]] -// -int16x4_t test_vqshl_s16(int16x4_t a, int16x4_t b) { - return vqshl_s16(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vqshl_s32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VQSHL_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> [[VQSHL_V_I]], <2 x i32> [[VQSHL_V1_I]]) -// CHECK-NEXT: [[VQSHL_V3_I:%.*]] = bitcast <2 x i32> [[VQSHL_V2_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to <2 x i32> -// CHECK-NEXT: ret <2 x i32> [[TMP2]] -// -int32x2_t test_vqshl_s32(int32x2_t a, int32x2_t b) { - return vqshl_s32(a, b); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vqshl_s64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// CHECK-NEXT: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> -// CHECK-NEXT: [[VQSHL_V2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> [[VQSHL_V_I]], <1 x i64> [[VQSHL_V1_I]]) -// CHECK-NEXT: [[VQSHL_V3_I:%.*]] = bitcast <1 x i64> [[VQSHL_V2_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to i64 -// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0 -// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]] -// -int64x1_t test_vqshl_s64(int64x1_t a, int64x1_t b) { - return vqshl_s64(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vqshl_u8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHL_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> [[A]], <8 x i8> [[B]]) -// CHECK-NEXT: ret <8 x i8> [[VQSHL_V_I]] -// -uint8x8_t test_vqshl_u8(uint8x8_t a, int8x8_t b) { - return vqshl_u8(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vqshl_u16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VQSHL_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[VQSHL_V_I]], <4 x i16> [[VQSHL_V1_I]]) -// CHECK-NEXT: [[VQSHL_V3_I:%.*]] = bitcast <4 x i16> [[VQSHL_V2_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to <4 x i16> -// CHECK-NEXT: ret <4 x i16> [[TMP2]] -// -uint16x4_t test_vqshl_u16(uint16x4_t a, int16x4_t b) { - return vqshl_u16(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vqshl_u32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VQSHL_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> [[VQSHL_V_I]], <2 x i32> [[VQSHL_V1_I]]) -// CHECK-NEXT: [[VQSHL_V3_I:%.*]] = bitcast <2 x i32> [[VQSHL_V2_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to <2 x i32> -// CHECK-NEXT: ret <2 x i32> [[TMP2]] -// -uint32x2_t test_vqshl_u32(uint32x2_t a, int32x2_t b) { - return vqshl_u32(a, b); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vqshl_u64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// CHECK-NEXT: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> -// CHECK-NEXT: [[VQSHL_V2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> [[VQSHL_V_I]], <1 x i64> [[VQSHL_V1_I]]) -// CHECK-NEXT: [[VQSHL_V3_I:%.*]] = bitcast <1 x i64> [[VQSHL_V2_I]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to i64 -// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0 -// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]] -// -uint64x1_t test_vqshl_u64(uint64x1_t a, int64x1_t b) { - return vqshl_u64(a, b); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vqshlq_s8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> [[A]], <16 x i8> [[B]]) -// CHECK-NEXT: ret <16 x i8> [[VQSHLQ_V_I]] -// -int8x16_t test_vqshlq_s8(int8x16_t a, int8x16_t b) { - return vqshlq_s8(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vqshlq_s16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK-NEXT: [[VQSHLQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> [[VQSHLQ_V_I]], <8 x i16> [[VQSHLQ_V1_I]]) -// CHECK-NEXT: [[VQSHLQ_V3_I:%.*]] = bitcast <8 x i16> [[VQSHLQ_V2_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <8 x i16> -// CHECK-NEXT: ret <8 x i16> [[TMP2]] -// -int16x8_t test_vqshlq_s16(int16x8_t a, int16x8_t b) { - return vqshlq_s16(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vqshlq_s32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> -// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> -// CHECK-NEXT: [[VQSHLQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> [[VQSHLQ_V_I]], <4 x i32> [[VQSHLQ_V1_I]]) -// CHECK-NEXT: [[VQSHLQ_V3_I:%.*]] = bitcast <4 x i32> [[VQSHLQ_V2_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <4 x i32> -// CHECK-NEXT: ret <4 x i32> [[TMP2]] -// -int32x4_t test_vqshlq_s32(int32x4_t a, int32x4_t b) { - return vqshlq_s32(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vqshlq_s64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> -// CHECK-NEXT: [[VQSHLQ_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> [[VQSHLQ_V_I]], <2 x i64> [[VQSHLQ_V1_I]]) -// CHECK-NEXT: [[VQSHLQ_V3_I:%.*]] = bitcast <2 x i64> [[VQSHLQ_V2_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <2 x i64> -// CHECK-NEXT: ret <2 x i64> [[TMP2]] -// -int64x2_t test_vqshlq_s64(int64x2_t a, int64x2_t b) { - return vqshlq_s64(a, b); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vqshlq_u8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> [[A]], <16 x i8> [[B]]) -// CHECK-NEXT: ret <16 x i8> [[VQSHLQ_V_I]] -// -uint8x16_t test_vqshlq_u8(uint8x16_t a, int8x16_t b) { - return vqshlq_u8(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vqshlq_u16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK-NEXT: [[VQSHLQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> [[VQSHLQ_V_I]], <8 x i16> [[VQSHLQ_V1_I]]) -// CHECK-NEXT: [[VQSHLQ_V3_I:%.*]] = bitcast <8 x i16> [[VQSHLQ_V2_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <8 x i16> -// CHECK-NEXT: ret <8 x i16> [[TMP2]] -// -uint16x8_t test_vqshlq_u16(uint16x8_t a, int16x8_t b) { - return vqshlq_u16(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vqshlq_u32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> -// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> -// CHECK-NEXT: [[VQSHLQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> [[VQSHLQ_V_I]], <4 x i32> [[VQSHLQ_V1_I]]) -// CHECK-NEXT: [[VQSHLQ_V3_I:%.*]] = bitcast <4 x i32> [[VQSHLQ_V2_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <4 x i32> -// CHECK-NEXT: ret <4 x i32> [[TMP2]] -// -uint32x4_t test_vqshlq_u32(uint32x4_t a, int32x4_t b) { - return vqshlq_u32(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vqshlq_u64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// CHECK-NEXT: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> -// CHECK-NEXT: [[VQSHLQ_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> [[VQSHLQ_V_I]], <2 x i64> [[VQSHLQ_V1_I]]) -// CHECK-NEXT: [[VQSHLQ_V3_I:%.*]] = bitcast <2 x i64> [[VQSHLQ_V2_I]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <2 x i64> -// CHECK-NEXT: ret <2 x i64> [[TMP2]] -// -uint64x2_t test_vqshlq_u64(uint64x2_t a, int64x2_t b) { - return vqshlq_u64(a, b); -} - // CHECK-LABEL: define dso_local <8 x i8> @test_vrshl_s8( // CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -3476,86 +3242,6 @@ float64x2_t test_vmulxq_f64(float64x2_t a, float64x2_t b) { return vmulxq_f64(a, b); } -// CHECK-LABEL: define dso_local <8 x i8> @test_vqshlu_n_s8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHLU_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> [[A]], <8 x i8> splat (i8 3)) -// CHECK-NEXT: ret <8 x i8> [[VQSHLU_N]] -// -uint8x8_t test_vqshlu_n_s8(int8x8_t a) { - return vqshlu_n_s8(a, 3); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vqshlu_n_s16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> [[VQSHLU_N]], <4 x i16> splat (i16 3)) -// CHECK-NEXT: ret <4 x i16> [[VQSHLU_N1]] -// -uint16x4_t test_vqshlu_n_s16(int16x4_t a) { - return vqshlu_n_s16(a, 3); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vqshlu_n_s32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32> [[VQSHLU_N]], <2 x i32> splat (i32 3)) -// CHECK-NEXT: ret <2 x i32> [[VQSHLU_N1]] -// -uint32x2_t test_vqshlu_n_s32(int32x2_t a) { - return vqshlu_n_s32(a, 3); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vqshluq_n_s8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHLU_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8> [[A]], <16 x i8> splat (i8 3)) -// CHECK-NEXT: ret <16 x i8> [[VQSHLU_N]] -// -uint8x16_t test_vqshluq_n_s8(int8x16_t a) { - return vqshluq_n_s8(a, 3); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vqshluq_n_s16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16> [[VQSHLU_N]], <8 x i16> splat (i16 3)) -// CHECK-NEXT: ret <8 x i16> [[VQSHLU_N1]] -// -uint16x8_t test_vqshluq_n_s16(int16x8_t a) { - return vqshluq_n_s16(a, 3); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vqshluq_n_s32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshlu.v4i32(<4 x i32> [[VQSHLU_N]], <4 x i32> splat (i32 3)) -// CHECK-NEXT: ret <4 x i32> [[VQSHLU_N1]] -// -uint32x4_t test_vqshluq_n_s32(int32x4_t a) { - return vqshluq_n_s32(a, 3); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vqshluq_n_s64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> [[VQSHLU_N]], <2 x i64> splat (i64 3)) -// CHECK-NEXT: ret <2 x i64> [[VQSHLU_N1]] -// -uint64x2_t test_vqshluq_n_s64(int64x2_t a) { - return vqshluq_n_s64(a, 3); -} - // CHECK-LABEL: define dso_local <8 x i8> @test_vshrn_n_s16( // CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -4828,98 +4514,6 @@ int64x2_t test_vqdmlsl_high_s32(int64x2_t a, int32x4_t b, int32x4_t c) { return vqdmlsl_high_s32(a, b, c); } -// CHECK-LABEL: define dso_local i8 @test_vqshlb_s8( -// CHECK-SAME: i8 noundef [[A:%.*]], i8 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 -// CHECK-NEXT: [[VQSHLB_S8_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]]) -// CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[VQSHLB_S8_I]], i64 0 -// CHECK-NEXT: ret i8 [[TMP2]] -// -int8_t test_vqshlb_s8(int8_t a, int8_t b) { - return vqshlb_s8(a, b); -} - -// CHECK-LABEL: define dso_local i16 @test_vqshlh_s16( -// CHECK-SAME: i16 noundef [[A:%.*]], i16 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 -// CHECK-NEXT: [[VQSHLH_S16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) -// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[VQSHLH_S16_I]], i64 0 -// CHECK-NEXT: ret i16 [[TMP2]] -// -int16_t test_vqshlh_s16(int16_t a, int16_t b) { - return vqshlh_s16(a, b); -} - -// CHECK-LABEL: define dso_local i32 @test_vqshls_s32( -// CHECK-SAME: i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHLS_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sqshl.i32(i32 [[A]], i32 [[B]]) -// CHECK-NEXT: ret i32 [[VQSHLS_S32_I]] -// -int32_t test_vqshls_s32(int32_t a, int32_t b) { - return vqshls_s32(a, b); -} - -// CHECK-LABEL: define dso_local i64 @test_vqshld_s64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHLD_S64_I:%.*]] = call i64 @llvm.aarch64.neon.sqshl.i64(i64 [[A]], i64 [[B]]) -// CHECK-NEXT: ret i64 [[VQSHLD_S64_I]] -// -int64_t test_vqshld_s64(int64_t a, int64_t b) { - return vqshld_s64(a, b); -} - -// CHECK-LABEL: define dso_local i8 @test_vqshlb_u8( -// CHECK-SAME: i8 noundef [[A:%.*]], i8 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 -// CHECK-NEXT: [[VQSHLB_U8_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]]) -// CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[VQSHLB_U8_I]], i64 0 -// CHECK-NEXT: ret i8 [[TMP2]] -// -uint8_t test_vqshlb_u8(uint8_t a, int8_t b) { - return vqshlb_u8(a, b); -} - -// CHECK-LABEL: define dso_local i16 @test_vqshlh_u16( -// CHECK-SAME: i16 noundef [[A:%.*]], i16 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 -// CHECK-NEXT: [[VQSHLH_U16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) -// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[VQSHLH_U16_I]], i64 0 -// CHECK-NEXT: ret i16 [[TMP2]] -// -uint16_t test_vqshlh_u16(uint16_t a, int16_t b) { - return vqshlh_u16(a, b); -} - -// CHECK-LABEL: define dso_local i32 @test_vqshls_u32( -// CHECK-SAME: i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHLS_U32_I:%.*]] = call i32 @llvm.aarch64.neon.uqshl.i32(i32 [[A]], i32 [[B]]) -// CHECK-NEXT: ret i32 [[VQSHLS_U32_I]] -// -uint32_t test_vqshls_u32(uint32_t a, int32_t b) { - return vqshls_u32(a, b); -} - -// CHECK-LABEL: define dso_local i64 @test_vqshld_u64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHLD_U64_I:%.*]] = call i64 @llvm.aarch64.neon.uqshl.i64(i64 [[A]], i64 [[B]]) -// CHECK-NEXT: ret i64 [[VQSHLD_U64_I]] -// -uint64_t test_vqshld_u64(uint64_t a, int64_t b) { - return vqshld_u64(a, b); -} - // CHECK-LABEL: define dso_local i64 @test_vrshld_s64( // CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -7347,304 +6941,6 @@ uint64_t test_vcaltd_f64(float64_t a, float64_t b) { return (uint64_t)vcaltd_f64(a, b); } -// CHECK-LABEL: define dso_local i8 @test_vqshlb_n_s8( -// CHECK-SAME: i8 noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 -// CHECK-NEXT: [[VQSHLB_N_S8:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> [[TMP0]], <8 x i8> <i8 7, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>) -// CHECK-NEXT: [[TMP1:%.*]] = extractelement <8 x i8> [[VQSHLB_N_S8]], i64 0 -// CHECK-NEXT: ret i8 [[TMP1]] -// -int8_t test_vqshlb_n_s8(int8_t a) { - return (int8_t)vqshlb_n_s8(a, 7); -} - -// CHECK-LABEL: define dso_local i16 @test_vqshlh_n_s16( -// CHECK-SAME: i16 noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 -// CHECK-NEXT: [[VQSHLH_N_S16:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[TMP0]], <4 x i16> <i16 15, i16 poison, i16 poison, i16 poison>) -// CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i16> [[VQSHLH_N_S16]], i64 0 -// CHECK-NEXT: ret i16 [[TMP1]] -// -int16_t test_vqshlh_n_s16(int16_t a) { - return (int16_t)vqshlh_n_s16(a, 15); -} - -// CHECK-LABEL: define dso_local i32 @test_vqshls_n_s32( -// CHECK-SAME: i32 noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHLS_N_S32:%.*]] = call i32 @llvm.aarch64.neon.sqshl.i32(i32 [[A]], i32 31) -// CHECK-NEXT: ret i32 [[VQSHLS_N_S32]] -// -int32_t test_vqshls_n_s32(int32_t a) { - return (int32_t)vqshls_n_s32(a, 31); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vqshl_n_s8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHL_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> [[A]], <8 x i8> zeroinitializer) -// CHECK-NEXT: ret <8 x i8> [[VQSHL_N]] -// -int8x8_t test_vqshl_n_s8(int8x8_t a) { - return vqshl_n_s8(a, 0); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vqshlq_n_s8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHL_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> [[A]], <16 x i8> zeroinitializer) -// CHECK-NEXT: ret <16 x i8> [[VQSHL_N]] -// -int8x16_t test_vqshlq_n_s8(int8x16_t a) { - return vqshlq_n_s8(a, 0); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vqshl_n_s16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[VQSHL_N]], <4 x i16> zeroinitializer) -// CHECK-NEXT: ret <4 x i16> [[VQSHL_N1]] -// -int16x4_t test_vqshl_n_s16(int16x4_t a) { - return vqshl_n_s16(a, 0); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vqshlq_n_s16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> [[VQSHL_N]], <8 x i16> zeroinitializer) -// CHECK-NEXT: ret <8 x i16> [[VQSHL_N1]] -// -int16x8_t test_vqshlq_n_s16(int16x8_t a) { - return vqshlq_n_s16(a, 0); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vqshl_n_s32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> [[VQSHL_N]], <2 x i32> zeroinitializer) -// CHECK-NEXT: ret <2 x i32> [[VQSHL_N1]] -// -int32x2_t test_vqshl_n_s32(int32x2_t a) { - return vqshl_n_s32(a, 0); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vqshlq_n_s32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> [[VQSHL_N]], <4 x i32> zeroinitializer) -// CHECK-NEXT: ret <4 x i32> [[VQSHL_N1]] -// -int32x4_t test_vqshlq_n_s32(int32x4_t a) { - return vqshlq_n_s32(a, 0); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vqshlq_n_s64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> [[VQSHL_N]], <2 x i64> zeroinitializer) -// CHECK-NEXT: ret <2 x i64> [[VQSHL_N1]] -// -int64x2_t test_vqshlq_n_s64(int64x2_t a) { - return vqshlq_n_s64(a, 0); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vqshl_n_u8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHL_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> [[A]], <8 x i8> zeroinitializer) -// CHECK-NEXT: ret <8 x i8> [[VQSHL_N]] -// -uint8x8_t test_vqshl_n_u8(uint8x8_t a) { - return vqshl_n_u8(a, 0); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vqshlq_n_u8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHL_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> [[A]], <16 x i8> zeroinitializer) -// CHECK-NEXT: ret <16 x i8> [[VQSHL_N]] -// -uint8x16_t test_vqshlq_n_u8(uint8x16_t a) { - return vqshlq_n_u8(a, 0); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vqshl_n_u16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[VQSHL_N]], <4 x i16> zeroinitializer) -// CHECK-NEXT: ret <4 x i16> [[VQSHL_N1]] -// -uint16x4_t test_vqshl_n_u16(uint16x4_t a) { - return vqshl_n_u16(a, 0); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vqshlq_n_u16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> [[VQSHL_N]], <8 x i16> zeroinitializer) -// CHECK-NEXT: ret <8 x i16> [[VQSHL_N1]] -// -uint16x8_t test_vqshlq_n_u16(uint16x8_t a) { - return vqshlq_n_u16(a, 0); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vqshl_n_u32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> [[VQSHL_N]], <2 x i32> zeroinitializer) -// CHECK-NEXT: ret <2 x i32> [[VQSHL_N1]] -// -uint32x2_t test_vqshl_n_u32(uint32x2_t a) { - return vqshl_n_u32(a, 0); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vqshlq_n_u32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> [[VQSHL_N]], <4 x i32> zeroinitializer) -// CHECK-NEXT: ret <4 x i32> [[VQSHL_N1]] -// -uint32x4_t test_vqshlq_n_u32(uint32x4_t a) { - return vqshlq_n_u32(a, 0); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vqshlq_n_u64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> [[VQSHL_N]], <2 x i64> zeroinitializer) -// CHECK-NEXT: ret <2 x i64> [[VQSHL_N1]] -// -uint64x2_t test_vqshlq_n_u64(uint64x2_t a) { - return vqshlq_n_u64(a, 0); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vqshl_n_s64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> [[VQSHL_N]], <1 x i64> splat (i64 1)) -// CHECK-NEXT: ret <1 x i64> [[VQSHL_N1]] -// -int64x1_t test_vqshl_n_s64(int64x1_t a) { - return vqshl_n_s64(a, 1); -} - -// CHECK-LABEL: define dso_local i8 @test_vqshlb_n_u8( -// CHECK-SAME: i8 noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 -// CHECK-NEXT: [[VQSHLB_N_U8:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> [[TMP0]], <8 x i8> <i8 7, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>) -// CHECK-NEXT: [[TMP1:%.*]] = extractelement <8 x i8> [[VQSHLB_N_U8]], i64 0 -// CHECK-NEXT: ret i8 [[TMP1]] -// -uint8_t test_vqshlb_n_u8(uint8_t a) { - return (uint8_t)vqshlb_n_u8(a, 7); -} - -// CHECK-LABEL: define dso_local i16 @test_vqshlh_n_u16( -// CHECK-SAME: i16 noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 -// CHECK-NEXT: [[VQSHLH_N_U16:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[TMP0]], <4 x i16> <i16 15, i16 poison, i16 poison, i16 poison>) -// CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i16> [[VQSHLH_N_U16]], i64 0 -// CHECK-NEXT: ret i16 [[TMP1]] -// -uint16_t test_vqshlh_n_u16(uint16_t a) { - return (uint16_t)vqshlh_n_u16(a, 15); -} - -// CHECK-LABEL: define dso_local i32 @test_vqshls_n_u32( -// CHECK-SAME: i32 noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHLS_N_U32:%.*]] = call i32 @llvm.aarch64.neon.uqshl.i32(i32 [[A]], i32 31) -// CHECK-NEXT: ret i32 [[VQSHLS_N_U32]] -// -uint32_t test_vqshls_n_u32(uint32_t a) { - return (uint32_t)vqshls_n_u32(a, 31); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vqshl_n_u64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> [[VQSHL_N]], <1 x i64> splat (i64 1)) -// CHECK-NEXT: ret <1 x i64> [[VQSHL_N1]] -// -uint64x1_t test_vqshl_n_u64(uint64x1_t a) { - return vqshl_n_u64(a, 1); -} - -// CHECK-LABEL: define dso_local i8 @test_vqshlub_n_s8( -// CHECK-SAME: i8 noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 -// CHECK-NEXT: [[VQSHLUB_N_S8:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> [[TMP0]], <8 x i8> <i8 7, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>) -// CHECK-NEXT: [[TMP1:%.*]] = extractelement <8 x i8> [[VQSHLUB_N_S8]], i64 0 -// CHECK-NEXT: ret i8 [[TMP1]] -// -int8_t test_vqshlub_n_s8(int8_t a) { - return (int8_t)vqshlub_n_s8(a, 7); -} - -// CHECK-LABEL: define dso_local i16 @test_vqshluh_n_s16( -// CHECK-SAME: i16 noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 -// CHECK-NEXT: [[VQSHLUH_N_S16:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> [[TMP0]], <4 x i16> <i16 15, i16 poison, i16 poison, i16 poison>) -// CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i16> [[VQSHLUH_N_S16]], i64 0 -// CHECK-NEXT: ret i16 [[TMP1]] -// -int16_t test_vqshluh_n_s16(int16_t a) { - return (int16_t)vqshluh_n_s16(a, 15); -} - -// CHECK-LABEL: define dso_local i32 @test_vqshlus_n_s32( -// CHECK-SAME: i32 noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHLUS_N_S32:%.*]] = call i32 @llvm.aarch64.neon.sqshlu.i32(i32 [[A]], i32 31) -// CHECK-NEXT: ret i32 [[VQSHLUS_N_S32]] -// -int32_t test_vqshlus_n_s32(int32_t a) { - return (int32_t)vqshlus_n_s32(a, 31); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vqshlu_n_s64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshlu.v1i64(<1 x i64> [[VQSHLU_N]], <1 x i64> splat (i64 1)) -// CHECK-NEXT: ret <1 x i64> [[VQSHLU_N1]] -// -uint64x1_t test_vqshlu_n_s64(int64x1_t a) { - return vqshlu_n_s64(a, 1); -} - // CHECK-LABEL: define dso_local <8 x i8> @test_vreinterpret_s8_s16( diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index 6d46e7ad8a8f3..7175c616cf484 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -561,9 +561,8 @@ float64_t test_vmaxvq_f64(float64x2_t a) { } //===------------------------------------------------------===// -// 2.1.3.2 Vector Saturating Shift Left -// -// TODO: Implement the remaining intrinsics from this group. +// 2.1.3.1.2 Vector Saturating Shift Left +// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-saturating-shift-left //===------------------------------------------------------===// // ALL-LABEL: @test_vqshlud_n_s64( @@ -600,6 +599,797 @@ int64_t test_vqshld_n_s64(int64_t a) { return (int64_t)vqshld_n_s64(a, 63); } +// LLVM-LABEL: @test_vqshl_s8( +// CIR-LABEL: @vqshl_s8( +int8x8_t test_vqshl_s8(int8x8_t a, int8x8_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, {{%.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i> + +// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[VQSHL_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> [[A]], <8 x i8> [[B]]) +// LLVM: ret <8 x i8> [[VQSHL_V_I]] + return vqshl_s8(a, b); +} + +// LLVM-LABEL: @test_vqshl_s16( +// CIR-LABEL: @vqshl_s16( +int16x4_t test_vqshl_s16(int16x4_t a, int16x4_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, {{%.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s16i> + +// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> +// LLVM: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> +// LLVM: [[VQSHL_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[VQSHL_V_I]], <4 x i16> [[VQSHL_V1_I]]) +// LLVM: [[VQSHL_V3_I:%.*]] = bitcast <4 x i16> [[VQSHL_V2_I]] to <8 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to <4 x i16> +// LLVM: ret <4 x i16> [[TMP2]] + return vqshl_s16(a, b); +} + +// LLVM-LABEL: @test_vqshl_s32( +// CIR-LABEL: @vqshl_s32( +int32x2_t test_vqshl_s32(int32x2_t a, int32x2_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, {{%.*}} : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>) -> !cir.vector<2 x !s32i> + +// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> +// LLVM: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> +// LLVM: [[VQSHL_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> [[VQSHL_V_I]], <2 x i32> [[VQSHL_V1_I]]) +// LLVM: [[VQSHL_V3_I:%.*]] = bitcast <2 x i32> [[VQSHL_V2_I]] to <8 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to <2 x i32> +// LLVM: ret <2 x i32> [[TMP2]] + return vqshl_s32(a, b); +} + +// LLVM-LABEL: @test_vqshl_s64( +// CIR-LABEL: @vqshl_s64( +int64x1_t test_vqshl_s64(int64x1_t a, int64x1_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, {{%.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>) -> !cir.vector<1 x !s64i> + +// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> +// LLVM: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> +// LLVM: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> +// LLVM: [[VQSHL_V2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> [[VQSHL_V_I]], <1 x i64> [[VQSHL_V1_I]]) +// LLVM: [[VQSHL_V3_I:%.*]] = bitcast <1 x i64> [[VQSHL_V2_I]] to <8 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to i64 +// LLVM: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0 +// LLVM: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]] + return vqshl_s64(a, b); +} + +// LLVM-LABEL: @test_vqshl_u8( +// CIR-LABEL: @vqshl_u8( +uint8x8_t test_vqshl_u8(uint8x8_t a, int8x8_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, {{%.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>) -> !cir.vector<8 x !u8i> + +// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[VQSHL_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> [[A]], <8 x i8> [[B]]) +// LLVM: ret <8 x i8> [[VQSHL_V_I]] + return vqshl_u8(a, b); +} + +// LLVM-LABEL: @test_vqshl_u16( +// CIR-LABEL: @vqshl_u16( +uint16x4_t test_vqshl_u16(uint16x4_t a, int16x4_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, {{%.*}} : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>) -> !cir.vector<4 x !u16i> + +// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> +// LLVM: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> +// LLVM: [[VQSHL_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[VQSHL_V_I]], <4 x i16> [[VQSHL_V1_I]]) +// LLVM: [[VQSHL_V3_I:%.*]] = bitcast <4 x i16> [[VQSHL_V2_I]] to <8 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to <4 x i16> +// LLVM: ret <4 x i16> [[TMP2]] + return vqshl_u16(a, b); +} + +// LLVM-LABEL: @test_vqshl_u32( +// CIR-LABEL: @vqshl_u32( +uint32x2_t test_vqshl_u32(uint32x2_t a, int32x2_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, {{%.*}} : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>) -> !cir.vector<2 x !u32i> + +// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> +// LLVM: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> +// LLVM: [[VQSHL_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> [[VQSHL_V_I]], <2 x i32> [[VQSHL_V1_I]]) +// LLVM: [[VQSHL_V3_I:%.*]] = bitcast <2 x i32> [[VQSHL_V2_I]] to <8 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to <2 x i32> +// LLVM: ret <2 x i32> [[TMP2]] + return vqshl_u32(a, b); +} + +// LLVM-LABEL: @test_vqshl_u64( +// CIR-LABEL: @vqshl_u64( +uint64x1_t test_vqshl_u64(uint64x1_t a, int64x1_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, {{%.*}} : (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>) -> !cir.vector<1 x !u64i> + +// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> +// LLVM: [[VQSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> +// LLVM: [[VQSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> +// LLVM: [[VQSHL_V2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> [[VQSHL_V_I]], <1 x i64> [[VQSHL_V1_I]]) +// LLVM: [[VQSHL_V3_I:%.*]] = bitcast <1 x i64> [[VQSHL_V2_I]] to <8 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VQSHL_V3_I]] to i64 +// LLVM: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0 +// LLVM: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]] + return vqshl_u64(a, b); +} + +// LLVM-LABEL: @test_vqshlq_s8( +// CIR-LABEL: @vqshlq_s8( +int8x16_t test_vqshlq_s8(int8x16_t a, int8x16_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, {{%.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>) -> !cir.vector<16 x !s8i> + +// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[VQSHLQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> [[A]], <16 x i8> [[B]]) +// LLVM: ret <16 x i8> [[VQSHLQ_V_I]] + return vqshlq_s8(a, b); +} + +// LLVM-LABEL: @test_vqshlq_s16( +// CIR-LABEL: @vqshlq_s16( +int16x8_t test_vqshlq_s16(int16x8_t a, int16x8_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, {{%.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>) -> !cir.vector<8 x !s16i> + +// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> +// LLVM: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> +// LLVM: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> +// LLVM: [[VQSHLQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> [[VQSHLQ_V_I]], <8 x i16> [[VQSHLQ_V1_I]]) +// LLVM: [[VQSHLQ_V3_I:%.*]] = bitcast <8 x i16> [[VQSHLQ_V2_I]] to <16 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <8 x i16> +// LLVM: ret <8 x i16> [[TMP2]] + return vqshlq_s16(a, b); +} + +// LLVM-LABEL: @test_vqshlq_s32( +// CIR-LABEL: @vqshlq_s32( +int32x4_t test_vqshlq_s32(int32x4_t a, int32x4_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, {{%.*}} : (!cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>) -> !cir.vector<4 x !s32i> + +// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> +// LLVM: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> +// LLVM: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// LLVM: [[VQSHLQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> [[VQSHLQ_V_I]], <4 x i32> [[VQSHLQ_V1_I]]) +// LLVM: [[VQSHLQ_V3_I:%.*]] = bitcast <4 x i32> [[VQSHLQ_V2_I]] to <16 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <4 x i32> +// LLVM: ret <4 x i32> [[TMP2]] + return vqshlq_s32(a, b); +} + +// LLVM-LABEL: @test_vqshlq_s64( +// CIR-LABEL: @vqshlq_s64( +int64x2_t test_vqshlq_s64(int64x2_t a, int64x2_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, {{%.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>) -> !cir.vector<2 x !s64i> + +// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> +// LLVM: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> +// LLVM: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// LLVM: [[VQSHLQ_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> [[VQSHLQ_V_I]], <2 x i64> [[VQSHLQ_V1_I]]) +// LLVM: [[VQSHLQ_V3_I:%.*]] = bitcast <2 x i64> [[VQSHLQ_V2_I]] to <16 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <2 x i64> +// LLVM: ret <2 x i64> [[TMP2]] + return vqshlq_s64(a, b); +} + +// LLVM-LABEL: @test_vqshlq_u8( +// CIR-LABEL: @vqshlq_u8( +uint8x16_t test_vqshlq_u8(uint8x16_t a, int8x16_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, {{%.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>) -> !cir.vector<16 x !u8i> + +// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[VQSHLQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> [[A]], <16 x i8> [[B]]) +// LLVM: ret <16 x i8> [[VQSHLQ_V_I]] + return vqshlq_u8(a, b); +} + +// LLVM-LABEL: @test_vqshlq_u16( +// CIR-LABEL: @vqshlq_u16( +uint16x8_t test_vqshlq_u16(uint16x8_t a, int16x8_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, {{%.*}} : (!cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>) -> !cir.vector<8 x !u16i> + +// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> +// LLVM: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> +// LLVM: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> +// LLVM: [[VQSHLQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> [[VQSHLQ_V_I]], <8 x i16> [[VQSHLQ_V1_I]]) +// LLVM: [[VQSHLQ_V3_I:%.*]] = bitcast <8 x i16> [[VQSHLQ_V2_I]] to <16 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <8 x i16> +// LLVM: ret <8 x i16> [[TMP2]] + return vqshlq_u16(a, b); +} + +// LLVM-LABEL: @test_vqshlq_u32( +// CIR-LABEL: @vqshlq_u32( +uint32x4_t test_vqshlq_u32(uint32x4_t a, int32x4_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, {{%.*}} : (!cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>) -> !cir.vector<4 x !u32i> + +// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> +// LLVM: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> +// LLVM: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// LLVM: [[VQSHLQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> [[VQSHLQ_V_I]], <4 x i32> [[VQSHLQ_V1_I]]) +// LLVM: [[VQSHLQ_V3_I:%.*]] = bitcast <4 x i32> [[VQSHLQ_V2_I]] to <16 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <4 x i32> +// LLVM: ret <4 x i32> [[TMP2]] + return vqshlq_u32(a, b); +} + +// LLVM-LABEL: @test_vqshlq_u64( +// CIR-LABEL: @vqshlq_u64( +uint64x2_t test_vqshlq_u64(uint64x2_t a, int64x2_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, {{%.*}} : (!cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>) -> !cir.vector<2 x !u64i> + +// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> +// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> +// LLVM: [[VQSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> +// LLVM: [[VQSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// LLVM: [[VQSHLQ_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> [[VQSHLQ_V_I]], <2 x i64> [[VQSHLQ_V1_I]]) +// LLVM: [[VQSHLQ_V3_I:%.*]] = bitcast <2 x i64> [[VQSHLQ_V2_I]] to <16 x i8> +// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VQSHLQ_V3_I]] to <2 x i64> +// LLVM: ret <2 x i64> [[TMP2]] + return vqshlq_u64(a, b); +} + +// LLVM-LABEL: @test_vqshlb_s8( +// CIR-LABEL: @vqshlb_s8( +int8_t test_vqshlb_s8(int8_t a, int8_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, {{%.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i> + +// LLVM-SAME: i8 {{.*}}[[A:%.*]], i8 {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 +// LLVM: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 +// LLVM: [[VQSHLB_S8_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]]) +// LLVM: [[TMP2:%.*]] = extractelement <8 x i8> [[VQSHLB_S8_I]], i64 0 +// LLVM: ret i8 [[TMP2]] + return vqshlb_s8(a, b); +} + +// LLVM-LABEL: @test_vqshlh_s16( +// CIR-LABEL: @vqshlh_s16( +int16_t test_vqshlh_s16(int16_t a, int16_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, {{%.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s16i> + +// LLVM-SAME: i16 {{.*}}[[A:%.*]], i16 {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 +// LLVM: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 +// LLVM: [[VQSHLH_S16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) +// LLVM: [[TMP2:%.*]] = extractelement <4 x i16> [[VQSHLH_S16_I]], i64 0 +// LLVM: ret i16 [[TMP2]] + return vqshlh_s16(a, b); +} + +// LLVM-LABEL: @test_vqshls_s32( +// CIR-LABEL: @vqshls_s32( +int32_t test_vqshls_s32(int32_t a, int32_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, {{%.*}} : (!s32i, !s32i) -> !s32i + +// LLVM-SAME: i32 {{.*}}[[A:%.*]], i32 {{.*}}[[B:%.*]]) +// LLVM: [[VQSHLS_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sqshl.i32(i32 [[A]], i32 [[B]]) +// LLVM: ret i32 [[VQSHLS_S32_I]] + return vqshls_s32(a, b); +} + +// LLVM-LABEL: @test_vqshld_s64( +// CIR-LABEL: @vqshld_s64( +int64_t test_vqshld_s64(int64_t a, int64_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, {{%.*}} : (!s64i, !s64i) -> !s64i + +// LLVM-SAME: i64 {{.*}}[[A:%.*]], i64 {{.*}}[[B:%.*]]) +// LLVM: [[VQSHLD_S64_I:%.*]] = call i64 @llvm.aarch64.neon.sqshl.i64(i64 [[A]], i64 [[B]]) +// LLVM: ret i64 [[VQSHLD_S64_I]] + return vqshld_s64(a, b); +} + +// LLVM-LABEL: @test_vqshlb_u8( +// CIR-LABEL: @vqshlb_u8( +uint8_t test_vqshlb_u8(uint8_t a, int8_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, {{%.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>) -> !cir.vector<8 x !u8i> + +// LLVM-SAME: i8 {{.*}}[[A:%.*]], i8 {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 +// LLVM: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 +// LLVM: [[VQSHLB_U8_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]]) +// LLVM: [[TMP2:%.*]] = extractelement <8 x i8> [[VQSHLB_U8_I]], i64 0 +// LLVM: ret i8 [[TMP2]] + return vqshlb_u8(a, b); +} + +// LLVM-LABEL: @test_vqshlh_u16( +// CIR-LABEL: @vqshlh_u16( +uint16_t test_vqshlh_u16(uint16_t a, int16_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, {{%.*}} : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>) -> !cir.vector<4 x !u16i> + +// LLVM-SAME: i16 {{.*}}[[A:%.*]], i16 {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 +// LLVM: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0 +// LLVM: [[VQSHLH_U16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) +// LLVM: [[TMP2:%.*]] = extractelement <4 x i16> [[VQSHLH_U16_I]], i64 0 +// LLVM: ret i16 [[TMP2]] + return vqshlh_u16(a, b); +} + +// LLVM-LABEL: @test_vqshls_u32( +// CIR-LABEL: @vqshls_u32( +uint32_t test_vqshls_u32(uint32_t a, int32_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, {{%.*}} : (!u32i, !s32i) -> !u32i + +// LLVM-SAME: i32 {{.*}}[[A:%.*]], i32 {{.*}}[[B:%.*]]) +// LLVM: [[VQSHLS_U32_I:%.*]] = call i32 @llvm.aarch64.neon.uqshl.i32(i32 [[A]], i32 [[B]]) +// LLVM: ret i32 [[VQSHLS_U32_I]] + return vqshls_u32(a, b); +} + +// LLVM-LABEL: @test_vqshld_u64( +// CIR-LABEL: @vqshld_u64( +uint64_t test_vqshld_u64(uint64_t a, int64_t b) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, {{%.*}} : (!u64i, !s64i) -> !u64i + +// LLVM-SAME: i64 {{.*}}[[A:%.*]], i64 {{.*}}[[B:%.*]]) +// LLVM: [[VQSHLD_U64_I:%.*]] = call i64 @llvm.aarch64.neon.uqshl.i64(i64 [[A]], i64 [[B]]) +// LLVM: ret i64 [[VQSHLD_U64_I]] + return vqshld_u64(a, b); +} + +// ALL-LABEL: @test_vqshlu_n_s8( +uint8x8_t test_vqshlu_n_s8(int8x8_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<3> : !u8i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !u8i, !cir.vector<8 x !u8i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshlu" {{%.*}}, [[AMT]] : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>) -> !cir.vector<8 x !u8i> + +// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]]) +// LLVM: [[VQSHLU_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> [[A]], <8 x i8> splat (i8 3)) +// LLVM: ret <8 x i8> [[VQSHLU_N]] + return vqshlu_n_s8(a, 3); +} + +// ALL-LABEL: @test_vqshlu_n_s16( +uint16x4_t test_vqshlu_n_s16(int16x4_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<3> : !u16i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !u16i, !cir.vector<4 x !u16i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshlu" {{%.*}}, [[AMT]] : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>) -> !cir.vector<4 x !u16i> + +// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// LLVM: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM: [[VQSHLU_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> [[VQSHLU_N]], <4 x i16> splat (i16 3)) +// LLVM: ret <4 x i16> [[VQSHLU_N1]] + return vqshlu_n_s16(a, 3); +} + +// ALL-LABEL: @test_vqshlu_n_s32( +uint32x2_t test_vqshlu_n_s32(int32x2_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<3> : !u32i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !u32i, !cir.vector<2 x !u32i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshlu" {{%.*}}, [[AMT]] : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>) -> !cir.vector<2 x !u32i> + +// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> +// LLVM: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM: [[VQSHLU_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32> [[VQSHLU_N]], <2 x i32> splat (i32 3)) +// LLVM: ret <2 x i32> [[VQSHLU_N1]] + return vqshlu_n_s32(a, 3); +} + +// ALL-LABEL: @test_vqshluq_n_s8( +uint8x16_t test_vqshluq_n_s8(int8x16_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<3> : !u8i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !u8i, !cir.vector<16 x !u8i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshlu" {{%.*}}, [[AMT]] : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>) -> !cir.vector<16 x !u8i> + +// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]]) +// LLVM: [[VQSHLU_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8> [[A]], <16 x i8> splat (i8 3)) +// LLVM: ret <16 x i8> [[VQSHLU_N]] + return vqshluq_n_s8(a, 3); +} + +// ALL-LABEL: @test_vqshluq_n_s16( +uint16x8_t test_vqshluq_n_s16(int16x8_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<3> : !u16i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !u16i, !cir.vector<8 x !u16i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshlu" {{%.*}}, [[AMT]] : (!cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>) -> !cir.vector<8 x !u16i> + +// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> +// LLVM: [[VQSHLU_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> +// LLVM: [[VQSHLU_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16> [[VQSHLU_N]], <8 x i16> splat (i16 3)) +// LLVM: ret <8 x i16> [[VQSHLU_N1]] + return vqshluq_n_s16(a, 3); +} + +// ALL-LABEL: @test_vqshluq_n_s32( +uint32x4_t test_vqshluq_n_s32(int32x4_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<3> : !u32i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !u32i, !cir.vector<4 x !u32i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshlu" {{%.*}}, [[AMT]] : (!cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>) -> !cir.vector<4 x !u32i> + +// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> +// LLVM: [[VQSHLU_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> +// LLVM: [[VQSHLU_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshlu.v4i32(<4 x i32> [[VQSHLU_N]], <4 x i32> splat (i32 3)) +// LLVM: ret <4 x i32> [[VQSHLU_N1]] + return vqshluq_n_s32(a, 3); +} + +// ALL-LABEL: @test_vqshluq_n_s64( +uint64x2_t test_vqshluq_n_s64(int64x2_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<3> : !u64i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !u64i, !cir.vector<2 x !u64i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshlu" {{%.*}}, [[AMT]] : (!cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>) -> !cir.vector<2 x !u64i> + +// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> +// LLVM: [[VQSHLU_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> +// LLVM: [[VQSHLU_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> [[VQSHLU_N]], <2 x i64> splat (i64 3)) +// LLVM: ret <2 x i64> [[VQSHLU_N1]] + return vqshluq_n_s64(a, 3); +} + +// ALL-LABEL: @test_vqshlb_n_s8( +int8_t test_vqshlb_n_s8(int8_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<7> : !s8i +// CIR: [[AMT:%.*]] = cir.vec.insert [[IMM]], {{.*}} : !cir.vector<8 x !s8i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, [[AMT]] : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i> + +// LLVM-SAME: i8 {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 +// LLVM: [[VQSHLB_N_S8:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> [[TMP0]], <8 x i8> <i8 7, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>) +// LLVM: [[TMP1:%.*]] = extractelement <8 x i8> [[VQSHLB_N_S8]], i64 0 +// LLVM: ret i8 [[TMP1]] + return (int8_t)vqshlb_n_s8(a, 7); +} + +// ALL-LABEL: @test_vqshlh_n_s16( +int16_t test_vqshlh_n_s16(int16_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<15> : !s16i +// CIR: [[AMT:%.*]] = cir.vec.insert [[IMM]], {{.*}} : !cir.vector<4 x !s16i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, [[AMT]] : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s16i> + +// LLVM-SAME: i16 {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 +// LLVM: [[VQSHLH_N_S16:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[TMP0]], <4 x i16> <i16 15, i16 poison, i16 poison, i16 poison>) +// LLVM: [[TMP1:%.*]] = extractelement <4 x i16> [[VQSHLH_N_S16]], i64 0 +// LLVM: ret i16 [[TMP1]] + return (int16_t)vqshlh_n_s16(a, 15); +} + +// ALL-LABEL: @test_vqshls_n_s32( +int32_t test_vqshls_n_s32(int32_t a) { +// CIR: [[AMT:%.*]] = cir.const #cir.int<31> : !s32i +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, [[AMT]] : (!s32i, !s32i) -> !s32i + +// LLVM-SAME: i32 {{.*}}[[A:%.*]]) +// LLVM: [[VQSHLS_N_S32:%.*]] = call i32 @llvm.aarch64.neon.sqshl.i32(i32 [[A]], i32 31) +// LLVM: ret i32 [[VQSHLS_N_S32]] + return (int32_t)vqshls_n_s32(a, 31); +} + +// ALL-LABEL: @test_vqshl_n_s8( +int8x8_t test_vqshl_n_s8(int8x8_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<0> : !s8i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !s8i, !cir.vector<8 x !s8i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, [[AMT]] : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i> + +// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]]) +// LLVM: [[VQSHL_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> [[A]], <8 x i8> zeroinitializer) +// LLVM: ret <8 x i8> [[VQSHL_N]] + return vqshl_n_s8(a, 0); +} + +// ALL-LABEL: @test_vqshlq_n_s8( +int8x16_t test_vqshlq_n_s8(int8x16_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<0> : !s8i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !s8i, !cir.vector<16 x !s8i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, [[AMT]] : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>) -> !cir.vector<16 x !s8i> + +// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]]) +// LLVM: [[VQSHL_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> [[A]], <16 x i8> zeroinitializer) +// LLVM: ret <16 x i8> [[VQSHL_N]] + return vqshlq_n_s8(a, 0); +} + +// ALL-LABEL: @test_vqshl_n_s16( +int16x4_t test_vqshl_n_s16(int16x4_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<0> : !s16i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !s16i, !cir.vector<4 x !s16i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, [[AMT]] : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s16i> + +// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// LLVM: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM: [[VQSHL_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[VQSHL_N]], <4 x i16> zeroinitializer) +// LLVM: ret <4 x i16> [[VQSHL_N1]] + return vqshl_n_s16(a, 0); +} + +// ALL-LABEL: @test_vqshlq_n_s16( +int16x8_t test_vqshlq_n_s16(int16x8_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<0> : !s16i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !s16i, !cir.vector<8 x !s16i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, [[AMT]] : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>) -> !cir.vector<8 x !s16i> + +// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> +// LLVM: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> +// LLVM: [[VQSHL_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> [[VQSHL_N]], <8 x i16> zeroinitializer) +// LLVM: ret <8 x i16> [[VQSHL_N1]] + return vqshlq_n_s16(a, 0); +} + +// ALL-LABEL: @test_vqshl_n_s32( +int32x2_t test_vqshl_n_s32(int32x2_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<0> : !s32i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !s32i, !cir.vector<2 x !s32i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, [[AMT]] : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>) -> !cir.vector<2 x !s32i> + +// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> +// LLVM: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM: [[VQSHL_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> [[VQSHL_N]], <2 x i32> zeroinitializer) +// LLVM: ret <2 x i32> [[VQSHL_N1]] + return vqshl_n_s32(a, 0); +} + +// ALL-LABEL: @test_vqshlq_n_s32( +int32x4_t test_vqshlq_n_s32(int32x4_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<0> : !s32i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !s32i, !cir.vector<4 x !s32i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, [[AMT]] : (!cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>) -> !cir.vector<4 x !s32i> + +// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> +// LLVM: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> +// LLVM: [[VQSHL_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> [[VQSHL_N]], <4 x i32> zeroinitializer) +// LLVM: ret <4 x i32> [[VQSHL_N1]] + return vqshlq_n_s32(a, 0); +} + +// ALL-LABEL: @test_vqshlq_n_s64( +int64x2_t test_vqshlq_n_s64(int64x2_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<0> : !s64i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !s64i, !cir.vector<2 x !s64i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, [[AMT]] : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>) -> !cir.vector<2 x !s64i> + +// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> +// LLVM: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> +// LLVM: [[VQSHL_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> [[VQSHL_N]], <2 x i64> zeroinitializer) +// LLVM: ret <2 x i64> [[VQSHL_N1]] + return vqshlq_n_s64(a, 0); +} + +// ALL-LABEL: @test_vqshl_n_u8( +uint8x8_t test_vqshl_n_u8(uint8x8_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<0> : !u8i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !u8i, !cir.vector<8 x !u8i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, [[AMT]] : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>) -> !cir.vector<8 x !u8i> + +// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]]) +// LLVM: [[VQSHL_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> [[A]], <8 x i8> zeroinitializer) +// LLVM: ret <8 x i8> [[VQSHL_N]] + return vqshl_n_u8(a, 0); +} + +// ALL-LABEL: @test_vqshlq_n_u8( +uint8x16_t test_vqshlq_n_u8(uint8x16_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<0> : !u8i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !u8i, !cir.vector<16 x !u8i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, [[AMT]] : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>) -> !cir.vector<16 x !u8i> + +// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]]) +// LLVM: [[VQSHL_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> [[A]], <16 x i8> zeroinitializer) +// LLVM: ret <16 x i8> [[VQSHL_N]] + return vqshlq_n_u8(a, 0); +} + +// ALL-LABEL: @test_vqshl_n_u16( +uint16x4_t test_vqshl_n_u16(uint16x4_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<0> : !u16i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !u16i, !cir.vector<4 x !u16i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, [[AMT]] : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>) -> !cir.vector<4 x !u16i> + +// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// LLVM: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM: [[VQSHL_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[VQSHL_N]], <4 x i16> zeroinitializer) +// LLVM: ret <4 x i16> [[VQSHL_N1]] + return vqshl_n_u16(a, 0); +} + +// ALL-LABEL: @test_vqshlq_n_u16( +uint16x8_t test_vqshlq_n_u16(uint16x8_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<0> : !u16i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !u16i, !cir.vector<8 x !u16i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, [[AMT]] : (!cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>) -> !cir.vector<8 x !u16i> + +// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> +// LLVM: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> +// LLVM: [[VQSHL_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> [[VQSHL_N]], <8 x i16> zeroinitializer) +// LLVM: ret <8 x i16> [[VQSHL_N1]] + return vqshlq_n_u16(a, 0); +} + +// ALL-LABEL: @test_vqshl_n_u32( +uint32x2_t test_vqshl_n_u32(uint32x2_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<0> : !u32i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !u32i, !cir.vector<2 x !u32i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, [[AMT]] : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>) -> !cir.vector<2 x !u32i> + +// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> +// LLVM: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM: [[VQSHL_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> [[VQSHL_N]], <2 x i32> zeroinitializer) +// LLVM: ret <2 x i32> [[VQSHL_N1]] + return vqshl_n_u32(a, 0); +} + +// ALL-LABEL: @test_vqshlq_n_u32( +uint32x4_t test_vqshlq_n_u32(uint32x4_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<0> : !u32i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !u32i, !cir.vector<4 x !u32i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, [[AMT]] : (!cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>) -> !cir.vector<4 x !u32i> + +// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> +// LLVM: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> +// LLVM: [[VQSHL_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> [[VQSHL_N]], <4 x i32> zeroinitializer) +// LLVM: ret <4 x i32> [[VQSHL_N1]] + return vqshlq_n_u32(a, 0); +} + +// ALL-LABEL: @test_vqshlq_n_u64( +uint64x2_t test_vqshlq_n_u64(uint64x2_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<0> : !u64i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !u64i, !cir.vector<2 x !u64i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, [[AMT]] : (!cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>) -> !cir.vector<2 x !u64i> + +// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> +// LLVM: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> +// LLVM: [[VQSHL_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> [[VQSHL_N]], <2 x i64> zeroinitializer) +// LLVM: ret <2 x i64> [[VQSHL_N1]] + return vqshlq_n_u64(a, 0); +} + +// ALL-LABEL: @test_vqshl_n_s64( +int64x1_t test_vqshl_n_s64(int64x1_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<1> : !s64i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !s64i, !cir.vector<1 x !s64i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}, [[AMT]] : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>) -> !cir.vector<1 x !s64i> + +// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> +// LLVM: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> +// LLVM: [[VQSHL_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> [[VQSHL_N]], <1 x i64> splat (i64 1)) +// LLVM: ret <1 x i64> [[VQSHL_N1]] + return vqshl_n_s64(a, 1); +} + +// ALL-LABEL: @test_vqshlb_n_u8( +uint8_t test_vqshlb_n_u8(uint8_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<7> : !u8i +// CIR: [[AMT:%.*]] = cir.vec.insert [[IMM]], {{.*}} : !cir.vector<8 x !u8i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, [[AMT]] : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>) -> !cir.vector<8 x !u8i> + +// LLVM-SAME: i8 {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 +// LLVM: [[VQSHLB_N_U8:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> [[TMP0]], <8 x i8> <i8 7, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>) +// LLVM: [[TMP1:%.*]] = extractelement <8 x i8> [[VQSHLB_N_U8]], i64 0 +// LLVM: ret i8 [[TMP1]] + return (uint8_t)vqshlb_n_u8(a, 7); +} + +// ALL-LABEL: @test_vqshlh_n_u16( +uint16_t test_vqshlh_n_u16(uint16_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<15> : !u16i +// CIR: [[AMT:%.*]] = cir.vec.insert [[IMM]], {{.*}} : !cir.vector<4 x !u16i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, [[AMT]] : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>) -> !cir.vector<4 x !u16i> + +// LLVM-SAME: i16 {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 +// LLVM: [[VQSHLH_N_U16:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[TMP0]], <4 x i16> <i16 15, i16 poison, i16 poison, i16 poison>) +// LLVM: [[TMP1:%.*]] = extractelement <4 x i16> [[VQSHLH_N_U16]], i64 0 +// LLVM: ret i16 [[TMP1]] + return (uint16_t)vqshlh_n_u16(a, 15); +} + +// ALL-LABEL: @test_vqshls_n_u32( +uint32_t test_vqshls_n_u32(uint32_t a) { +// CIR: [[AMT:%.*]] = cir.const #cir.int<31> : !s32i +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, [[AMT]] : (!u32i, !s32i) -> !u32i + +// LLVM-SAME: i32 {{.*}}[[A:%.*]]) +// LLVM: [[VQSHLS_N_U32:%.*]] = call i32 @llvm.aarch64.neon.uqshl.i32(i32 [[A]], i32 31) +// LLVM: ret i32 [[VQSHLS_N_U32]] + return (uint32_t)vqshls_n_u32(a, 31); +} + +// ALL-LABEL: @test_vqshl_n_u64( +uint64x1_t test_vqshl_n_u64(uint64x1_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<1> : !u64i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !u64i, !cir.vector<1 x !u64i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}, [[AMT]] : (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>) -> !cir.vector<1 x !u64i> + +// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> +// LLVM: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> +// LLVM: [[VQSHL_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> [[VQSHL_N]], <1 x i64> splat (i64 1)) +// LLVM: ret <1 x i64> [[VQSHL_N1]] + return vqshl_n_u64(a, 1); +} + +// ALL-LABEL: @test_vqshlub_n_s8( +int8_t test_vqshlub_n_s8(int8_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<7> : !s8i +// CIR: [[AMT:%.*]] = cir.vec.insert [[IMM]], {{.*}} : !cir.vector<8 x !s8i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshlu" {{%.*}}, [[AMT]] : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i> + +// LLVM-SAME: i8 {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 +// LLVM: [[VQSHLUB_N_S8:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> [[TMP0]], <8 x i8> <i8 7, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>) +// LLVM: [[TMP1:%.*]] = extractelement <8 x i8> [[VQSHLUB_N_S8]], i64 0 +// LLVM: ret i8 [[TMP1]] + return (int8_t)vqshlub_n_s8(a, 7); +} + +// ALL-LABEL: @test_vqshluh_n_s16( +int16_t test_vqshluh_n_s16(int16_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<15> : !s16i +// CIR: [[AMT:%.*]] = cir.vec.insert [[IMM]], {{.*}} : !cir.vector<4 x !s16i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshlu" {{%.*}}, [[AMT]] : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s16i> + +// LLVM-SAME: i16 {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0 +// LLVM: [[VQSHLUH_N_S16:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> [[TMP0]], <4 x i16> <i16 15, i16 poison, i16 poison, i16 poison>) +// LLVM: [[TMP1:%.*]] = extractelement <4 x i16> [[VQSHLUH_N_S16]], i64 0 +// LLVM: ret i16 [[TMP1]] + return (int16_t)vqshluh_n_s16(a, 15); +} + +// ALL-LABEL: @test_vqshlus_n_s32( +int32_t test_vqshlus_n_s32(int32_t a) { +// CIR: [[AMT:%.*]] = cir.const #cir.int<31> : !s32i +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshlu" {{%.*}}, [[AMT]] : (!s32i, !s32i) -> !s32i + +// LLVM-SAME: i32 {{.*}}[[A:%.*]]) +// LLVM: [[VQSHLUS_N_S32:%.*]] = call i32 @llvm.aarch64.neon.sqshlu.i32(i32 [[A]], i32 31) +// LLVM: ret i32 [[VQSHLUS_N_S32]] + return (int32_t)vqshlus_n_s32(a, 31); +} + +// ALL-LABEL: @test_vqshlu_n_s64( +uint64x1_t test_vqshlu_n_s64(int64x1_t a) { +// CIR: [[IMM:%.*]] = cir.const #cir.int<1> : !u64i +// CIR: [[AMT:%.*]] = cir.vec.splat [[IMM]] : !u64i, !cir.vector<1 x !u64i> +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.sqshlu" {{%.*}}, [[AMT]] : (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>) -> !cir.vector<1 x !u64i> + +// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> +// LLVM: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> +// LLVM: [[VQSHLU_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshlu.v1i64(<1 x i64> [[VQSHLU_N]], <1 x i64> splat (i64 1)) +// LLVM: ret <1 x i64> [[VQSHLU_N1]] + return vqshlu_n_s64(a, 1); +} + //===------------------------------------------------------===// // 2.1.7.1 Negate // https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#negate _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
