https://github.com/zeyi2 updated https://github.com/llvm/llvm-project/pull/223578
>From 5317b6c8cdafca6b1831ba180870a6d679bc825d Mon Sep 17 00:00:00 2001 From: Zeyi Xu <[email protected]> Date: Tue, 15 Sep 2026 09:39:56 +0800 Subject: [PATCH 1/2] [RISCV] Fix Zibi specification link in documentation --- llvm/docs/RISCVUsage.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/docs/RISCVUsage.md b/llvm/docs/RISCVUsage.md index a3b9c0fc90a1f..ceff6a035bd1b 100644 --- a/llvm/docs/RISCVUsage.md +++ b/llvm/docs/RISCVUsage.md @@ -343,7 +343,7 @@ The primary goal of experimental support is to assist in the process of ratifica `experimental-zibi` -: LLVM implements the [0.1 release specification](https://github.com/riscv/zibi/releases/tag/v0.1.0). +: LLVM implements the [0.1 draft specification](https://github.com/riscv/zibi/blob/c7a9b9b3083b3c79a9eb27e5daf4addfb1450122/src/zibi.adoc). `experimental-zicfilp`, `experimental-zicfiss` >From d5e35bcafea3b33db593b2f6ba1367084b2d0096 Mon Sep 17 00:00:00 2001 From: Zeyi Xu <[email protected]> Date: Tue, 15 Sep 2026 10:03:15 +0800 Subject: [PATCH 2/2] bump version to 0.7 --- clang/test/Driver/print-supported-extensions-riscv.c | 2 +- clang/test/Driver/riscv-arch.c | 8 ++++---- clang/test/Preprocessor/riscv-target-features.c | 4 ++-- llvm/docs/RISCVUsage.md | 2 +- llvm/docs/ReleaseNotes.md | 1 + llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +- llvm/test/CodeGen/RISCV/attributes.ll | 4 ++-- llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 6 +++--- 8 files changed, 15 insertions(+), 14 deletions(-) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 8efe2347a56d7..287e5fefa49ab 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -250,7 +250,7 @@ // CHECK-NEXT: Experimental extensions // CHECK-NEXT: p 0.21 'P' ('Base P' (Packed SIMD)) // CHECK-NEXT: y 0.98 'Y' ('Base Y' (CHERI)) -// CHECK-NEXT: zibi 0.1 'Zibi' (Branch with Immediate) +// CHECK-NEXT: zibi 0.7 'Zibi' (Branch with Immediate) // CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) // CHECK-NEXT: zilx 0.1 'Zilx' (Indexed Integer Load Instructions) // CHECK-NEXT: zvabd 0.9 'Zvabd' (Vector Absolute Difference) diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c index 0fd389faa969f..1ad8813726a78 100644 --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -381,12 +381,12 @@ // RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izibi' // RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number -// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izibi0p7 -menable-experimental-extensions -### %s \ +// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izibi0p1 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s -// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izibi0p7' -// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental extension 'zibi' (this compiler supports 0.1) +// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izibi0p1' +// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension 'zibi' (this compiler supports 0.7) -// RUN: %clang --target=riscv32-unknown-elf -march=rv32izibi0p1 -menable-experimental-extensions -### %s \ +// RUN: %clang --target=riscv32-unknown-elf -march=rv32izibi0p7 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s // RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zibi" diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index dca3bc32f045d..9dad9e7ea9eff 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -873,10 +873,10 @@ // CHECK-ZHINXMIN-EXT: __riscv_zhinxmin 1000000{{$}} // RUN: %clang --target=riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_zibi0p1 -E -dM %s \ +// RUN: -march=rv32i_zibi0p7 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZIBI-EXT %s // RUN: %clang --target=riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_zibi0p1 -E -dM %s \ +// RUN: -march=rv64i_zibi0p7 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZIBI-EXT %s // CHECK-ZIBI-EXT: __riscv_zibi diff --git a/llvm/docs/RISCVUsage.md b/llvm/docs/RISCVUsage.md index ceff6a035bd1b..21e9245a291e8 100644 --- a/llvm/docs/RISCVUsage.md +++ b/llvm/docs/RISCVUsage.md @@ -343,7 +343,7 @@ The primary goal of experimental support is to assist in the process of ratifica `experimental-zibi` -: LLVM implements the [0.1 draft specification](https://github.com/riscv/zibi/blob/c7a9b9b3083b3c79a9eb27e5daf4addfb1450122/src/zibi.adoc). +: LLVM implements the [0.7 draft specification](https://github.com/riscv/zibi/releases/tag/riscv-isa-release-aa5e27f-2026-07-30). `experimental-zicfilp`, `experimental-zicfiss` diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 607bb0e30b058..6a2ac479c7b06 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -238,6 +238,7 @@ Makes programs 10x faster by doing Special New Thing. * Bump Svukte extension to 1.0. * Remove experimental from Zicfiss. * Added support for `Sspmp`, `Sspmpen` and `Smpmpdeleg` extensions. +* Bumped the supported version of the experimental `Zibi` extension from 0.1 to 0.7. ### Changes to the WebAssembly Backend diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 1f396b61962f0..ed7d5e25f049e 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -79,7 +79,7 @@ def FeatureStdExtE RISCVExtensionBitmask<0, 4>; def FeatureStdExtZibi - : RISCVExperimentalExtension<0, 1, "Branch with Immediate">, + : RISCVExperimentalExtension<0, 7, "Branch with Immediate">, RISCVExtensionBitmask<1, 13>; def HasStdExtZibi : Predicate<"Subtarget->hasStdExtZibi()">, AssemblerPredicate<(all_of FeatureStdExtZibi), diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 3c1e00c851fcd..129c79ac7e6bc 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -519,7 +519,7 @@ ; RV32SMCTR: .attribute 5, "rv32i2p1_smctr1p0_sscsrind1p0" ; RV32SSCTR: .attribute 5, "rv32i2p1_sscsrind1p0_ssctr1p0" ; RV32P: .attribute 5, "rv32i2p1_p0p21_zicsr2p0_zmmul1p0_zba1p0_zbb1p0" -; RV32ZIBI: .attribute 5, "rv32i2p1_zibi0p1" +; RV32ZIBI: .attribute 5, "rv32i2p1_zibi0p7" ; RV32ZVQWBDOTA8I: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqwbdota8i0p2" ; RV32ZVQWBDOTA16I: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_zvqwbdota16i0p2" ; RV32ZVFWBDOTA16BF: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfwbdota16bf0p2_zvl32b1p0" @@ -694,7 +694,7 @@ ; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0" ; RV64P: .attribute 5, "rv64i2p1_p0p21_zicsr2p0_zmmul1p0_zba1p0_zbb1p0" ; RV64Y: .attribute 5, "rv64i2p1_y0p98" -; RV64ZIBI: .attribute 5, "rv64i2p1_zibi0p1" +; RV64ZIBI: .attribute 5, "rv64i2p1_zibi0p7" ; RV64ZVQWBDOTA8I: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqwbdota8i0p2" ; RV64ZVQWBDOTA16I: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_zvqwbdota16i0p2" ; RV64ZVFWBDOTA16BF: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfwbdota16bf0p2_zvl32b1p0" diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 6abd70c1f0f32..3d1160af9ce4b 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -631,7 +631,7 @@ TEST(ParseArchString, const auto &Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 2UL); EXPECT_EQ(Exts.count("zibi"), 1U); - auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64izibi0p1", true); + auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64izibi0p7", true); ASSERT_THAT_EXPECTED(MaybeISAInfo2, Succeeded()); const auto &Exts2 = (*MaybeISAInfo2)->getExtensions(); EXPECT_EQ(Exts2.size(), 2UL); @@ -659,7 +659,7 @@ TEST(ParseArchString, RejectsUnrecognizedVersionForExperimentalExtension) { EXPECT_EQ( toString(RISCVISAInfo::parseArchString("rv64izibi9p9", true).takeError()), "unsupported version number 9.9 for experimental extension 'zibi' " - "(this compiler supports 0.1)"); + "(this compiler supports 0.7)"); EXPECT_EQ( toString(RISCVISAInfo::parseArchString("rv64y0p97", true).takeError()), "unsupported version number 0.97 for experimental extension 'y' " @@ -1640,7 +1640,7 @@ R"(All available -march extensions for RISC-V Experimental extensions p 0.21 y 0.98 - zibi 0.1 + zibi 0.7 zicfilp 1.0 This is a long dummy description zilx 0.1 zvabd 0.9 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
