================
@@ -1059,6 +980,48 @@ void rewriteIndirectReturnCall(cir::CallOp call,
call->erase();
}
+/// Whether \p ty is an eightbyte that travels in a vector register. An x87
+/// long double is floating-point but travels in neither register class, so it
+/// is excluded. A caller reads a false result as the integer class.
+bool isSSERegisterClass(mlir::Type ty) {
+ if (mlir::isa<cir::VectorType>(ty))
+ return true;
+ if (auto fp = mlir::dyn_cast<cir::FPTypeInterface>(ty))
+ return &fp.getFloatSemantics() != &llvm::APFloat::x87DoubleExtended();
+ return false;
+}
+
+/// The boundary the caller aligned \p ty to in the argument area. An
+/// alignment attribute can raise a record above what its members imply, and
+/// only the record-layout metadata carries that, so the member-derived value
+/// alone can be too small.
+uint64_t argumentAreaAlign(mlir::Type ty, mlir::ModuleOp modOp,
+ const mlir::DataLayout &dl) {
+ uint64_t align = dl.getTypeABIAlignment(ty);
+ if (auto recTy = mlir::dyn_cast<cir::RecordType>(ty))
+ if (auto layout = cir::tryGetRecordLayout(modOp, recTy.getName()))
+ align = std::max<uint64_t>(align, layout.getRecordAlign());
+ return align;
+}
+
+/// Whether an SSE-class type fits the single 16-byte vector-register slot a
+/// fetch can read from. A wider vector travels in memory no matter how many
+/// vector registers the target has, because a fetch has no declared parameter
+/// to pin it to one. The width has to be measured here rather than read off
+/// the classification, which spells a memory-class scalar the same way it
+/// spells one that really does travel in a register.
+bool fitsOneVectorSlot(mlir::Type ty, const mlir::DataLayout &dl) {
+ return dl.getTypeSize(ty).getFixedValue() <= 16;
----------------
adams381 wrote:
It does, which is what made the hardcoded 16 wrong to rely on. That helper is
gone and the classifier decides it.
https://github.com/llvm/llvm-project/pull/222420
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