https://github.com/sstwcw created
https://github.com/llvm/llvm-project/pull/224794
This patch adds the space on the left of the `:=` operator. Previously there
was only one on the right. It is the style used in the spec.
old
```SystemVerilog
x dist {[100 : 102]:= 1, 200:= 2, 300:= 5};
```
new
```SystemVerilog
x dist {[100 : 102] := 1, 200 := 2, 300 := 5};
```
>From 3c2a3a35b260a8d85999c0cbbf6939de2a0b44fa Mon Sep 17 00:00:00 2001
From: sstwcw <[email protected]>
Date: Sat, 19 Sep 2026 02:53:49 +0000
Subject: [PATCH] [clang-format] Handle Verilog dist
This patch adds the space on the left of the `:=` operator. It is the
style used in the spec. Previously there was only one on the right.
old
```SystemVerilog
x dist {[100 : 102]:= 1, 200:= 2, 300:= 5};
```
new
```SystemVerilog
x dist {[100 : 102] := 1, 200 := 2, 300 := 5};
```
---
clang/lib/Format/TokenAnnotator.cpp | 5 +++++
clang/unittests/Format/FormatTestVerilog.cpp | 10 ++++++++++
2 files changed, 15 insertions(+)
diff --git a/clang/lib/Format/TokenAnnotator.cpp
b/clang/lib/Format/TokenAnnotator.cpp
index 105c98e704c3b..b3bc5842a4011 100644
--- a/clang/lib/Format/TokenAnnotator.cpp
+++ b/clang/lib/Format/TokenAnnotator.cpp
@@ -5584,6 +5584,11 @@ bool TokenAnnotator::spaceRequiredBefore(const
AnnotatedLine &Line,
// Add space in attribute like `(* ASYNC_REG = "TRUE" *)`.
if (Left.endsSequence(tok::star, tok::l_paren) &&
Right.is(tok::identifier))
return true;
+ // Add space in the dist list like `x dist {100 := 1};`.
+ if (Right.is(tok::colon) &&
+ (Right.TokenText == ":=" || Right.TokenText == ":/")) {
+ return true;
+ }
// Add space before drive strength like in `wire (strong1, pull0)`.
if (Right.is(tok::l_paren) && Right.is(TT_VerilogStrength))
return true;
diff --git a/clang/unittests/Format/FormatTestVerilog.cpp
b/clang/unittests/Format/FormatTestVerilog.cpp
index 9baa3210dbd82..2c63cf5dd09c4 100644
--- a/clang/unittests/Format/FormatTestVerilog.cpp
+++ b/clang/unittests/Format/FormatTestVerilog.cpp
@@ -1109,6 +1109,16 @@ TEST_F(FormatTestVerilog, Operators) {
verifyFormat("req dist {1};"); // dist
verifyFormat("a inside {b, c};"); // inside
verifyFormat("bus.randomize() with { atype == low; };"); // with
+
+ verifyFormat("x dist {100 := 1, 200 := 2, 300 := 5};");
+ verifyFormat("x dist {[100 : 102] := 1, 200 := 2, 300 := 5};");
+ verifyFormat("x dist {[100 : 102] :/ 1, 200 :/ 2, 300 :/ 5};");
+ auto Style = getDefaultStyle();
+ Style.Cpp11BracedListStyle = FormatStyle::BLS_Block;
+ verifyFormat("x dist { 100 := 1, 200 := 2, 300 := 5 };", Style);
+ verifyFormat("x dist { [100 : 102] := 1, 200 := 2, 300 := 5 };", Style);
+ verifyFormat("x dist { [100 : 102] :/ 1, 200 :/ 2, 300 :/ 5 };", Style);
+ verifyFormat("a inside { b, c };", Style);
}
TEST_F(FormatTestVerilog, Preprocessor) {
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