I think this caused some unused variable warnings: ../tools/clang/lib/CodeGen/CGStmtOpenMP.cpp:360:25: warning: unused variable 'ExtInfo' [-Wunused-variable] FunctionType::ExtInfo ExtInfo; ^ 1 warning generated. [3049/3507] Building CXX object tools/clang/lib/CodeGen/CMakeFiles/clangCodeGen.dir/CGStmt.cpp.o ../tools/clang/lib/CodeGen/CGStmt.cpp:2271:25: warning: unused variable 'ExtInfo' [-Wunused-variable] FunctionType::ExtInfo ExtInfo; ^ 1 warning generated. [3068/3507] Building CXX object tools/clang/lib/CodeGen/CMakeFiles/clangCodeGen.dir/CGOpenMPRuntime.cpp.o ../tools/clang/lib/CodeGen/CGOpenMPRuntime.cpp:3926:25: warning: unused variable 'Info' [-Wunused-variable] FunctionType::ExtInfo Info; ^
I removed them in r318578. Can you double check I got it right? On Fri, Nov 17, 2017 at 9:57 AM, Alexey Bataev via cfe-commits <cfe-commits@lists.llvm.org> wrote: > Author: abataev > Date: Fri Nov 17 09:57:25 2017 > New Revision: 318536 > > URL: http://llvm.org/viewvc/llvm-project?rev=318536&view=rev > Log: > [OPENMP] Codegen for `target simd` construct. > > Added codegen support for `target simd` directive. > > Added: > cfe/trunk/test/OpenMP/target_simd_codegen.cpp > cfe/trunk/test/OpenMP/target_simd_codegen_registration.cpp > cfe/trunk/test/OpenMP/target_simd_codegen_registration_naming.cpp > Modified: > cfe/trunk/lib/Basic/OpenMPKinds.cpp > cfe/trunk/lib/CodeGen/CGOpenMPRuntime.cpp > cfe/trunk/lib/CodeGen/CGStmtOpenMP.cpp > cfe/trunk/lib/CodeGen/CodeGenFunction.h > cfe/trunk/lib/Sema/SemaOpenMP.cpp > > Modified: cfe/trunk/lib/Basic/OpenMPKinds.cpp > URL: > http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/OpenMPKinds.cpp?rev=318536&r1=318535&r2=318536&view=diff > ============================================================================== > --- cfe/trunk/lib/Basic/OpenMPKinds.cpp (original) > +++ cfe/trunk/lib/Basic/OpenMPKinds.cpp Fri Nov 17 09:57:25 2017 > @@ -894,6 +894,9 @@ void clang::getOpenMPCaptureRegions( > case OMPD_teams_distribute: > CaptureRegions.push_back(OMPD_teams); > break; > + case OMPD_target_simd: > + CaptureRegions.push_back(OMPD_target); > + break; > case OMPD_teams: > case OMPD_simd: > case OMPD_for: > @@ -909,7 +912,6 @@ void clang::getOpenMPCaptureRegions( > case OMPD_atomic: > case OMPD_target_data: > case OMPD_target: > - case OMPD_target_simd: > case OMPD_task: > case OMPD_taskloop: > case OMPD_taskloop_simd: > > Modified: cfe/trunk/lib/CodeGen/CGOpenMPRuntime.cpp > URL: > http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGOpenMPRuntime.cpp?rev=318536&r1=318535&r2=318536&view=diff > ============================================================================== > --- cfe/trunk/lib/CodeGen/CGOpenMPRuntime.cpp (original) > +++ cfe/trunk/lib/CodeGen/CGOpenMPRuntime.cpp Fri Nov 17 09:57:25 2017 > @@ -7131,6 +7131,10 @@ void CGOpenMPRuntime::scanForTargetRegio > CodeGenFunction::EmitOMPTargetParallelForSimdDeviceFunction( > CGM, ParentName, cast<OMPTargetParallelForSimdDirective>(*S)); > break; > + case Stmt::OMPTargetSimdDirectiveClass: > + CodeGenFunction::EmitOMPTargetSimdDeviceFunction( > + CGM, ParentName, cast<OMPTargetSimdDirective>(*S)); > + break; > default: > llvm_unreachable("Unknown target directive for OpenMP device > codegen."); > } > > Modified: cfe/trunk/lib/CodeGen/CGStmtOpenMP.cpp > URL: > http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGStmtOpenMP.cpp?rev=318536&r1=318535&r2=318536&view=diff > ============================================================================== > --- cfe/trunk/lib/CodeGen/CGStmtOpenMP.cpp (original) > +++ cfe/trunk/lib/CodeGen/CGStmtOpenMP.cpp Fri Nov 17 09:57:25 2017 > @@ -138,6 +138,10 @@ public: > > } // namespace > > +static void emitCommonOMPTargetDirective(CodeGenFunction &CGF, > + const OMPExecutableDirective &S, > + const RegionCodeGenTy &CodeGen); > + > LValue CodeGenFunction::EmitOMPSharedLValue(const Expr *E) { > if (auto *OrigDRE = dyn_cast<DeclRefExpr>(E)) { > if (auto *OrigVD = dyn_cast<VarDecl>(OrigDRE->getDecl())) { > @@ -1536,83 +1540,90 @@ static void emitOMPLoopBodyWithStopPoint > CGF.EmitStopPoint(&S); > } > > -void CodeGenFunction::EmitOMPSimdDirective(const OMPSimdDirective &S) { > - auto &&CodeGen = [&S](CodeGenFunction &CGF, PrePostActionTy &) { > - OMPLoopScope PreInitScope(CGF, S); > - // if (PreCond) { > - // for (IV in 0..LastIteration) BODY; > - // <Final counter/linear vars updates>; > - // } > - // > - > - // Emit: if (PreCond) - begin. > - // If the condition constant folds and can be elided, avoid emitting the > - // whole loop. > - bool CondConstant; > - llvm::BasicBlock *ContBlock = nullptr; > - if (CGF.ConstantFoldsToSimpleInteger(S.getPreCond(), CondConstant)) { > - if (!CondConstant) > - return; > - } else { > - auto *ThenBlock = CGF.createBasicBlock("simd.if.then"); > - ContBlock = CGF.createBasicBlock("simd.if.end"); > - emitPreCond(CGF, S, S.getPreCond(), ThenBlock, ContBlock, > - CGF.getProfileCount(&S)); > - CGF.EmitBlock(ThenBlock); > - CGF.incrementProfileCounter(&S); > - } > - > - // Emit the loop iteration variable. > - const Expr *IVExpr = S.getIterationVariable(); > - const VarDecl *IVDecl = > cast<VarDecl>(cast<DeclRefExpr>(IVExpr)->getDecl()); > - CGF.EmitVarDecl(*IVDecl); > - CGF.EmitIgnoredExpr(S.getInit()); > - > - // Emit the iterations count variable. > - // If it is not a variable, Sema decided to calculate iterations count on > - // each iteration (e.g., it is foldable into a constant). > - if (auto LIExpr = dyn_cast<DeclRefExpr>(S.getLastIteration())) { > - CGF.EmitVarDecl(*cast<VarDecl>(LIExpr->getDecl())); > - // Emit calculation of the iterations count. > - CGF.EmitIgnoredExpr(S.getCalcLastIteration()); > - } > - > - CGF.EmitOMPSimdInit(S); > - > - emitAlignedClause(CGF, S); > - (void)CGF.EmitOMPLinearClauseInit(S); > - { > - OMPPrivateScope LoopScope(CGF); > - CGF.EmitOMPPrivateLoopCounters(S, LoopScope); > - CGF.EmitOMPLinearClause(S, LoopScope); > - CGF.EmitOMPPrivateClause(S, LoopScope); > - CGF.EmitOMPReductionClauseInit(S, LoopScope); > - bool HasLastprivateClause = > - CGF.EmitOMPLastprivateClauseInit(S, LoopScope); > - (void)LoopScope.Privatize(); > - CGF.EmitOMPInnerLoop(S, LoopScope.requiresCleanups(), S.getCond(), > - S.getInc(), > - [&S](CodeGenFunction &CGF) { > - CGF.EmitOMPLoopBody(S, JumpDest()); > - CGF.EmitStopPoint(&S); > - }, > - [](CodeGenFunction &) {}); > - CGF.EmitOMPSimdFinal( > - S, [](CodeGenFunction &) -> llvm::Value * { return nullptr; }); > - // Emit final copy of the lastprivate variables at the end of loops. > - if (HasLastprivateClause) > - CGF.EmitOMPLastprivateClauseFinal(S, /*NoFinals=*/true); > - CGF.EmitOMPReductionClauseFinal(S, /*ReductionKind=*/OMPD_simd); > - emitPostUpdateForReductionClause( > - CGF, S, [](CodeGenFunction &) -> llvm::Value * { return nullptr; > }); > - } > - CGF.EmitOMPLinearClauseFinal( > +static void emitOMPSimdRegion(CodeGenFunction &CGF, const OMPLoopDirective > &S, > + PrePostActionTy &Action) { > + Action.Enter(CGF); > + assert(isOpenMPSimdDirective(S.getDirectiveKind()) && > + "Expected simd directive"); > + OMPLoopScope PreInitScope(CGF, S); > + // if (PreCond) { > + // for (IV in 0..LastIteration) BODY; > + // <Final counter/linear vars updates>; > + // } > + // > + > + // Emit: if (PreCond) - begin. > + // If the condition constant folds and can be elided, avoid emitting the > + // whole loop. > + bool CondConstant; > + llvm::BasicBlock *ContBlock = nullptr; > + if (CGF.ConstantFoldsToSimpleInteger(S.getPreCond(), CondConstant)) { > + if (!CondConstant) > + return; > + } else { > + auto *ThenBlock = CGF.createBasicBlock("simd.if.then"); > + ContBlock = CGF.createBasicBlock("simd.if.end"); > + emitPreCond(CGF, S, S.getPreCond(), ThenBlock, ContBlock, > + CGF.getProfileCount(&S)); > + CGF.EmitBlock(ThenBlock); > + CGF.incrementProfileCounter(&S); > + } > + > + // Emit the loop iteration variable. > + const Expr *IVExpr = S.getIterationVariable(); > + const VarDecl *IVDecl = > cast<VarDecl>(cast<DeclRefExpr>(IVExpr)->getDecl()); > + CGF.EmitVarDecl(*IVDecl); > + CGF.EmitIgnoredExpr(S.getInit()); > + > + // Emit the iterations count variable. > + // If it is not a variable, Sema decided to calculate iterations count on > + // each iteration (e.g., it is foldable into a constant). > + if (auto LIExpr = dyn_cast<DeclRefExpr>(S.getLastIteration())) { > + CGF.EmitVarDecl(*cast<VarDecl>(LIExpr->getDecl())); > + // Emit calculation of the iterations count. > + CGF.EmitIgnoredExpr(S.getCalcLastIteration()); > + } > + > + CGF.EmitOMPSimdInit(S); > + > + emitAlignedClause(CGF, S); > + (void)CGF.EmitOMPLinearClauseInit(S); > + { > + CodeGenFunction::OMPPrivateScope LoopScope(CGF); > + CGF.EmitOMPPrivateLoopCounters(S, LoopScope); > + CGF.EmitOMPLinearClause(S, LoopScope); > + CGF.EmitOMPPrivateClause(S, LoopScope); > + CGF.EmitOMPReductionClauseInit(S, LoopScope); > + bool HasLastprivateClause = CGF.EmitOMPLastprivateClauseInit(S, > LoopScope); > + (void)LoopScope.Privatize(); > + CGF.EmitOMPInnerLoop(S, LoopScope.requiresCleanups(), S.getCond(), > + S.getInc(), > + [&S](CodeGenFunction &CGF) { > + CGF.EmitOMPLoopBody(S, > CodeGenFunction::JumpDest()); > + CGF.EmitStopPoint(&S); > + }, > + [](CodeGenFunction &) {}); > + CGF.EmitOMPSimdFinal( > S, [](CodeGenFunction &) -> llvm::Value * { return nullptr; }); > - // Emit: if (PreCond) - end. > - if (ContBlock) { > - CGF.EmitBranch(ContBlock); > - CGF.EmitBlock(ContBlock, true); > - } > + // Emit final copy of the lastprivate variables at the end of loops. > + if (HasLastprivateClause) > + CGF.EmitOMPLastprivateClauseFinal(S, /*NoFinals=*/true); > + CGF.EmitOMPReductionClauseFinal(S, /*ReductionKind=*/OMPD_simd); > + emitPostUpdateForReductionClause( > + CGF, S, [](CodeGenFunction &) -> llvm::Value * { return nullptr; }); > + } > + CGF.EmitOMPLinearClauseFinal( > + S, [](CodeGenFunction &) -> llvm::Value * { return nullptr; }); > + // Emit: if (PreCond) - end. > + if (ContBlock) { > + CGF.EmitBranch(ContBlock); > + CGF.EmitBlock(ContBlock, true); > + } > +} > + > +void CodeGenFunction::EmitOMPSimdDirective(const OMPSimdDirective &S) { > + auto &&CodeGen = [&S](CodeGenFunction &CGF, PrePostActionTy &Action) { > + emitOMPSimdRegion(CGF, S, Action); > }; > OMPLexicalScope Scope(*this, S, /*AsInlined=*/true); > CGM.getOpenMPRuntime().emitInlinedDirective(*this, OMPD_simd, CodeGen); > @@ -2027,15 +2038,26 @@ void CodeGenFunction::EmitOMPDistributeS > }); > } > > +void CodeGenFunction::EmitOMPTargetSimdDeviceFunction( > + CodeGenModule &CGM, StringRef ParentName, const OMPTargetSimdDirective > &S) { > + // Emit SPMD target parallel for region as a standalone region. > + auto &&CodeGen = [&S](CodeGenFunction &CGF, PrePostActionTy &Action) { > + emitOMPSimdRegion(CGF, S, Action); > + }; > + llvm::Function *Fn; > + llvm::Constant *Addr; > + // Emit target region as a standalone region. > + CGM.getOpenMPRuntime().emitTargetOutlinedFunction( > + S, ParentName, Fn, Addr, /*IsOffloadEntry=*/true, CodeGen); > + assert(Fn && Addr && "Target device function emission failed."); > +} > + > void CodeGenFunction::EmitOMPTargetSimdDirective( > const OMPTargetSimdDirective &S) { > - OMPLexicalScope Scope(*this, S, /*AsInlined=*/true); > - CGM.getOpenMPRuntime().emitInlinedDirective( > - *this, OMPD_target_simd, [&S](CodeGenFunction &CGF, PrePostActionTy &) > { > - OMPLoopScope PreInitScope(CGF, S); > - CGF.EmitStmt( > - cast<CapturedStmt>(S.getAssociatedStmt())->getCapturedStmt()); > - }); > + auto &&CodeGen = [&S](CodeGenFunction &CGF, PrePostActionTy &Action) { > + emitOMPSimdRegion(CGF, S, Action); > + }; > + emitCommonOMPTargetDirective(*this, S, CodeGen); > } > > void CodeGenFunction::EmitOMPTeamsDistributeSimdDirective( > > Modified: cfe/trunk/lib/CodeGen/CodeGenFunction.h > URL: > http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CodeGenFunction.h?rev=318536&r1=318535&r2=318536&view=diff > ============================================================================== > --- cfe/trunk/lib/CodeGen/CodeGenFunction.h (original) > +++ cfe/trunk/lib/CodeGen/CodeGenFunction.h Fri Nov 17 09:57:25 2017 > @@ -2896,6 +2896,10 @@ public: > static void > EmitOMPTargetTeamsDeviceFunction(CodeGenModule &CGM, StringRef ParentName, > const OMPTargetTeamsDirective &S); > + /// Emit device code for the target simd directive. > + static void EmitOMPTargetSimdDeviceFunction(CodeGenModule &CGM, > + StringRef ParentName, > + const OMPTargetSimdDirective > &S); > /// \brief Emit inner loop of the worksharing/simd construct. > /// > /// \param S Directive, for which the inner loop must be emitted. > @@ -2927,6 +2931,12 @@ public: > const CodeGenLoopBoundsTy &CodeGenLoopBounds, > const CodeGenDispatchBoundsTy > &CGDispatchBounds); > > + /// Helpers for the OpenMP loop directives. > + void EmitOMPSimdInit(const OMPLoopDirective &D, bool IsMonotonic = false); > + void EmitOMPSimdFinal( > + const OMPLoopDirective &D, > + const llvm::function_ref<llvm::Value *(CodeGenFunction &)> &CondGen); > + > /// Emits the lvalue for the expression with possibly captured variable. > LValue EmitOMPSharedLValue(const Expr *E); > > @@ -2937,12 +2947,6 @@ private: > llvm::Value *EmitBlockLiteral(const CGBlockInfo &Info, > llvm::Function **InvokeF = nullptr); > > - /// Helpers for the OpenMP loop directives. > - void EmitOMPSimdInit(const OMPLoopDirective &D, bool IsMonotonic = false); > - void EmitOMPSimdFinal( > - const OMPLoopDirective &D, > - const llvm::function_ref<llvm::Value *(CodeGenFunction &)> &CondGen); > - > void EmitOMPDistributeLoop(const OMPLoopDirective &S, > const CodeGenLoopTy &CodeGenLoop, Expr > *IncExpr); > > > Modified: cfe/trunk/lib/Sema/SemaOpenMP.cpp > URL: > http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Sema/SemaOpenMP.cpp?rev=318536&r1=318535&r2=318536&view=diff > ============================================================================== > --- cfe/trunk/lib/Sema/SemaOpenMP.cpp (original) > +++ cfe/trunk/lib/Sema/SemaOpenMP.cpp Fri Nov 17 09:57:25 2017 > @@ -6823,13 +6823,24 @@ StmtResult Sema::ActOnOpenMPTargetSimdDi > // The point of exit cannot be a branch out of the structured block. > // longjmp() and throw() must not violate the entry/exit criteria. > CS->getCapturedDecl()->setNothrow(); > + for (int ThisCaptureLevel = getOpenMPCaptureLevels(OMPD_target_simd); > + ThisCaptureLevel > 1; --ThisCaptureLevel) { > + CS = cast<CapturedStmt>(CS->getCapturedStmt()); > + // 1.2.2 OpenMP Language Terminology > + // Structured block - An executable statement with a single entry at the > + // top and a single exit at the bottom. > + // The point of exit cannot be a branch out of the structured block. > + // longjmp() and throw() must not violate the entry/exit criteria. > + CS->getCapturedDecl()->setNothrow(); > + } > + > > OMPLoopDirective::HelperExprs B; > // In presence of clause 'collapse' with number of loops, it will define > the > // nested loops number. > unsigned NestedLoopCount = > CheckOpenMPLoop(OMPD_target_simd, getCollapseNumberExpr(Clauses), > - getOrderedNumberExpr(Clauses), AStmt, *this, *DSAStack, > + getOrderedNumberExpr(Clauses), CS, *this, *DSAStack, > VarsWithImplicitDSA, B); > if (NestedLoopCount == 0) > return StmtError(); > > Added: cfe/trunk/test/OpenMP/target_simd_codegen.cpp > URL: > http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/target_simd_codegen.cpp?rev=318536&view=auto > ============================================================================== > --- cfe/trunk/test/OpenMP/target_simd_codegen.cpp (added) > +++ cfe/trunk/test/OpenMP/target_simd_codegen.cpp Fri Nov 17 09:57:25 2017 > @@ -0,0 +1,675 @@ > +// Test host codegen. > +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 > +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -emit-pch -o %t %s > +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s > --check-prefix CHECK --check-prefix CHECK-64 > +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple > i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | > FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 > +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple > i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s > +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple > i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 > -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix > CHECK --check-prefix CHECK-32 > + > +// Test target codegen - host bc file has to be created first. > +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -emit-llvm-bc %s -o %t-ppc-host.bc > +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o > - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 > +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t > %s > +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc > -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix > TCHECK --check-prefix TCHECK-64 > +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple > i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o > %t-x86-host.bc > +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple > i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s > -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck > %s --check-prefix TCHECK --check-prefix TCHECK-32 > +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple > i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch > -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s > +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple > i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 > -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t > -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK > --check-prefix TCHECK-32 > + > +// expected-no-diagnostics > +#ifndef HEADER > +#define HEADER > + > +// CHECK-DAG: [[TT:%.+]] = type { i64, i8 } > +// CHECK-DAG: [[S1:%.+]] = type { double } > +// CHECK-DAG: [[ENTTY:%.+]] = type { i8*, i8*, i[[SZ:32|64]], i32, i32 } > +// CHECK-DAG: [[DEVTY:%.+]] = type { i8*, i8*, [[ENTTY]]*, [[ENTTY]]* } > +// CHECK-DAG: [[DSCTY:%.+]] = type { i32, [[DEVTY]]*, [[ENTTY]]*, [[ENTTY]]* > } > + > +// TCHECK: [[ENTTY:%.+]] = type { i8*, i8*, i{{32|64}}, i32, i32 } > + > +// CHECK-DAG: $[[REGFN:\.omp_offloading\..+]] = comdat > + > +// We have 8 target regions, but only 7 that actually will generate > offloading > +// code, only 6 will have mapped arguments, and only 4 have all-constant map > +// sizes. > + > +// CHECK-DAG: [[SIZET2:@.+]] = private unnamed_addr constant [3 x i[[SZ]]] > [i[[SZ]] 2, i[[SZ]] 4, i[[SZ]] 4] > +// CHECK-DAG: [[MAPT2:@.+]] = private unnamed_addr constant [3 x i32] [i32 > 288, i32 288, i32 288] > +// CHECK-DAG: [[SIZET3:@.+]] = private unnamed_addr constant [2 x i[[SZ]]] > [i[[SZ]] 4, i[[SZ]] 2] > +// CHECK-DAG: [[MAPT3:@.+]] = private unnamed_addr constant [2 x i32] [i32 > 288, i32 288] > +// CHECK-DAG: [[MAPT4:@.+]] = private unnamed_addr constant [9 x i32] [i32 > 288, i32 547, i32 288, i32 547, i32 547, i32 288, i32 288, i32 547, i32 547] > +// CHECK-DAG: [[SIZET5:@.+]] = private unnamed_addr constant [3 x i[[SZ]]] > [i[[SZ]] 4, i[[SZ]] 2, i[[SZ]] 40] > +// CHECK-DAG: [[MAPT5:@.+]] = private unnamed_addr constant [3 x i32] [i32 > 288, i32 288, i32 547] > +// CHECK-DAG: [[SIZET6:@.+]] = private unnamed_addr constant [4 x i[[SZ]]] > [i[[SZ]] 4, i[[SZ]] 2, i[[SZ]] 1, i[[SZ]] 40] > +// CHECK-DAG: [[MAPT6:@.+]] = private unnamed_addr constant [4 x i32] [i32 > 288, i32 288, i32 288, i32 547] > +// CHECK-DAG: [[MAPT7:@.+]] = private unnamed_addr constant [5 x i32] [i32 > 547, i32 288, i32 288, i32 288, i32 547] > +// CHECK-DAG: @{{.*}} = private constant i8 0 > +// CHECK-DAG: @{{.*}} = private constant i8 0 > +// CHECK-DAG: @{{.*}} = private constant i8 0 > +// CHECK-DAG: @{{.*}} = private constant i8 0 > +// CHECK-DAG: @{{.*}} = private constant i8 0 > +// CHECK-DAG: @{{.*}} = private constant i8 0 > +// CHECK-DAG: @{{.*}} = private constant i8 0 > + > +// TCHECK: @{{.+}} = constant [[ENTTY]] > +// TCHECK: @{{.+}} = constant [[ENTTY]] > +// TCHECK: @{{.+}} = constant [[ENTTY]] > +// TCHECK: @{{.+}} = constant [[ENTTY]] > +// TCHECK: @{{.+}} = constant [[ENTTY]] > +// TCHECK: @{{.+}} = constant [[ENTTY]] > +// TCHECK: @{{.+}} = constant [[ENTTY]] > +// TCHECK-NOT: @{{.+}} = constant [[ENTTY]] > + > +// Check if offloading descriptor is created. > +// CHECK: [[ENTBEGIN:@.+]] = external constant [[ENTTY]] > +// CHECK: [[ENTEND:@.+]] = external constant [[ENTTY]] > +// CHECK: [[DEVBEGIN:@.+]] = external constant i8 > +// CHECK: [[DEVEND:@.+]] = external constant i8 > +// CHECK: [[IMAGES:@.+]] = internal unnamed_addr constant [1 x [[DEVTY]]] > [{{.+}} { i8* [[DEVBEGIN]], i8* [[DEVEND]], [[ENTTY]]* [[ENTBEGIN]], > [[ENTTY]]* [[ENTEND]] }], comdat($[[REGFN]]) > +// CHECK: [[DESC:@.+]] = internal constant [[DSCTY]] { i32 1, [[DEVTY]]* > getelementptr inbounds ([1 x [[DEVTY]]], [1 x [[DEVTY]]]* [[IMAGES]], i32 0, > i32 0), [[ENTTY]]* [[ENTBEGIN]], [[ENTTY]]* [[ENTEND]] }, comdat($[[REGFN]]) > + > +// Check target registration is registered as a Ctor. > +// CHECK: appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, > i8* } { i32 0, void ()* bitcast (void (i8*)* @[[REGFN]] to void ()*), i8* > bitcast (void (i8*)* @[[REGFN]] to i8*) }] > + > + > +template<typename tx, typename ty> > +struct TT{ > + tx X; > + ty Y; > +}; > + > +// CHECK-LABEL: get_val > +long long get_val() { return 0; } > + > +// CHECK: define {{.*}}[[FOO:@.+]]( > +int foo(int n) { > + int a = 0; > + short aa = 0; > + float b[10]; > + float bn[n]; > + double c[5][10]; > + double cn[5][n]; > + TT<long long, char> d; > + > + // CHECK: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* > @{{[^,]+}}, i32 0, i8** null, i8** null, i[[SZ]]* null, i32* null) > + // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0 > + // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label > %[[END:[^,]+]] > + // CHECK: [[FAIL]] > + // CHECK: call void [[HVT0:@.+]]() > + // CHECK-NEXT: br label %[[END]] > + // CHECK: [[END]] > + #pragma omp target simd > + for (int i = 3; i < 32; i += 5) { > + } > + > + // CHECK: call void [[HVT1:@.+]](i[[SZ]] {{[^,]+}}, > i{{32|64}}{{[*]*}} {{[^)]+}}) > + long long k = get_val(); > + #pragma omp target simd if(target: 0) linear(k : 3) > + for (int i = 10; i > 1; i--) { > + a += 1; > + } > + > + // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* > @{{[^,]+}}, i32 3, i8** [[BP:%[^,]+]], i8** [[P:%[^,]+]], i[[SZ]]* > getelementptr inbounds ([3 x i[[SZ]]], [3 x i[[SZ]]]* [[SIZET2]], i32 0, i32 > 0), i32* getelementptr inbounds ([3 x i32], [3 x i32]* [[MAPT2]], i32 0, i32 > 0)) > + // CHECK-DAG: [[BP]] = getelementptr inbounds [3 x i8*], [3 x i8*]* > [[BPR:%[^,]+]], i32 0, i32 0 > + // CHECK-DAG: [[P]] = getelementptr inbounds [3 x i8*], [3 x i8*]* > [[PR:%[^,]+]], i32 0, i32 0 > + // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [3 x i8*], [3 x > i8*]* [[BPR]], i32 0, i32 0 > + // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [3 x i8*], [3 x > i8*]* [[PR]], i32 0, i32 0 > + // CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to i[[SZ]]* > + // CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to i[[SZ]]* > + // CHECK-DAG: store i[[SZ]] [[VAL0:%.+]], i[[SZ]]* [[CBPADDR0]], > + // CHECK-DAG: store i[[SZ]] [[VAL0]], i[[SZ]]* [[CPADDR0]], > + // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [3 x i8*], [3 x > i8*]* [[BPR]], i32 0, i32 1 > + // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [3 x i8*], [3 x > i8*]* [[PR]], i32 0, i32 1 > + // CHECK-DAG: [[CBPADDR1:%.+]] = bitcast i8** [[BPADDR1]] to i[[SZ]]* > + // CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]* > + // CHECK-DAG: store i[[SZ]] [[VAL1:%.+]], i[[SZ]]* [[CBPADDR1]], > + // CHECK-DAG: store i[[SZ]] [[VAL1]], i[[SZ]]* [[CPADDR1]], > + // CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [3 x i8*], [3 x > i8*]* [[BPR]], i32 0, i32 1 > + // CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [3 x i8*], [3 x > i8*]* [[PR]], i32 0, i32 1 > + // CHECK-DAG: [[CBPADDR2:%.+]] = bitcast i8** [[BPADDR2]] to i[[SZ]]* > + // CHECK-DAG: [[CPADDR2:%.+]] = bitcast i8** [[PADDR2]] to i[[SZ]]* > + // CHECK-DAG: store i[[SZ]] [[VAL2:%.+]], i[[SZ]]* [[CBPADDR2]], > + // CHECK-DAG: store i[[SZ]] [[VAL2]], i[[SZ]]* [[CPADDR2]], > + > + // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0 > + // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label > %[[END:[^,]+]] > + // CHECK: [[FAIL]] > + // CHECK: call void [[HVT2:@.+]](i[[SZ]] {{[^,]+}}, i[[SZ]] > {{[^)]+}}) > + // CHECK-NEXT: br label %[[END]] > + // CHECK: [[END]] > + int lin = 12; > + #pragma omp target simd if(target: 1) linear(lin, a : get_val()) > + for (unsigned long long it = 2000; it >= 600; it-=400) { > + aa += 1; > + } > + > + // CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 10 > + // CHECK: br i1 [[IF]], label %[[IFTHEN:[^,]+]], label > %[[IFELSE:[^,]+]] > + // CHECK: [[IFTHEN]] > + // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* > @{{[^,]+}}, i32 2, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* > getelementptr inbounds ([2 x i[[SZ]]], [2 x i[[SZ]]]* [[SIZET3]], i32 0, i32 > 0), i32* getelementptr inbounds ([2 x i32], [2 x i32]* [[MAPT3]], i32 0, i32 > 0)) > + // CHECK-DAG: [[BPR]] = getelementptr inbounds [2 x i8*], [2 x i8*]* > [[BP:%[^,]+]], i32 0, i32 0 > + // CHECK-DAG: [[PR]] = getelementptr inbounds [2 x i8*], [2 x i8*]* > [[P:%[^,]+]], i32 0, i32 0 > + > + // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x > i8*]* [[BP]], i32 0, i32 0 > + // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x > i8*]* [[P]], i32 0, i32 0 > + // CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to i[[SZ]]* > + // CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to i[[SZ]]* > + // CHECK-DAG: store i[[SZ]] [[VAL0:%.+]], i[[SZ]]* [[CBPADDR0]], > + // CHECK-DAG: store i[[SZ]] [[VAL0]], i[[SZ]]* [[CPADDR0]], > + > + // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [2 x i8*], [2 x > i8*]* [[BP]], i32 0, i32 1 > + // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [2 x i8*], [2 x > i8*]* [[P]], i32 0, i32 1 > + // CHECK-DAG: [[CBPADDR1:%.+]] = bitcast i8** [[BPADDR1]] to i[[SZ]]* > + // CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]* > + // CHECK-DAG: store i[[SZ]] [[VAL1:%.+]], i[[SZ]]* [[CBPADDR1]], > + // CHECK-DAG: store i[[SZ]] [[VAL1]], i[[SZ]]* [[CPADDR1]], > + // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0 > + // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]] > + // CHECK: [[FAIL]] > + // CHECK: call void [[HVT3:@.+]]({{[^,]+}}, {{[^,]+}}) > + // CHECK-NEXT: br label %[[END]] > + // CHECK: [[END]] > + // CHECK-NEXT: br label %[[IFEND:.+]] > + // CHECK: [[IFELSE]] > + // CHECK: call void [[HVT3]]({{[^,]+}}, {{[^,]+}}) > + // CHECK-NEXT: br label %[[IFEND]] > + // CHECK: [[IFEND]] > + > + #pragma omp target simd if(target: n>10) > + for (short it = 6; it <= 20; it-=-4) { > + a += 1; > + aa += 1; > + } > + > + // We capture 3 VLA sizes in this target region > + // CHECK-64: [[A_VAL:%.+]] = load i32, i32* %{{.+}}, > + // CHECK-64: [[A_ADDR:%.+]] = bitcast i[[SZ]]* [[A_CADDR:%.+]] to > i32* > + // CHECK-64: store i32 [[A_VAL]], i32* [[A_ADDR]], > + // CHECK-64: [[A_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[A_CADDR]], > + > + // CHECK-32: [[A_VAL:%.+]] = load i32, i32* %{{.+}}, > + // CHECK-32: store i32 [[A_VAL]], i32* [[A_CADDR:%.+]], > + // CHECK-32: [[A_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[A_CADDR]], > + > + // CHECK: [[BNSIZE:%.+]] = mul nuw i[[SZ]] [[VLA0:%.+]], 4 > + // CHECK: [[CNELEMSIZE2:%.+]] = mul nuw i[[SZ]] 5, [[VLA1:%.+]] > + // CHECK: [[CNSIZE:%.+]] = mul nuw i[[SZ]] [[CNELEMSIZE2]], 8 > + > + // CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 20 > + // CHECK: br i1 [[IF]], label %[[TRY:[^,]+]], label %[[FAIL:[^,]+]] > + // CHECK: [[TRY]] > + // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* > @{{[^,]+}}, i32 9, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* > [[SR:%[^,]+]], i32* getelementptr inbounds ([9 x i32], [9 x i32]* [[MAPT4]], > i32 0, i32 0)) > + // CHECK-DAG: [[BPR]] = getelementptr inbounds [9 x i8*], [9 x i8*]* > [[BP:%[^,]+]], i32 0, i32 0 > + // CHECK-DAG: [[PR]] = getelementptr inbounds [9 x i8*], [9 x i8*]* > [[P:%[^,]+]], i32 0, i32 0 > + // CHECK-DAG: [[SR]] = getelementptr inbounds [9 x i[[SZ]]], [9 x > i[[SZ]]]* [[S:%[^,]+]], i32 0, i32 0 > + > + // CHECK-DAG: [[SADDR0:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 > x i[[SZ]]]* [[S]], i32 0, i32 [[IDX0:[0-9]+]] > + // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [9 x i8*], [9 x > i8*]* [[BP]], i32 0, i32 [[IDX0]] > + // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [9 x i8*], [9 x > i8*]* [[P]], i32 0, i32 [[IDX0]] > + // CHECK-DAG: [[SADDR1:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 > x i[[SZ]]]* [[S]], i32 0, i32 [[IDX1:[0-9]+]] > + // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [9 x i8*], [9 x > i8*]* [[BP]], i32 0, i32 [[IDX1]] > + // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [9 x i8*], [9 x > i8*]* [[P]], i32 0, i32 [[IDX1]] > + // CHECK-DAG: [[SADDR2:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 > x i[[SZ]]]* [[S]], i32 0, i32 [[IDX2:[0-9]+]] > + // CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [9 x i8*], [9 x > i8*]* [[BP]], i32 0, i32 [[IDX2]] > + // CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [9 x i8*], [9 x > i8*]* [[P]], i32 0, i32 [[IDX2]] > + // CHECK-DAG: [[SADDR3:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 > x i[[SZ]]]* [[S]], i32 0, i32 [[IDX3:[0-9]+]] > + // CHECK-DAG: [[BPADDR3:%.+]] = getelementptr inbounds [9 x i8*], [9 x > i8*]* [[BP]], i32 0, i32 [[IDX3]] > + // CHECK-DAG: [[PADDR3:%.+]] = getelementptr inbounds [9 x i8*], [9 x > i8*]* [[P]], i32 0, i32 [[IDX3]] > + // CHECK-DAG: [[SADDR4:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 > x i[[SZ]]]* [[S]], i32 0, i32 [[IDX4:[0-9]+]] > + // CHECK-DAG: [[BPADDR4:%.+]] = getelementptr inbounds [9 x i8*], [9 x > i8*]* [[BP]], i32 0, i32 [[IDX4]] > + // CHECK-DAG: [[PADDR4:%.+]] = getelementptr inbounds [9 x i8*], [9 x > i8*]* [[P]], i32 0, i32 [[IDX4]] > + // CHECK-DAG: [[SADDR5:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 > x i[[SZ]]]* [[S]], i32 0, i32 [[IDX5:[0-9]+]] > + // CHECK-DAG: [[BPADDR5:%.+]] = getelementptr inbounds [9 x i8*], [9 x > i8*]* [[BP]], i32 0, i32 [[IDX5]] > + // CHECK-DAG: [[PADDR5:%.+]] = getelementptr inbounds [9 x i8*], [9 x > i8*]* [[P]], i32 0, i32 [[IDX5]] > + // CHECK-DAG: [[SADDR6:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 > x i[[SZ]]]* [[S]], i32 0, i32 [[IDX6:[0-9]+]] > + // CHECK-DAG: [[BPADDR6:%.+]] = getelementptr inbounds [9 x i8*], [9 x > i8*]* [[BP]], i32 0, i32 [[IDX6]] > + // CHECK-DAG: [[PADDR6:%.+]] = getelementptr inbounds [9 x i8*], [9 x > i8*]* [[P]], i32 0, i32 [[IDX6]] > + // CHECK-DAG: [[SADDR7:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 > x i[[SZ]]]* [[S]], i32 0, i32 [[IDX7:[0-9]+]] > + // CHECK-DAG: [[BPADDR7:%.+]] = getelementptr inbounds [9 x i8*], [9 x > i8*]* [[BP]], i32 0, i32 [[IDX7]] > + // CHECK-DAG: [[PADDR7:%.+]] = getelementptr inbounds [9 x i8*], [9 x > i8*]* [[P]], i32 0, i32 [[IDX7]] > + // CHECK-DAG: [[SADDR8:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 > x i[[SZ]]]* [[S]], i32 0, i32 [[IDX8:[0-9]+]] > + // CHECK-DAG: [[BPADDR8:%.+]] = getelementptr inbounds [9 x i8*], [9 x > i8*]* [[BP]], i32 0, i32 [[IDX8]] > + // CHECK-DAG: [[PADDR8:%.+]] = getelementptr inbounds [9 x i8*], [9 x > i8*]* [[P]], i32 0, i32 [[IDX8]] > + > + // The names below are not necessarily consistent with the names used for > the > + // addresses above as some are repeated. > + // CHECK-DAG: store i[[SZ]] [[VLA0]], i[[SZ]]* [[CBPADDR0:%.+]], > + // CHECK-DAG: store i[[SZ]] [[VLA0]], i[[SZ]]* [[CPADDR0:%.+]], > + // CHECK-DAG: [[CBPADDR0]] = bitcast i8** {{%[^,]+}} to i[[SZ]]* > + // CHECK-DAG: [[CPADDR0]] = bitcast i8** {{%[^,]+}} to i[[SZ]]* > + // CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* {{%[^,]+}} > + > + // CHECK-DAG: store i[[SZ]] [[VLA1]], i[[SZ]]* [[CBPADDR1:%.+]], > + // CHECK-DAG: store i[[SZ]] [[VLA1]], i[[SZ]]* [[CPADDR1:%.+]], > + // CHECK-DAG: [[CBPADDR1]] = bitcast i8** {{%[^,]+}} to i[[SZ]]* > + // CHECK-DAG: [[CPADDR1]] = bitcast i8** {{%[^,]+}} to i[[SZ]]* > + // CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* {{%[^,]+}} > + > + // CHECK-DAG: store i[[SZ]] 5, i[[SZ]]* [[CBPADDR2:%.+]], > + // CHECK-DAG: store i[[SZ]] 5, i[[SZ]]* [[CPADDR2:%.+]], > + // CHECK-DAG: [[CBPADDR2]] = bitcast i8** {{%[^,]+}} to i[[SZ]]* > + // CHECK-DAG: [[CPADDR2]] = bitcast i8** {{%[^,]+}} to i[[SZ]]* > + // CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* {{%[^,]+}} > + > + // CHECK-DAG: store i[[SZ]] [[A_CVAL]], i[[SZ]]* [[CBPADDR3:%.+]], > + // CHECK-DAG: store i[[SZ]] [[A_CVAL]], i[[SZ]]* [[CPADDR3:%.+]], > + // CHECK-DAG: [[CBPADDR3]] = bitcast i8** {{%[^,]+}} to i[[SZ]]* > + // CHECK-DAG: [[CPADDR3]] = bitcast i8** {{%[^,]+}} to i[[SZ]]* > + // CHECK-DAG: store i[[SZ]] 4, i[[SZ]]* {{%[^,]+}} > + > + // CHECK-DAG: store [10 x float]* %{{.+}}, [10 x float]** > [[CBPADDR4:%.+]], > + // CHECK-DAG: store [10 x float]* %{{.+}}, [10 x float]** > [[CPADDR4:%.+]], > + // CHECK-DAG: [[CBPADDR4]] = bitcast i8** {{%[^,]+}} to [10 x float]** > + // CHECK-DAG: [[CPADDR4]] = bitcast i8** {{%[^,]+}} to [10 x float]** > + // CHECK-DAG: store i[[SZ]] 40, i[[SZ]]* {{%[^,]+}} > + > + // CHECK-DAG: store float* %{{.+}}, float** [[CBPADDR5:%.+]], > + // CHECK-DAG: store float* %{{.+}}, float** [[CPADDR5:%.+]], > + // CHECK-DAG: [[CBPADDR5]] = bitcast i8** {{%[^,]+}} to float** > + // CHECK-DAG: [[CPADDR5]] = bitcast i8** {{%[^,]+}} to float** > + // CHECK-DAG: store i[[SZ]] [[BNSIZE]], i[[SZ]]* {{%[^,]+}} > + > + // CHECK-DAG: store [5 x [10 x double]]* %{{.+}}, [5 x [10 x double]]** > [[CBPADDR6:%.+]], > + // CHECK-DAG: store [5 x [10 x double]]* %{{.+}}, [5 x [10 x double]]** > [[CPADDR6:%.+]], > + // CHECK-DAG: [[CBPADDR6]] = bitcast i8** {{%[^,]+}} to [5 x [10 x > double]]** > + // CHECK-DAG: [[CPADDR6]] = bitcast i8** {{%[^,]+}} to [5 x [10 x > double]]** > + // CHECK-DAG: store i[[SZ]] 400, i[[SZ]]* {{%[^,]+}} > + > + // CHECK-DAG: store double* %{{.+}}, double** [[CBPADDR7:%.+]], > + // CHECK-DAG: store double* %{{.+}}, double** [[CPADDR7:%.+]], > + // CHECK-DAG: [[CBPADDR7]] = bitcast i8** {{%[^,]+}} to double** > + // CHECK-DAG: [[CPADDR7]] = bitcast i8** {{%[^,]+}} to double** > + // CHECK-DAG: store i[[SZ]] [[CNSIZE]], i[[SZ]]* {{%[^,]+}} > + > + // CHECK-DAG: store [[TT]]* %{{.+}}, [[TT]]** [[CBPADDR8:%.+]], > + // CHECK-DAG: store [[TT]]* %{{.+}}, [[TT]]** [[CPADDR8:%.+]], > + // CHECK-DAG: [[CBPADDR8]] = bitcast i8** {{%[^,]+}} to [[TT]]** > + // CHECK-DAG: [[CPADDR8]] = bitcast i8** {{%[^,]+}} to [[TT]]** > + // CHECK-DAG: store i[[SZ]] {{12|16}}, i[[SZ]]* {{%[^,]+}} > + > + // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0 > + // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label > %[[END:[^,]+]] > + > + // CHECK: [[FAIL]] > + // CHECK: call void [[HVT4:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, > {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}) > + // CHECK-NEXT: br label %[[END]] > + // CHECK: [[END]] > + #pragma omp target simd if(target: n>20) > + for (unsigned char it = 'z'; it >= 'a'; it+=-1) { > + a += 1; > + b[2] += 1.0; > + bn[3] += 1.0; > + c[1][2] += 1.0; > + cn[1][3] += 1.0; > + d.X += 1; > + d.Y += 1; > + } > + > + return a; > +} > + > +// Check that the offloading functions are emitted and that the arguments are > +// correct and loaded correctly for the target regions in foo(). > + > +// CHECK: define internal void [[HVT0]]() > +// CHECK: !llvm.loop > +// CHECK: ret void > +// CHECK-NEXT: } > + > + > +// CHECK: define internal void [[HVT1]](i[[SZ]] %{{.+}}, > i{{32|64}}{{[*]*.*}} %{{.+}}) > +// CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align > +// CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align > +// CHECK-64: [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i32* > +// CHECK-64: [[AA:%.+]] = load i32, i32* [[AA_CADDR]], align > +// CHECK-32: [[AA:%.+]] = load i32, i32* [[AA_ADDR]], align > +// CHECK: !llvm.mem.parallel_loop_access > +// CHECK: !llvm.loop > +// CHECK: ret void > +// CHECK-NEXT: } > + > +// CHECK: define internal void [[HVT2]](i[[SZ]] %{{.+}}, i[[SZ]] > %{{.+}}, i[[SZ]] %{{.+}}) > +// CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align > +// CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align > +// CHECK: [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i16* > +// CHECK: [[AA:%.+]] = load i16, i16* [[AA_CADDR]], align > +// CHECK: !llvm.loop > +// CHECK: ret void > +// CHECK-NEXT: } > + > +// CHECK: define internal void [[HVT3]] > +// CHECK: [[A_ADDR:%.+]] = alloca i[[SZ]], align > +// CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align > +// CHECK-DAG: store i[[SZ]] %{{.+}}, i[[SZ]]* [[A_ADDR]], align > +// CHECK-DAG: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align > +// CHECK-64-DAG:[[A_CADDR:%.+]] = bitcast i[[SZ]]* [[A_ADDR]] to i32* > +// CHECK-DAG: [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i16* > +// CHECK: !llvm.loop > +// CHECK: ret void > +// CHECK-NEXT: } > + > +// CHECK: define internal void [[HVT4]] > +// Create local storage for each capture. > +// CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]] > +// CHECK: [[LOCAL_B:%.+]] = alloca [10 x float]* > +// CHECK: [[LOCAL_VLA1:%.+]] = alloca i[[SZ]] > +// CHECK: [[LOCAL_BN:%.+]] = alloca float* > +// CHECK: [[LOCAL_C:%.+]] = alloca [5 x [10 x double]]* > +// CHECK: [[LOCAL_VLA2:%.+]] = alloca i[[SZ]] > +// CHECK: [[LOCAL_VLA3:%.+]] = alloca i[[SZ]] > +// CHECK: [[LOCAL_CN:%.+]] = alloca double* > +// CHECK: [[LOCAL_D:%.+]] = alloca [[TT]]* > +// CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]] > +// CHECK-DAG: store [10 x float]* [[ARG_B:%.+]], [10 x float]** [[LOCAL_B]] > +// CHECK-DAG: store i[[SZ]] [[ARG_VLA1:%.+]], i[[SZ]]* [[LOCAL_VLA1]] > +// CHECK-DAG: store float* [[ARG_BN:%.+]], float** [[LOCAL_BN]] > +// CHECK-DAG: store [5 x [10 x double]]* [[ARG_C:%.+]], [5 x [10 x > double]]** [[LOCAL_C]] > +// CHECK-DAG: store i[[SZ]] [[ARG_VLA2:%.+]], i[[SZ]]* [[LOCAL_VLA2]] > +// CHECK-DAG: store i[[SZ]] [[ARG_VLA3:%.+]], i[[SZ]]* [[LOCAL_VLA3]] > +// CHECK-DAG: store double* [[ARG_CN:%.+]], double** [[LOCAL_CN]] > +// CHECK-DAG: store [[TT]]* [[ARG_D:%.+]], [[TT]]** [[LOCAL_D]] > + > +// CHECK-64-DAG:[[CONV_AP:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32* > +// CHECK-DAG: [[REF_B:%.+]] = load [10 x float]*, [10 x float]** > [[LOCAL_B]], > +// CHECK-DAG: [[VAL_VLA1:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA1]], > +// CHECK-DAG: [[REF_BN:%.+]] = load float*, float** [[LOCAL_BN]], > +// CHECK-DAG: [[REF_C:%.+]] = load [5 x [10 x double]]*, [5 x [10 x > double]]** [[LOCAL_C]], > +// CHECK-DAG: [[VAL_VLA2:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA2]], > +// CHECK-DAG: [[VAL_VLA3:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA3]], > +// CHECK-DAG: [[REF_CN:%.+]] = load double*, double** [[LOCAL_CN]], > +// CHECK-DAG: [[REF_D:%.+]] = load [[TT]]*, [[TT]]** [[LOCAL_D]], > + > + > +template<typename tx> > +tx ftemplate(int n) { > + tx a = 0; > + short aa = 0; > + tx b[10]; > + > + #pragma omp target simd if(target: n>40) > + for (long long i = -10; i < 10; i += 3) { > + a += 1; > + aa += 1; > + b[2] += 1; > + } > + > + return a; > +} > + > +static > +int fstatic(int n) { > + int a = 0; > + short aa = 0; > + char aaa = 0; > + int b[10]; > + > + #pragma omp target simd if(target: n>50) > + for (unsigned i=100; i<10; i+=10) { > + a += 1; > + aa += 1; > + aaa += 1; > + b[2] += 1; > + } > + > + return a; > +} > + > +struct S1 { > + double a; > + > + int r1(int n){ > + int b = n+1; > + short int c[2][n]; > + > + #pragma omp target simd if(target: n>60) > + for (unsigned long long it = 2000; it >= 600; it -= 400) { > + this->a = (double)b + 1.5; > + c[1][1] = ++a; > + } > + > + return c[1][1] + (int)b; > + } > +}; > + > +// CHECK: define {{.*}}@{{.*}}bar{{.*}} > +int bar(int n){ > + int a = 0; > + > + // CHECK: call {{.*}}i32 [[FOO]](i32 {{.*}}) > + a += foo(n); > + > + S1 S; > + // CHECK: call {{.*}}i32 [[FS1:@.+]]([[S1]]* {{.*}}, i32 {{.*}}) > + a += S.r1(n); > + > + // CHECK: call {{.*}}i32 [[FSTATIC:@.+]](i32 {{.*}}) > + a += fstatic(n); > + > + // CHECK: call {{.*}}i32 [[FTEMPLATE:@.+]](i32 {{.*}}) > + a += ftemplate<int>(n); > + > + return a; > +} > + > +// > +// CHECK: define {{.*}}[[FS1]] > +// > +// CHECK: i8* @llvm.stacksave() > +// CHECK-64: [[B_ADDR:%.+]] = bitcast i[[SZ]]* [[B_CADDR:%.+]] to i32* > +// CHECK-64: store i32 %{{.+}}, i32* [[B_ADDR]], > +// CHECK-64: [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_CADDR]], > + > +// CHECK-32: store i32 %{{.+}}, i32* [[B_ADDR:%.+]], > +// CHECK-32: [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_ADDR]], > + > +// We capture 2 VLA sizes in this target region > +// CHECK: [[CELEMSIZE2:%.+]] = mul nuw i[[SZ]] 2, [[VLA0:%.+]] > +// CHECK: [[CSIZE:%.+]] = mul nuw i[[SZ]] [[CELEMSIZE2]], 2 > + > +// CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 60 > +// CHECK: br i1 [[IF]], label %[[TRY:[^,]+]], label %[[FAIL:[^,]+]] > +// CHECK: [[TRY]] > +// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, > i32 5, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* [[SR:%[^,]+]], i32* > getelementptr inbounds ([5 x i32], [5 x i32]* [[MAPT7]], i32 0, i32 0)) > +// CHECK-DAG: [[BPR]] = getelementptr inbounds [5 x i8*], [5 x i8*]* > [[BP:%.+]], i32 0, i32 0 > +// CHECK-DAG: [[PR]] = getelementptr inbounds [5 x i8*], [5 x i8*]* > [[P:%.+]], i32 0, i32 0 > +// CHECK-DAG: [[SR]] = getelementptr inbounds [5 x i[[SZ]]], [5 x > i[[SZ]]]* [[S:%.+]], i32 0, i32 0 > +// CHECK-DAG: [[SADDR0:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x > i[[SZ]]]* [[S]], i32 [[IDX0:[0-9]+]] > +// CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [5 x i8*], [5 x > i8*]* [[BP]], i32 [[IDX0]] > +// CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [5 x i8*], [5 x > i8*]* [[P]], i32 [[IDX0]] > +// CHECK-DAG: [[SADDR1:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x > i[[SZ]]]* [[S]], i32 [[IDX1:[0-9]+]] > +// CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [5 x i8*], [5 x > i8*]* [[BP]], i32 [[IDX1]] > +// CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [5 x i8*], [5 x > i8*]* [[P]], i32 [[IDX1]] > +// CHECK-DAG: [[SADDR2:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x > i[[SZ]]]* [[S]], i32 [[IDX2:[0-9]+]] > +// CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [5 x i8*], [5 x > i8*]* [[BP]], i32 [[IDX2]] > +// CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [5 x i8*], [5 x > i8*]* [[P]], i32 [[IDX2]] > +// CHECK-DAG: [[SADDR3:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x > i[[SZ]]]* [[S]], i32 [[IDX3:[0-9]+]] > +// CHECK-DAG: [[BPADDR3:%.+]] = getelementptr inbounds [5 x i8*], [5 x > i8*]* [[BP]], i32 [[IDX3]] > +// CHECK-DAG: [[PADDR3:%.+]] = getelementptr inbounds [5 x i8*], [5 x > i8*]* [[P]], i32 [[IDX3]] > + > +// The names below are not necessarily consistent with the names used for the > +// addresses above as some are repeated. > +// CHECK-DAG: store i[[SZ]] [[VLA0]], i[[SZ]]* [[CBPADDR0:%.+]], > +// CHECK-DAG: store i[[SZ]] [[VLA0]], i[[SZ]]* [[CPADDR0:%.+]], > +// CHECK-DAG: [[CBPADDR0]] = bitcast i8** {{%[^,]+}} to i[[SZ]]* > +// CHECK-DAG: [[CPADDR0]] = bitcast i8** {{%[^,]+}} to i[[SZ]]* > +// CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* {{%[^,]+}} > + > +// CHECK-DAG: store i[[SZ]] 2, i[[SZ]]* [[CBPADDR1:%.+]], > +// CHECK-DAG: store i[[SZ]] 2, i[[SZ]]* [[CPADDR1:%.+]], > +// CHECK-DAG: [[CBPADDR1]] = bitcast i8** {{%[^,]+}} to i[[SZ]]* > +// CHECK-DAG: [[CPADDR1]] = bitcast i8** {{%[^,]+}} to i[[SZ]]* > +// CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* {{%[^,]+}} > + > +// CHECK-DAG: store i[[SZ]] [[B_CVAL]], i[[SZ]]* [[CBPADDR2:%.+]], > +// CHECK-DAG: store i[[SZ]] [[B_CVAL]], i[[SZ]]* [[CPADDR2:%.+]], > +// CHECK-DAG: [[CBPADDR2]] = bitcast i8** {{%[^,]+}} to i[[SZ]]* > +// CHECK-DAG: [[CPADDR2]] = bitcast i8** {{%[^,]+}} to i[[SZ]]* > +// CHECK-DAG: store i[[SZ]] 4, i[[SZ]]* {{%[^,]+}} > + > +// CHECK-DAG: store [[S1]]* %{{.+}}, [[S1]]** [[CBPADDR3:%.+]], > +// CHECK-DAG: store [[S1]]* %{{.+}}, [[S1]]** [[CPADDR3:%.+]], > +// CHECK-DAG: [[CBPADDR3]] = bitcast i8** {{%[^,]+}} to [[S1]]** > +// CHECK-DAG: [[CPADDR3]] = bitcast i8** {{%[^,]+}} to [[S1]]** > +// CHECK-DAG: store i[[SZ]] 8, i[[SZ]]* {{%[^,]+}} > + > +// CHECK-DAG: store i16* %{{.+}}, i16** [[CBPADDR4:%.+]], > +// CHECK-DAG: store i16* %{{.+}}, i16** [[CPADDR4:%.+]], > +// CHECK-DAG: [[CBPADDR4]] = bitcast i8** {{%[^,]+}} to i16** > +// CHECK-DAG: [[CPADDR4]] = bitcast i8** {{%[^,]+}} to i16** > +// CHECK-DAG: store i[[SZ]] [[CSIZE]], i[[SZ]]* {{%[^,]+}} > + > +// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0 > +// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]] > + > +// CHECK: [[FAIL]] > +// CHECK: call void [[HVT7:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, > {{[^,]+}}, {{[^,]+}}) > +// CHECK-NEXT: br label %[[END]] > +// CHECK: [[END]] > + > +// > +// CHECK: define {{.*}}[[FSTATIC]] > +// > +// CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 50 > +// CHECK: br i1 [[IF]], label %[[IFTHEN:[^,]+]], label > %[[IFELSE:[^,]+]] > +// CHECK: [[IFTHEN]] > +// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, > i32 4, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* getelementptr > inbounds ([4 x i[[SZ]]], [4 x i[[SZ]]]* [[SIZET6]], i32 0, i32 0), i32* > getelementptr inbounds ([4 x i32], [4 x i32]* [[MAPT6]], i32 0, i32 0)) > +// CHECK-DAG: [[BPR]] = getelementptr inbounds [4 x i8*], [4 x i8*]* > [[BP:%.+]], i32 0, i32 0 > +// CHECK-DAG: [[PR]] = getelementptr inbounds [4 x i8*], [4 x i8*]* > [[P:%.+]], i32 0, i32 0 > + > +// CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [4 x i8*], [4 x > i8*]* [[BP]], i32 0, i32 0 > +// CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [4 x i8*], [4 x > i8*]* [[P]], i32 0, i32 0 > +// CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to i[[SZ]]* > +// CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to i[[SZ]]* > +// CHECK-DAG: store i[[SZ]] [[VAL0:%.+]], i[[SZ]]* [[CBPADDR0]], > +// CHECK-DAG: store i[[SZ]] [[VAL0]], i[[SZ]]* [[CPADDR0]], > + > +// CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [4 x i8*], [4 x > i8*]* [[BP]], i32 0, i32 1 > +// CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [4 x i8*], [4 x > i8*]* [[P]], i32 0, i32 1 > +// CHECK-DAG: [[CBPADDR1:%.+]] = bitcast i8** [[BPADDR1]] to i[[SZ]]* > +// CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]* > +// CHECK-DAG: store i[[SZ]] [[VAL1:%.+]], i[[SZ]]* [[CBPADDR1]], > +// CHECK-DAG: store i[[SZ]] [[VAL1]], i[[SZ]]* [[CPADDR1]], > + > +// CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [4 x i8*], [4 x > i8*]* [[BP]], i32 0, i32 2 > +// CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [4 x i8*], [4 x > i8*]* [[P]], i32 0, i32 2 > +// CHECK-DAG: [[CBPADDR2:%.+]] = bitcast i8** [[BPADDR2]] to i[[SZ]]* > +// CHECK-DAG: [[CPADDR2:%.+]] = bitcast i8** [[PADDR2]] to i[[SZ]]* > +// CHECK-DAG: store i[[SZ]] [[VAL2:%.+]], i[[SZ]]* [[CBPADDR2]], > +// CHECK-DAG: store i[[SZ]] [[VAL2]], i[[SZ]]* [[CPADDR2]], > + > +// CHECK-DAG: [[BPADDR3:%.+]] = getelementptr inbounds [4 x i8*], [4 x > i8*]* [[BP]], i32 0, i32 3 > +// CHECK-DAG: [[PADDR3:%.+]] = getelementptr inbounds [4 x i8*], [4 x > i8*]* [[P]], i32 0, i32 3 > +// CHECK-DAG: [[CBPADDR3:%.+]] = bitcast i8** [[BPADDR3]] to [10 x i32]** > +// CHECK-DAG: [[CPADDR3:%.+]] = bitcast i8** [[PADDR3]] to [10 x i32]** > +// CHECK-DAG: store [10 x i32]* [[VAL3:%.+]], [10 x i32]** [[CBPADDR3]], > +// CHECK-DAG: store [10 x i32]* [[VAL3]], [10 x i32]** [[CPADDR3]], > + > +// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0 > +// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]] > +// CHECK: [[FAIL]] > +// CHECK: call void [[HVT6:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, > {{[^,]+}}) > +// CHECK-NEXT: br label %[[END]] > +// CHECK: [[END]] > +// CHECK-NEXT: br label %[[IFEND:.+]] > +// CHECK: [[IFELSE]] > +// CHECK: call void [[HVT6]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, > {{[^,]+}}) > +// CHECK-NEXT: br label %[[IFEND]] > +// CHECK: [[IFEND]] > + > +// > +// CHECK: define {{.*}}[[FTEMPLATE]] > +// > +// CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 40 > +// CHECK: br i1 [[IF]], label %[[IFTHEN:[^,]+]], label > %[[IFELSE:[^,]+]] > +// CHECK: [[IFTHEN]] > +// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, > i32 3, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* getelementptr > inbounds ([3 x i[[SZ]]], [3 x i[[SZ]]]* [[SIZET5]], i32 0, i32 0), i32* > getelementptr inbounds ([3 x i32], [3 x i32]* [[MAPT5]], i32 0, i32 0)) > +// CHECK-DAG: [[BPR]] = getelementptr inbounds [3 x i8*], [3 x i8*]* > [[BP:%.+]], i32 0, i32 0 > +// CHECK-DAG: [[PR]] = getelementptr inbounds [3 x i8*], [3 x i8*]* > [[P:%.+]], i32 0, i32 0 > + > +// CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [3 x i8*], [3 x > i8*]* [[BP]], i32 0, i32 0 > +// CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [3 x i8*], [3 x > i8*]* [[P]], i32 0, i32 0 > +// CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to i[[SZ]]* > +// CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to i[[SZ]]* > +// CHECK-DAG: store i[[SZ]] [[VAL0:%.+]], i[[SZ]]* [[CBPADDR0]], > +// CHECK-DAG: store i[[SZ]] [[VAL0]], i[[SZ]]* [[CPADDR0]], > + > +// CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [3 x i8*], [3 x > i8*]* [[BP]], i32 0, i32 1 > +// CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [3 x i8*], [3 x > i8*]* [[P]], i32 0, i32 1 > +// CHECK-DAG: [[CBPADDR1:%.+]] = bitcast i8** [[BPADDR1]] to i[[SZ]]* > +// CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]* > +// CHECK-DAG: store i[[SZ]] [[VAL1:%.+]], i[[SZ]]* [[CBPADDR1]], > +// CHECK-DAG: store i[[SZ]] [[VAL1]], i[[SZ]]* [[CPADDR1]], > + > +// CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [3 x i8*], [3 x > i8*]* [[BP]], i32 0, i32 2 > +// CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [3 x i8*], [3 x > i8*]* [[P]], i32 0, i32 2 > +// CHECK-DAG: [[CBPADDR2:%.+]] = bitcast i8** [[BPADDR2]] to [10 x i32]** > +// CHECK-DAG: [[CPADDR2:%.+]] = bitcast i8** [[PADDR2]] to [10 x i32]** > +// CHECK-DAG: store [10 x i32]* [[VAL2:%.+]], [10 x i32]** [[CBPADDR2]], > +// CHECK-DAG: store [10 x i32]* [[VAL2]], [10 x i32]** [[CPADDR2]], > + > +// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0 > +// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]] > +// CHECK: [[FAIL]] > +// CHECK: call void [[HVT5:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}) > +// CHECK-NEXT: br label %[[END]] > +// CHECK: [[END]] > +// CHECK-NEXT: br label %[[IFEND:.+]] > +// CHECK: [[IFELSE]] > +// CHECK: call void [[HVT:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}) > +// CHECK-NEXT: br label %[[IFEND]] > +// CHECK: [[IFEND]] > + > +// Check that the offloading functions are emitted and that the arguments are > +// correct and loaded correctly for the target regions of the callees of > bar(). > + > +// CHECK: define internal void [[HVT7]] > +// Create local storage for each capture. > +// CHECK: [[LOCAL_THIS:%.+]] = alloca [[S1]]* > +// CHECK: [[LOCAL_B:%.+]] = alloca i[[SZ]] > +// CHECK: [[LOCAL_VLA1:%.+]] = alloca i[[SZ]] > +// CHECK: [[LOCAL_VLA2:%.+]] = alloca i[[SZ]] > +// CHECK: [[LOCAL_C:%.+]] = alloca i16* > +// CHECK-DAG: store [[S1]]* [[ARG_THIS:%.+]], [[S1]]** [[LOCAL_THIS]] > +// CHECK-DAG: store i[[SZ]] [[ARG_B:%.+]], i[[SZ]]* [[LOCAL_B]] > +// CHECK-DAG: store i[[SZ]] [[ARG_VLA1:%.+]], i[[SZ]]* [[LOCAL_VLA1]] > +// CHECK-DAG: store i[[SZ]] [[ARG_VLA2:%.+]], i[[SZ]]* [[LOCAL_VLA2]] > +// CHECK-DAG: store i16* [[ARG_C:%.+]], i16** [[LOCAL_C]] > +// Store captures in the context. > +// CHECK-DAG: [[REF_THIS:%.+]] = load [[S1]]*, [[S1]]** [[LOCAL_THIS]], > +// CHECK-64-DAG:[[CONV_BP:%.+]] = bitcast i[[SZ]]* [[LOCAL_B]] to i32* > +// CHECK-DAG: [[VAL_VLA1:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA1]], > +// CHECK-DAG: [[VAL_VLA2:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA2]], > +// CHECK-DAG: [[REF_C:%.+]] = load i16*, i16** [[LOCAL_C]], > + > + > +// CHECK: define internal void [[HVT6]] > +// Create local storage for each capture. > +// CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]] > +// CHECK: [[LOCAL_AA:%.+]] = alloca i[[SZ]] > +// CHECK: [[LOCAL_AAA:%.+]] = alloca i[[SZ]] > +// CHECK: [[LOCAL_B:%.+]] = alloca [10 x i32]* > +// CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]] > +// CHECK-DAG: store i[[SZ]] [[ARG_AA:%.+]], i[[SZ]]* [[LOCAL_AA]] > +// CHECK-DAG: store i[[SZ]] [[ARG_AAA:%.+]], i[[SZ]]* [[LOCAL_AAA]] > +// CHECK-DAG: store [10 x i32]* [[ARG_B:%.+]], [10 x i32]** [[LOCAL_B]] > +// Store captures in the context. > +// CHECK-64-DAG:[[CONV_AP:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32* > +// CHECK-DAG: [[CONV_AAP:%.+]] = bitcast i[[SZ]]* [[LOCAL_AA]] to i16* > +// CHECK-DAG: [[CONV_AAAP:%.+]] = bitcast i[[SZ]]* [[LOCAL_AAA]] to i8* > +// CHECK-DAG: [[REF_B:%.+]] = load [10 x i32]*, [10 x i32]** [[LOCAL_B]], > + > +// CHECK: define internal void [[HVT5]] > +// Create local storage for each capture. > +// CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]] > +// CHECK: [[LOCAL_AA:%.+]] = alloca i[[SZ]] > +// CHECK: [[LOCAL_B:%.+]] = alloca [10 x i32]* > +// CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]] > +// CHECK-DAG: store i[[SZ]] [[ARG_AA:%.+]], i[[SZ]]* [[LOCAL_AA]] > +// CHECK-DAG: store [10 x i32]* [[ARG_B:%.+]], [10 x i32]** [[LOCAL_B]] > +// Store captures in the context. > +// CHECK-64-DAG:[[CONV_AP:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32* > +// CHECK-DAG: [[CONV_AAP:%.+]] = bitcast i[[SZ]]* [[LOCAL_AA]] to i16* > +// CHECK-DAG: [[REF_B:%.+]] = load [10 x i32]*, [10 x i32]** [[LOCAL_B]], > + > +#endif > > Added: cfe/trunk/test/OpenMP/target_simd_codegen_registration.cpp > URL: > http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/target_simd_codegen_registration.cpp?rev=318536&view=auto > ============================================================================== > --- cfe/trunk/test/OpenMP/target_simd_codegen_registration.cpp (added) > +++ cfe/trunk/test/OpenMP/target_simd_codegen_registration.cpp Fri Nov 17 > 09:57:25 2017 > @@ -0,0 +1,451 @@ > +// Test host codegen. > +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -emit-llvm %s -o - | FileCheck %s > +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -emit-pch -o %t %s > +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s > +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple > i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | > FileCheck %s > +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple > i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s > +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple > i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 > -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s > + > +// Test target simd codegen - host bc file has to be created first. > +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -emit-llvm-bc %s -o %t-ppc-host.bc > +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o > - | FileCheck %s -check-prefix=TCHECK > +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t > %s > +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc > -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -check-prefix=TCHECK > +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple > i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o > %t-x86-host.bc > +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple > i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s > -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck > %s -check-prefix=TCHECK > +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple > i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch > -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s > +// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple > i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 > -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t > -verify %s -emit-llvm -o - | FileCheck %s -check-prefix=TCHECK > + > +// Check that no target code is emmitted if no omptests flag was provided. > +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple > powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s > -check-prefix=CHECK-NTARGET > + > +// expected-no-diagnostics > +#ifndef HEADER > +#define HEADER > + > +// CHECK-DAG: [[SA:%.+]] = type { [4 x i32] } > +// CHECK-DAG: [[SB:%.+]] = type { [8 x i32] } > +// CHECK-DAG: [[SC:%.+]] = type { [16 x i32] } > +// CHECK-DAG: [[SD:%.+]] = type { [32 x i32] } > +// CHECK-DAG: [[SE:%.+]] = type { [64 x i32] } > +// CHECK-DAG: [[ST1:%.+]] = type { [228 x i32] } > +// CHECK-DAG: [[ST2:%.+]] = type { [1128 x i32] } > +// CHECK-DAG: [[ENTTY:%.+]] = type { i8*, i8*, i[[SZ:32|64]], i32, i32 } > +// CHECK-DAG: [[DEVTY:%.+]] = type { i8*, i8*, [[ENTTY]]*, [[ENTTY]]* } > +// CHECK-DAG: [[DSCTY:%.+]] = type { i32, [[DEVTY]]*, [[ENTTY]]*, [[ENTTY]]* > } > + > +// TCHECK: [[ENTTY:%.+]] = type { i8*, i8*, i[[SZ:32|64]], i32, i32 } > + > +// CHECK-DAG: $[[REGFN:\.omp_offloading\..+]] = comdat > + > +// CHECK-DAG: [[A1:@.+]] = internal global [[SA]] > +// CHECK-DAG: [[A2:@.+]] = global [[SA]] > +// CHECK-DAG: [[B1:@.+]] = global [[SB]] > +// CHECK-DAG: [[B2:@.+]] = global [[SB]] > +// CHECK-DAG: [[C1:@.+]] = internal global [[SC]] > +// CHECK-DAG: [[D1:@.+]] = global [[SD]] > +// CHECK-DAG: [[E1:@.+]] = global [[SE]] > +// CHECK-DAG: [[T1:@.+]] = global [[ST1]] > +// CHECK-DAG: [[T2:@.+]] = global [[ST2]] > + > +// CHECK-NTARGET-DAG: [[SA:%.+]] = type { [4 x i32] } > +// CHECK-NTARGET-DAG: [[SB:%.+]] = type { [8 x i32] } > +// CHECK-NTARGET-DAG: [[SC:%.+]] = type { [16 x i32] } > +// CHECK-NTARGET-DAG: [[SD:%.+]] = type { [32 x i32] } > +// CHECK-NTARGET-DAG: [[SE:%.+]] = type { [64 x i32] } > +// CHECK-NTARGET-DAG: [[ST1:%.+]] = type { [228 x i32] } > +// CHECK-NTARGET-DAG: [[ST2:%.+]] = type { [1128 x i32] } > +// CHECK-NTARGET-NOT: type { i8*, i8*, % > +// CHECK-NTARGET-NOT: type { i32, % > + > +// We have 7 target regions > + > +// CHECK-DAG: {{@.+}} = private constant i8 0 > +// TCHECK-NOT: {{@.+}} = private constant i8 0 > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i[[SZ]]] [i[[SZ]] > 4] > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i32] [i32 288] > +// CHECK-DAG: {{@.+}} = private constant i8 0 > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i[[SZ]]] [i[[SZ]] > 4] > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i32] [i32 288] > +// CHECK-DAG: {{@.+}} = private constant i8 0 > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i[[SZ]]] [i[[SZ]] > 4] > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i32] [i32 288] > +// CHECK-DAG: {{@.+}} = private constant i8 0 > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i[[SZ]]] [i[[SZ]] > 4] > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i32] [i32 288] > +// CHECK-DAG: {{@.+}} = private constant i8 0 > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i[[SZ]]] [i[[SZ]] > 4] > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i32] [i32 288] > +// CHECK-DAG: {{@.+}} = private constant i8 0 > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i[[SZ]]] [i[[SZ]] > 4] > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i32] [i32 288] > +// CHECK-DAG: {{@.+}} = private constant i8 0 > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i[[SZ]]] [i[[SZ]] > 4] > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i32] [i32 288] > +// CHECK-DAG: {{@.+}} = private constant i8 0 > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i[[SZ]]] [i[[SZ]] > 4] > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i32] [i32 288] > +// CHECK-DAG: {{@.+}} = private constant i8 0 > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i[[SZ]]] [i[[SZ]] > 4] > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i32] [i32 288] > +// CHECK-DAG: {{@.+}} = private constant i8 0 > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i[[SZ]]] [i[[SZ]] > 4] > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i32] [i32 288] > +// CHECK-DAG: {{@.+}} = private constant i8 0 > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i[[SZ]]] [i[[SZ]] > 4] > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i32] [i32 288] > +// CHECK-DAG: {{@.+}} = private constant i8 0 > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i[[SZ]]] [i[[SZ]] > 4] > +// CHECK-DAG: {{@.+}} = private unnamed_addr constant [1 x i32] [i32 288] > + > +// CHECK-NTARGET-NOT: private constant i8 0 > +// CHECK-NTARGET-NOT: private unnamed_addr constant [1 x i > + > +// CHECK-DAG: [[NAMEPTR1:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME1:__omp_offloading_[0-9a-f]+_[0-9a-f]+__Z.+_l[0-9]+]]\00" > +// CHECK-DAG: [[ENTRY1:@.+]] = constant [[ENTTY]] { i8* @{{.*}}, i8* > getelementptr inbounds ([{{.*}} x i8], [{{.*}} x i8]* [[NAMEPTR1]], i32 0, > i32 0), i[[SZ]] 0, i32 0, i32 0 }, section ".omp_offloading.entries", align 1 > +// CHECK-DAG: [[NAMEPTR2:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME2:.+]]\00" > +// CHECK-DAG: [[ENTRY2:@.+]] = constant [[ENTTY]] { i8* @{{.*}}, i8* > getelementptr inbounds ([{{.*}} x i8], [{{.*}} x i8]* [[NAMEPTR2]], i32 0, > i32 0), i[[SZ]] 0, i32 0, i32 0 }, section ".omp_offloading.entries", align 1 > +// CHECK-DAG: [[NAMEPTR3:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME3:.+]]\00" > +// CHECK-DAG: [[ENTRY3:@.+]] = constant [[ENTTY]] { i8* @{{.*}}, i8* > getelementptr inbounds ([{{.*}} x i8], [{{.*}} x i8]* [[NAMEPTR3]], i32 0, > i32 0), i[[SZ]] 0, i32 0, i32 0 }, section ".omp_offloading.entries", align 1 > +// CHECK-DAG: [[NAMEPTR4:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME4:.+]]\00" > +// CHECK-DAG: [[ENTRY4:@.+]] = constant [[ENTTY]] { i8* @{{.*}}, i8* > getelementptr inbounds ([{{.*}} x i8], [{{.*}} x i8]* [[NAMEPTR4]], i32 0, > i32 0), i[[SZ]] 0, i32 0, i32 0 }, section ".omp_offloading.entries", align 1 > +// CHECK-DAG: [[NAMEPTR5:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME5:.+]]\00" > +// CHECK-DAG: [[ENTRY5:@.+]] = constant [[ENTTY]] { i8* @{{.*}}, i8* > getelementptr inbounds ([{{.*}} x i8], [{{.*}} x i8]* [[NAMEPTR5]], i32 0, > i32 0), i[[SZ]] 0, i32 0, i32 0 }, section ".omp_offloading.entries", align 1 > +// CHECK-DAG: [[NAMEPTR6:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME6:.+]]\00" > +// CHECK-DAG: [[ENTRY6:@.+]] = constant [[ENTTY]] { i8* @{{.*}}, i8* > getelementptr inbounds ([{{.*}} x i8], [{{.*}} x i8]* [[NAMEPTR6]], i32 0, > i32 0), i[[SZ]] 0, i32 0, i32 0 }, section ".omp_offloading.entries", align 1 > +// CHECK-DAG: [[NAMEPTR7:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME7:.+]]\00" > +// CHECK-DAG: [[ENTRY7:@.+]] = constant [[ENTTY]] { i8* @{{.*}}, i8* > getelementptr inbounds ([{{.*}} x i8], [{{.*}} x i8]* [[NAMEPTR7]], i32 0, > i32 0), i[[SZ]] 0, i32 0, i32 0 }, section ".omp_offloading.entries", align 1 > +// CHECK-DAG: [[NAMEPTR8:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME8:.+]]\00" > +// CHECK-DAG: [[ENTRY8:@.+]] = constant [[ENTTY]] { i8* @{{.*}}, i8* > getelementptr inbounds ([{{.*}} x i8], [{{.*}} x i8]* [[NAMEPTR8]], i32 0, > i32 0), i[[SZ]] 0, i32 0, i32 0 }, section ".omp_offloading.entries", align 1 > +// CHECK-DAG: [[NAMEPTR9:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME9:.+]]\00" > +// CHECK-DAG: [[ENTRY9:@.+]] = constant [[ENTTY]] { i8* @{{.*}}, i8* > getelementptr inbounds ([{{.*}} x i8], [{{.*}} x i8]* [[NAMEPTR9]], i32 0, > i32 0), i[[SZ]] 0, i32 0, i32 0 }, section ".omp_offloading.entries", align 1 > +// CHECK-DAG: [[NAMEPTR10:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME10:.+]]\00" > +// CHECK-DAG: [[ENTRY10:@.+]] = constant [[ENTTY]] { i8* @{{.*}}, i8* > getelementptr inbounds ([{{.*}} x i8], [{{.*}} x i8]* [[NAMEPTR10]], i32 0, > i32 0), i[[SZ]] 0, i32 0, i32 0 }, section ".omp_offloading.entries", align 1 > +// CHECK-DAG: [[NAMEPTR11:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME11:.+]]\00" > +// CHECK-DAG: [[ENTRY11:@.+]] = constant [[ENTTY]] { i8* @{{.*}}, i8* > getelementptr inbounds ([{{.*}} x i8], [{{.*}} x i8]* [[NAMEPTR11]], i32 0, > i32 0), i[[SZ]] 0, i32 0, i32 0 }, section ".omp_offloading.entries", align 1 > +// CHECK-DAG: [[NAMEPTR12:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME12:.+]]\00" > +// CHECK-DAG: [[ENTRY12:@.+]] = constant [[ENTTY]] { i8* @{{.*}}, i8* > getelementptr inbounds ([{{.*}} x i8], [{{.*}} x i8]* [[NAMEPTR12]], i32 0, > i32 0), i[[SZ]] 0, i32 0, i32 0 }, section ".omp_offloading.entries", align 1 > + > +// TCHECK-DAG: [[NAMEPTR1:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME1:__omp_offloading_[0-9a-f]+_[0-9a-f]+__Z.+_l[0-9]+]]\00" > +// TCHECK-DAG: [[ENTRY1:@.+]] = constant [[ENTTY]] { i8* bitcast (void > (i[[SZ]])* @{{.*}} to i8*), i8* getelementptr inbounds ([{{.*}} x i8], > [{{.*}} x i8]* [[NAMEPTR1]], i32 0, i32 0), i[[SZ]] 0, i32 0, i32 0 }, > section ".omp_offloading.entries", align 1 > +// TCHECK-DAG: [[NAMEPTR2:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME2:.+]]\00" > +// TCHECK-DAG: [[ENTRY2:@.+]] = constant [[ENTTY]] { i8* bitcast (void > (i[[SZ]])* @{{.*}} to i8*), i8* getelementptr inbounds ([{{.*}} x i8], > [{{.*}} x i8]* [[NAMEPTR2]], i32 0, i32 0), i[[SZ]] 0, i32 0, i32 0 }, > section ".omp_offloading.entries", align 1 > +// TCHECK-DAG: [[NAMEPTR3:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME3:.+]]\00" > +// TCHECK-DAG: [[ENTRY3:@.+]] = constant [[ENTTY]] { i8* bitcast (void > (i[[SZ]])* @{{.*}} to i8*), i8* getelementptr inbounds ([{{.*}} x i8], > [{{.*}} x i8]* [[NAMEPTR3]], i32 0, i32 0), i[[SZ]] 0, i32 0, i32 0 }, > section ".omp_offloading.entries", align 1 > +// TCHECK-DAG: [[NAMEPTR4:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME4:.+]]\00" > +// TCHECK-DAG: [[ENTRY4:@.+]] = constant [[ENTTY]] { i8* bitcast (void > (i[[SZ]])* @{{.*}} to i8*), i8* getelementptr inbounds ([{{.*}} x i8], > [{{.*}} x i8]* [[NAMEPTR4]], i32 0, i32 0), i[[SZ]] 0, i32 0, i32 0 }, > section ".omp_offloading.entries", align 1 > +// TCHECK-DAG: [[NAMEPTR5:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME5:.+]]\00" > +// TCHECK-DAG: [[ENTRY5:@.+]] = constant [[ENTTY]] { i8* bitcast (void > (i[[SZ]])* @{{.*}} to i8*), i8* getelementptr inbounds ([{{.*}} x i8], > [{{.*}} x i8]* [[NAMEPTR5]], i32 0, i32 0), i[[SZ]] 0, i32 0, i32 0 }, > section ".omp_offloading.entries", align 1 > +// TCHECK-DAG: [[NAMEPTR6:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME6:.+]]\00" > +// TCHECK-DAG: [[ENTRY6:@.+]] = constant [[ENTTY]] { i8* bitcast (void > (i[[SZ]])* @{{.*}} to i8*), i8* getelementptr inbounds ([{{.*}} x i8], > [{{.*}} x i8]* [[NAMEPTR6]], i32 0, i32 0), i[[SZ]] 0, i32 0, i32 0 }, > section ".omp_offloading.entries", align 1 > +// TCHECK-DAG: [[NAMEPTR7:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME7:.+]]\00" > +// TCHECK-DAG: [[ENTRY7:@.+]] = constant [[ENTTY]] { i8* bitcast (void > (i[[SZ]])* @{{.*}} to i8*), i8* getelementptr inbounds ([{{.*}} x i8], > [{{.*}} x i8]* [[NAMEPTR7]], i32 0, i32 0), i[[SZ]] 0, i32 0, i32 0 }, > section ".omp_offloading.entries", align 1 > +// TCHECK-DAG: [[NAMEPTR8:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME8:.+]]\00" > +// TCHECK-DAG: [[ENTRY8:@.+]] = constant [[ENTTY]] { i8* bitcast (void > (i[[SZ]])* @{{.*}} to i8*), i8* getelementptr inbounds ([{{.*}} x i8], > [{{.*}} x i8]* [[NAMEPTR8]], i32 0, i32 0), i[[SZ]] 0, i32 0, i32 0 }, > section ".omp_offloading.entries", align 1 > +// TCHECK-DAG: [[NAMEPTR9:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME9:.+]]\00" > +// TCHECK-DAG: [[ENTRY9:@.+]] = constant [[ENTTY]] { i8* bitcast (void > (i[[SZ]])* @{{.*}} to i8*), i8* getelementptr inbounds ([{{.*}} x i8], > [{{.*}} x i8]* [[NAMEPTR9]], i32 0, i32 0), i[[SZ]] 0, i32 0, i32 0 }, > section ".omp_offloading.entries", align 1 > +// TCHECK-DAG: [[NAMEPTR10:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME10:.+]]\00" > +// TCHECK-DAG: [[ENTRY10:@.+]] = constant [[ENTTY]] { i8* bitcast (void > (i[[SZ]])* @{{.*}} to i8*), i8* getelementptr inbounds ([{{.*}} x i8], > [{{.*}} x i8]* [[NAMEPTR10]], i32 0, i32 0), i[[SZ]] 0, i32 0, i32 0 }, > section ".omp_offloading.entries", align 1 > +// TCHECK-DAG: [[NAMEPTR11:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME11:.+]]\00" > +// TCHECK-DAG: [[ENTRY11:@.+]] = constant [[ENTTY]] { i8* bitcast (void > (i[[SZ]])* @{{.*}} to i8*), i8* getelementptr inbounds ([{{.*}} x i8], > [{{.*}} x i8]* [[NAMEPTR11]], i32 0, i32 0), i[[SZ]] 0, i32 0, i32 0 }, > section ".omp_offloading.entries", align 1 > +// TCHECK-DAG: [[NAMEPTR12:@.+]] = internal unnamed_addr constant [{{.*}} x > i8] c"[[NAME12:.+]]\00" > +// TCHECK-DAG: [[ENTRY12:@.+]] = constant [[ENTTY]] { i8* bitcast (void > (i[[SZ]])* @{{.*}} to i8*), i8* getelementptr inbounds ([{{.*}} x i8], > [{{.*}} x i8]* [[NAMEPTR12]], i32 0, i32 0), i[[SZ]] 0, i32 0, i32 0 }, > section ".omp_offloading.entries", align 1 > + > +// CHECK: [[ENTBEGIN:@.+]] = external constant [[ENTTY]] > +// CHECK: [[ENTEND:@.+]] = external constant [[ENTTY]] > +// CHECK: [[DEVBEGIN:@.+]] = external constant i8 > +// CHECK: [[DEVEND:@.+]] = external constant i8 > +// CHECK: [[IMAGES:@.+]] = internal unnamed_addr constant [1 x [[DEVTY]]] > [{{.+}} { i8* [[DEVBEGIN]], i8* [[DEVEND]], [[ENTTY]]* [[ENTBEGIN]], > [[ENTTY]]* [[ENTEND]] }], comdat($[[REGFN]]) > +// CHECK: [[DESC:@.+]] = internal constant [[DSCTY]] { i32 1, [[DEVTY]]* > getelementptr inbounds ([1 x [[DEVTY]]], [1 x [[DEVTY]]]* [[IMAGES]], i32 0, > i32 0), [[ENTTY]]* [[ENTBEGIN]], [[ENTTY]]* [[ENTEND]] }, comdat($[[REGFN]]) > + > +// We have 4 initializers, one for the 500 priority, another one for 501, or > more for the default priority, and the last one for the offloading > registration function. > +// CHECK: @llvm.global_ctors = appending global [4 x { i32, void ()*, i8* }] > [ > +// CHECK-SAME: { i32, void ()*, i8* } { i32 500, void ()* [[P500:@[^,]+]], > i8* null }, > +// CHECK-SAME: { i32, void ()*, i8* } { i32 501, void ()* [[P501:@[^,]+]], > i8* null }, > +// CHECK-SAME: { i32, void ()*, i8* } { i32 65535, void ()* [[PMAX:@[^,]+]], > i8* null }, > +// CHECK-SAME: { i32, void ()*, i8* } { i32 0, void ()* bitcast (void (i8*)* > @[[REGFN]] to void ()*), i8* bitcast (void (i8*)* @[[REGFN]] to i8*) }] > + > +// CHECK-NTARGET: @llvm.global_ctors = appending global [3 x { i32, void > ()*, i8* }] [ > + > +extern int *R; > + > +struct SA { > + int arr[4]; > + void foo() { > + int a = *R; > + a += 1; > + *R = a; > + } > + SA() { > + int a = *R; > + a += 2; > + *R = a; > + } > + ~SA() { > + int a = *R; > + a += 3; > + *R = a; > + } > +}; > + > +struct SB { > + int arr[8]; > + void foo() { > + int a = *R; > + #pragma omp target simd > + for (int i = 0; i < 10; ++i) > + a += 4; > + *R = a; > + } > + SB() { > + int a = *R; > + a += 5; > + *R = a; > + } > + ~SB() { > + int a = *R; > + a += 6; > + *R = a; > + } > +}; > + > +struct SC { > + int arr[16]; > + void foo() { > + int a = *R; > + a += 7; > + *R = a; > + } > + SC() { > + int a = *R; > + #pragma omp target simd > + for (int i = 0; i < 10; ++i) > + a += 8; > + *R = a; > + } > + ~SC() { > + int a = *R; > + a += 9; > + *R = a; > + } > +}; > + > +struct SD { > + int arr[32]; > + void foo() { > + int a = *R; > + a += 10; > + *R = a; > + } > + SD() { > + int a = *R; > + a += 11; > + *R = a; > + } > + ~SD() { > + int a = *R; > + #pragma omp target simd > + for (int i = 0; i < 10; ++i) > + a += 12; > + *R = a; > + } > +}; > + > +struct SE { > + int arr[64]; > + void foo() { > + int a = *R; > + #pragma omp target simd if(target: 0) > + for (int i = 0; i < 10; ++i) > + a += 13; > + *R = a; > + } > + SE() { > + int a = *R; > + #pragma omp target simd > + for (int i = 0; i < 10; ++i) > + a += 14; > + *R = a; > + } > + ~SE() { > + int a = *R; > + #pragma omp target simd > + for (int i = 0; i < 10; ++i) > + a += 15; > + *R = a; > + } > +}; > + > +template <int x> > +struct ST { > + int arr[128 + x]; > + void foo() { > + int a = *R; > + #pragma omp target simd > + for (int i = 0; i < 10; ++i) > + a += 16 + x; > + *R = a; > + } > + ST() { > + int a = *R; > + #pragma omp target simd > + for (int i = 0; i < 10; ++i) > + a += 17 + x; > + *R = a; > + } > + ~ST() { > + int a = *R; > + #pragma omp target simd > + for (int i = 0; i < 10; ++i) > + a += 18 + x; > + *R = a; > + } > +}; > + > +// We have to make sure we us all the target regions: > +//CHECK-DAG: define internal void @[[NAME1]]( > +//CHECK-DAG: call void @[[NAME1]]( > +//CHECK-DAG: define internal void @[[NAME2]]( > +//CHECK-DAG: call void @[[NAME2]]( > +//CHECK-DAG: define internal void @[[NAME3]]( > +//CHECK-DAG: call void @[[NAME3]]( > +//CHECK-DAG: define internal void @[[NAME4]]( > +//CHECK-DAG: call void @[[NAME4]]( > +//CHECK-DAG: define internal void @[[NAME5]]( > +//CHECK-DAG: call void @[[NAME5]]( > +//CHECK-DAG: define internal void @[[NAME6]]( > +//CHECK-DAG: call void @[[NAME6]]( > +//CHECK-DAG: define internal void @[[NAME7]]( > +//CHECK-DAG: call void @[[NAME7]]( > +//CHECK-DAG: define internal void @[[NAME8]]( > +//CHECK-DAG: call void @[[NAME8]]( > +//CHECK-DAG: define internal void @[[NAME9]]( > +//CHECK-DAG: call void @[[NAME9]]( > +//CHECK-DAG: define internal void @[[NAME10]]( > +//CHECK-DAG: call void @[[NAME10]]( > +//CHECK-DAG: define internal void @[[NAME11]]( > +//CHECK-DAG: call void @[[NAME11]]( > +//CHECK-DAG: define internal void @[[NAME12]]( > +//CHECK-DAG: call void @[[NAME12]]( > + > +//TCHECK-DAG: define void @[[NAME1]]( > +//TCHECK-DAG: define void @[[NAME2]]( > +//TCHECK-DAG: define void @[[NAME3]]( > +//TCHECK-DAG: define void @[[NAME4]]( > +//TCHECK-DAG: define void @[[NAME5]]( > +//TCHECK-DAG: define void @[[NAME6]]( > +//TCHECK-DAG: define void @[[NAME7]]( > +//TCHECK-DAG: define void @[[NAME8]]( > +//TCHECK-DAG: define void @[[NAME9]]( > +//TCHECK-DAG: define void @[[NAME10]]( > +//TCHECK-DAG: define void @[[NAME11]]( > +//TCHECK-DAG: define void @[[NAME12]]( > + > +// CHECK-NTARGET-NOT: __tgt_target > +// CHECK-NTARGET-NOT: __tgt_register_lib > +// CHECK-NTARGET-NOT: __tgt_unregister_lib > + > +// TCHECK-NOT: __tgt_target > +// TCHECK-NOT: __tgt_register_lib > +// TCHECK-NOT: __tgt_unregister_lib > + > +// We have 2 initializers with priority 500 > +//CHECK: define internal void [[P500]]( > +//CHECK: call void @{{.+}}() > +//CHECK: call void @{{.+}}() > +//CHECK-NOT: call void @{{.+}}() > +//CHECK: ret void > + > +// We have 1 initializers with priority 501 > +//CHECK: define internal void [[P501]]( > +//CHECK: call void @{{.+}}() > +//CHECK-NOT: call void @{{.+}}() > +//CHECK: ret void > + > +// We have 6 initializers with default priority > +//CHECK: define internal void [[PMAX]]( > +//CHECK: call void @{{.+}}() > +//CHECK: call void @{{.+}}() > +//CHECK: call void @{{.+}}() > +//CHECK: call void @{{.+}}() > +//CHECK: call void @{{.+}}() > +//CHECK: call void @{{.+}}() > +//CHECK-NOT: call void @{{.+}}() > +//CHECK: ret void > + > +// Check registration and unregistration > + > +//CHECK: define internal void @[[UNREGFN:.+]](i8*) > +//CHECK-SAME: comdat($[[REGFN]]) { > +//CHECK: call i32 @__tgt_unregister_lib([[DSCTY]]* [[DESC]]) > +//CHECK: ret void > +//CHECK: declare i32 @__tgt_unregister_lib([[DSCTY]]*) > + > +//CHECK: define linkonce hidden void @[[REGFN]](i8*) > +//CHECK-SAME: comdat { > +//CHECK: call i32 @__tgt_register_lib([[DSCTY]]* [[DESC]]) > +//CHECK: call i32 @__cxa_atexit(void (i8*)* @[[UNREGFN]], i8* bitcast > ([[DSCTY]]* [[DESC]] to i8*), > +//CHECK: ret void > +//CHECK: declare i32 @__tgt_register_lib([[DSCTY]]*) > + > +static __attribute__((init_priority(500))) SA a1; > +SA a2; > +SB __attribute__((init_priority(500))) b1; > +SB __attribute__((init_priority(501))) b2; > +static SC c1; > +SD d1; > +SE e1; > +ST<100> t1; > +ST<1000> t2; > + > + > +int bar(int a){ > + int r = a; > + > + a1.foo(); > + a2.foo(); > + b1.foo(); > + b2.foo(); > + c1.foo(); > + d1.foo(); > + e1.foo(); > + t1.foo(); > + t2.foo(); > + > + #pragma omp target simd > + for (int i = 0; i < 10; ++i) > + ++r; > + > + return r + *R; > +} > + > +// Check metadata is properly generated: > +// CHECK: !omp_offload.info = !{!{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, > !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, > !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}} > +// CHECK-DAG: = !{i32 0, i32 [[DEVID:-?[0-9]+]], i32 [[FILEID:-?[0-9]+]], > !"_ZN2SB3fooEv", i32 195, i32 {{[0-9]+}}} > +// CHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], !"_ZN2SDD1Ev", i32 > 247, i32 {{[0-9]+}}} > +// CHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], !"_ZN2SEC1Ev", i32 > 265, i32 {{[0-9]+}}} > +// CHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], !"_ZN2SED1Ev", i32 > 272, i32 {{[0-9]+}}} > +// CHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], > !"_ZN2STILi1000EE3fooEv", i32 284, i32 {{[0-9]+}}} > +// CHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], > !"_ZN2STILi100EEC1Ev", i32 291, i32 {{[0-9]+}}} > +// CHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], !"_Z3bari", i32 415, > i32 {{[0-9]+}}} > +// CHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], > !"_ZN2STILi100EED1Ev", i32 298, i32 {{[0-9]+}}} > +// CHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], > !"_ZN2STILi1000EEC1Ev", i32 291, i32 {{[0-9]+}}} > +// CHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], > !"_ZN2STILi1000EED1Ev", i32 298, i32 {{[0-9]+}}} > +// CHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], > !"_ZN2STILi100EE3fooEv", i32 284, i32 {{[0-9]+}}} > +// CHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], !"_ZN2SCC1Ev", i32 > 221, i32 {{[0-9]+}}} > + > +// TCHECK: !omp_offload.info = !{!{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, > !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}, > !{{[0-9]+}}, !{{[0-9]+}}, !{{[0-9]+}}} > +// TCHECK-DAG: = !{i32 0, i32 [[DEVID:-?[0-9]+]], i32 [[FILEID:-?[0-9]+]], > !"_ZN2SB3fooEv", i32 195, i32 {{[0-9]+}}} > +// TCHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], !"_ZN2SDD1Ev", i32 > 247, i32 {{[0-9]+}}} > +// TCHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], !"_ZN2SEC1Ev", i32 > 265, i32 {{[0-9]+}}} > +// TCHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], !"_ZN2SED1Ev", i32 > 272, i32 {{[0-9]+}}} > +// TCHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], > !"_ZN2STILi1000EE3fooEv", i32 284, i32 {{[0-9]+}}} > +// TCHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], > !"_ZN2STILi100EEC1Ev", i32 291, i32 {{[0-9]+}}} > +// TCHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], !"_Z3bari", i32 > 415, i32 {{[0-9]+}}} > +// TCHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], > !"_ZN2STILi100EED1Ev", i32 298, i32 {{[0-9]+}}} > +// TCHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], > !"_ZN2STILi1000EEC1Ev", i32 291, i32 {{[0-9]+}}} > +// TCHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], > !"_ZN2STILi1000EED1Ev", i32 298, i32 {{[0-9]+}}} > +// TCHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], > !"_ZN2STILi100EE3fooEv", i32 284, i32 {{[0-9]+}}} > +// TCHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], !"_ZN2SCC1Ev", i32 > 221, i32 {{[0-9]+}}} > + > +#endif > > Added: cfe/trunk/test/OpenMP/target_simd_codegen_registration_naming.cpp > URL: > http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/target_simd_codegen_registration_naming.cpp?rev=318536&view=auto > ============================================================================== > --- cfe/trunk/test/OpenMP/target_simd_codegen_registration_naming.cpp (added) > +++ cfe/trunk/test/OpenMP/target_simd_codegen_registration_naming.cpp Fri Nov > 17 09:57:25 2017 > @@ -0,0 +1,68 @@ > +// Test host codegen. > +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -emit-llvm %s -o - | FileCheck %s > +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -emit-pch -o %t %s > +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s > +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple > i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | > FileCheck %s > +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown > -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s > +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown > -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - > | FileCheck %s > + > +// Test target simd codegen - host bc file has to be created first. > +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -emit-llvm-bc %s -o %t-ppc-host.bc > +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o > - | FileCheck %s -check-prefix=TCHECK > +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -std=c++11 -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t > %s > +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple > powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu > -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t > -verify %s -emit-llvm -o - | FileCheck %s -check-prefix=TCHECK > +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple > i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o > %t-x86-host.bc > +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple > i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s > -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck > %s -check-prefix=TCHECK > +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown > -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device > -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s > +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown > -fopenmp-targets=i386-pc-linux-gnu -fopenmp-is-device > -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s > -emit-llvm -o - | FileCheck %s -check-prefix=TCHECK > + > +// expected-no-diagnostics > +#ifndef HEADER > +#define HEADER > + > +// CHECK: [[CA:%.+]] = type { i32* } > + > +// CHECK: define {{.*}}i32 @[[NNAME:.+]](i32 {{.*}}%{{.+}}) > +int nested(int a){ > + // CHECK: call void > @__omp_offloading_[[FILEID:[0-9a-f]+_[0-9a-f]+]]_[[NNAME]]_l[[T1L:[0-9]+]]( > + #pragma omp target simd > + for (int i = 0; i < 10; ++i) > + ++a; > + > + // CHECK: call void @"[[LNAME:.+]]"([[CA]]* > + auto F = [&](){ > + #pragma omp parallel > + { > + #pragma omp target simd > + for (int i = 0; i < 10; ++i) > + ++a; > + } > + }; > + > + F(); > + > + return a; > +} > + > +// CHECK: define {{.*}}void @__omp_offloading_[[FILEID]]_[[NNAME]]_l[[T1L]]( > +// TCHECK: define {{.*}}void > @__omp_offloading_[[FILEID:[0-9a-f]+_[0-9a-f]+]]_[[NNAME:.+]]_l[[T1L:[0-9]+]]( > + > +// CHECK: define {{.*}}void @"[[LNAME]]"( > +// CHECK: call void {{.*}}@__kmpc_fork_call{{.+}}[[PNAME:@.+]] to > + > +// CHECK: define {{.*}}void [[PNAME]]( > +// CHECK: call void @__omp_offloading_[[FILEID]]_[[NNAME]]_l[[T2L:[0-9]+]]( > + > +// CHECK: define {{.*}}void @__omp_offloading_[[FILEID]]_[[NNAME]]_l[[T2L]]( > +// TCHECK: define {{.*}}void > @__omp_offloading_[[FILEID]]_[[NNAME:.+]]_l[[T2L:[0-9]+]]( > + > + > +// Check metadata is properly generated: > +// CHECK: !omp_offload.info = !{!{{[0-9]+}}, !{{[0-9]+}}} > +// CHECK-DAG: = !{i32 0, i32 {{-?[0-9]+}}, i32 {{-?[0-9]+}}, !"[[NNAME]]", > i32 [[T1L]], i32 {{[0-9]+}}} > +// CHECK-DAG: = !{i32 0, i32 {{-?[0-9]+}}, i32 {{-?[0-9]+}}, !"[[NNAME]]", > i32 [[T2L]], i32 {{[0-9]+}}} > + > +// TCHECK: !omp_offload.info = !{!{{[0-9]+}}, !{{[0-9]+}}} > +// TCHECK-DAG: = !{i32 0, i32 {{-?[0-9]+}}, i32 {{-?[0-9]+}}, !"[[NNAME]]", > i32 [[T1L]], i32 {{[0-9]+}}} > +// TCHECK-DAG: = !{i32 0, i32 {{-?[0-9]+}}, i32 {{-?[0-9]+}}, !"[[NNAME]]", > i32 [[T2L]], i32 {{[0-9]+}}} > +#endif > > > _______________________________________________ > cfe-commits mailing list > cfe-commits@lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits