https://github.com/osa1 updated https://github.com/llvm/llvm-project/pull/225339
From fec5ada488cefb130872a56aa651d3b8297d5e30 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <[email protected]> Date: Mon, 21 Sep 2026 15:24:28 +0100 Subject: [PATCH] [AArch64] Upgrade `llvm.aarch64.neon.{s,u}{min,max}...` vector intrinsics --- clang/test/CodeGen/AArch64/neon/intrinsics.c | 48 +-- llvm/lib/IR/AutoUpgrade.cpp | 16 + .../Bitcode/aarch64-neon-minmax-upgrade.ll | 58 ++++ llvm/test/CodeGen/AArch64/abd-combine.ll | 7 +- .../MemorySanitizer/AArch64/arm64-vmax.ll | 312 +++++++++--------- 5 files changed, 257 insertions(+), 184 deletions(-) create mode 100644 llvm/test/Bitcode/aarch64-neon-minmax-upgrade.ll diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index 7175c616cf484..a804f0bc218ad 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -2321,7 +2321,7 @@ int8x8_t test_vmax_s8(int8x8_t v1, int8x8_t v2) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.smax" %{{.*}}, %{{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i> // LLVM-SAME: <8 x i8> {{.*}} [[V1:%.*]], <8 x i8> noundef [[V2:%.*]]) {{.*}} { - // LLVM: [[VMAX_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.smax.v8i8(<8 x i8> [[V1]], <8 x i8> [[V2]]) + // LLVM: [[VMAX_V_I:%.*]] = call <8 x i8> @llvm.smax.v8i8(<8 x i8> [[V1]], <8 x i8> [[V2]]) // LLVM: ret <8 x i8> [[VMAX_V_I]] return vmax_s8(v1, v2); } @@ -2336,7 +2336,7 @@ int16x4_t test_vmax_s16(int16x4_t v1, int16x4_t v2) { // LLVM: [[TMP1:%.*]] = bitcast <4 x i16> [[V2]] to <8 x i8> // LLVM: [[VMAX_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> // LLVM: [[VMAX_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> - // LLVM: [[VMAX_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.smax.v4i16(<4 x i16> [[VMAX_V_I]], <4 x i16> [[VMAX_V1_I]]) + // LLVM: [[VMAX_V2_I:%.*]] = call <4 x i16> @llvm.smax.v4i16(<4 x i16> [[VMAX_V_I]], <4 x i16> [[VMAX_V1_I]]) // LLVM: ret <4 x i16> [[VMAX_V2_I]] return vmax_s16(v1, v2); } @@ -2351,7 +2351,7 @@ int32x2_t test_vmax_s32(int32x2_t v1, int32x2_t v2) { // LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[V2]] to <8 x i8> // LLVM: [[VMAX_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> // LLVM: [[VMAX_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> - // LLVM: [[VMAX_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.smax.v2i32(<2 x i32> [[VMAX_V_I]], <2 x i32> [[VMAX_V1_I]]) + // LLVM: [[VMAX_V2_I:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[VMAX_V_I]], <2 x i32> [[VMAX_V1_I]]) // LLVM: ret <2 x i32> [[VMAX_V2_I]] return vmax_s32(v1, v2); } @@ -2362,7 +2362,7 @@ uint8x8_t test_vmax_u8(uint8x8_t v1, uint8x8_t v2) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.umax" %{{.*}}, %{{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>) -> !cir.vector<8 x !u8i> // LLVM-SAME: <8 x i8> {{.*}} [[V1:%.*]], <8 x i8> noundef [[V2:%.*]]) {{.*}} { - // LLVM: [[VMAX_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.umax.v8i8(<8 x i8> [[V1]], <8 x i8> [[V2]]) + // LLVM: [[VMAX_V_I:%.*]] = call <8 x i8> @llvm.umax.v8i8(<8 x i8> [[V1]], <8 x i8> [[V2]]) // LLVM: ret <8 x i8> [[VMAX_V_I]] return vmax_u8(v1, v2); } @@ -2377,7 +2377,7 @@ uint16x4_t test_vmax_u16(uint16x4_t v1, uint16x4_t v2) { // LLVM: [[TMP1:%.*]] = bitcast <4 x i16> [[V2]] to <8 x i8> // LLVM: [[VMAX_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> // LLVM: [[VMAX_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> - // LLVM: [[VMAX_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.umax.v4i16(<4 x i16> [[VMAX_V_I]], <4 x i16> [[VMAX_V1_I]]) + // LLVM: [[VMAX_V2_I:%.*]] = call <4 x i16> @llvm.umax.v4i16(<4 x i16> [[VMAX_V_I]], <4 x i16> [[VMAX_V1_I]]) // LLVM: ret <4 x i16> [[VMAX_V2_I]] return vmax_u16(v1, v2); } @@ -2392,7 +2392,7 @@ uint32x2_t test_vmax_u32(uint32x2_t v1, uint32x2_t v2) { // LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[V2]] to <8 x i8> // LLVM: [[VMAX_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> // LLVM: [[VMAX_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> - // LLVM: [[VMAX_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.umax.v2i32(<2 x i32> [[VMAX_V_I]], <2 x i32> [[VMAX_V1_I]]) + // LLVM: [[VMAX_V2_I:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[VMAX_V_I]], <2 x i32> [[VMAX_V1_I]]) // LLVM: ret <2 x i32> [[VMAX_V2_I]] return vmax_u32(v1, v2); } @@ -2403,7 +2403,7 @@ int8x16_t test_vmaxq_s8(int8x16_t v1, int8x16_t v2) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.smax" %{{.*}}, %{{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>) -> !cir.vector<16 x !s8i> // LLVM-SAME: <16 x i8> {{.*}} [[V1:%.*]], <16 x i8> noundef [[V2:%.*]]) {{.*}} { - // LLVM: [[VMAXQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.smax.v16i8(<16 x i8> [[V1]], <16 x i8> [[V2]]) + // LLVM: [[VMAXQ_V_I:%.*]] = call <16 x i8> @llvm.smax.v16i8(<16 x i8> [[V1]], <16 x i8> [[V2]]) // LLVM: ret <16 x i8> [[VMAXQ_V_I]] return vmaxq_s8(v1, v2); } @@ -2418,7 +2418,7 @@ int16x8_t test_vmaxq_s16(int16x8_t v1, int16x8_t v2) { // LLVM: [[TMP1:%.*]] = bitcast <8 x i16> [[V2]] to <16 x i8> // LLVM: [[VMAXQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> // LLVM: [[VMAXQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> - // LLVM: [[VMAXQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.smax.v8i16(<8 x i16> [[VMAXQ_V_I]], <8 x i16> [[VMAXQ_V1_I]]) + // LLVM: [[VMAXQ_V2_I:%.*]] = call <8 x i16> @llvm.smax.v8i16(<8 x i16> [[VMAXQ_V_I]], <8 x i16> [[VMAXQ_V1_I]]) // LLVM: ret <8 x i16> [[VMAXQ_V2_I]] return vmaxq_s16(v1, v2); } @@ -2433,7 +2433,7 @@ int32x4_t test_vmaxq_s32(int32x4_t v1, int32x4_t v2) { // LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[V2]] to <16 x i8> // LLVM: [[VMAXQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> // LLVM: [[VMAXQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> - // LLVM: [[VMAXQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> [[VMAXQ_V_I]], <4 x i32> [[VMAXQ_V1_I]]) + // LLVM: [[VMAXQ_V2_I:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[VMAXQ_V_I]], <4 x i32> [[VMAXQ_V1_I]]) // LLVM: ret <4 x i32> [[VMAXQ_V2_I]] return vmaxq_s32(v1, v2); } @@ -2444,7 +2444,7 @@ uint8x16_t test_vmaxq_u8(uint8x16_t v1, uint8x16_t v2) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.umax" %{{.*}}, %{{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>) -> !cir.vector<16 x !u8i> // LLVM-SAME: <16 x i8> {{.*}} [[V1:%.*]], <16 x i8> noundef [[V2:%.*]]) {{.*}} { - // LLVM: [[VMAXQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.umax.v16i8(<16 x i8> [[V1]], <16 x i8> [[V2]]) + // LLVM: [[VMAXQ_V_I:%.*]] = call <16 x i8> @llvm.umax.v16i8(<16 x i8> [[V1]], <16 x i8> [[V2]]) // LLVM: ret <16 x i8> [[VMAXQ_V_I]] return vmaxq_u8(v1, v2); } @@ -2459,7 +2459,7 @@ uint16x8_t test_vmaxq_u16(uint16x8_t v1, uint16x8_t v2) { // LLVM: [[TMP1:%.*]] = bitcast <8 x i16> [[V2]] to <16 x i8> // LLVM: [[VMAXQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> // LLVM: [[VMAXQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> - // LLVM: [[VMAXQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.umax.v8i16(<8 x i16> [[VMAXQ_V_I]], <8 x i16> [[VMAXQ_V1_I]]) + // LLVM: [[VMAXQ_V2_I:%.*]] = call <8 x i16> @llvm.umax.v8i16(<8 x i16> [[VMAXQ_V_I]], <8 x i16> [[VMAXQ_V1_I]]) // LLVM: ret <8 x i16> [[VMAXQ_V2_I]] return vmaxq_u16(v1, v2); } @@ -2474,7 +2474,7 @@ uint32x4_t test_vmaxq_u32(uint32x4_t v1, uint32x4_t v2) { // LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[V2]] to <16 x i8> // LLVM: [[VMAXQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> // LLVM: [[VMAXQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> - // LLVM: [[VMAXQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32> [[VMAXQ_V_I]], <4 x i32> [[VMAXQ_V1_I]]) + // LLVM: [[VMAXQ_V2_I:%.*]] = call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[VMAXQ_V_I]], <4 x i32> [[VMAXQ_V1_I]]) // LLVM: ret <4 x i32> [[VMAXQ_V2_I]] return vmaxq_u32(v1, v2); } @@ -2920,7 +2920,7 @@ int8x8_t test_vmin_s8(int8x8_t v1, int8x8_t v2) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.smin" %{{.*}}, %{{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i> // LLVM-SAME: <8 x i8> {{.*}} [[V1:%.*]], <8 x i8> noundef [[V2:%.*]]) {{.*}} { - // LLVM: [[VMIN_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.smin.v8i8(<8 x i8> [[V1]], <8 x i8> [[V2]]) + // LLVM: [[VMIN_V_I:%.*]] = call <8 x i8> @llvm.smin.v8i8(<8 x i8> [[V1]], <8 x i8> [[V2]]) // LLVM: ret <8 x i8> [[VMIN_V_I]] return vmin_s8(v1, v2); } @@ -2935,7 +2935,7 @@ int16x4_t test_vmin_s16(int16x4_t v1, int16x4_t v2) { // LLVM: [[TMP1:%.*]] = bitcast <4 x i16> [[V2]] to <8 x i8> // LLVM: [[VMIN_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> // LLVM: [[VMIN_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> - // LLVM: [[VMIN_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.smin.v4i16(<4 x i16> [[VMIN_V_I]], <4 x i16> [[VMIN_V1_I]]) + // LLVM: [[VMIN_V2_I:%.*]] = call <4 x i16> @llvm.smin.v4i16(<4 x i16> [[VMIN_V_I]], <4 x i16> [[VMIN_V1_I]]) // LLVM: ret <4 x i16> [[VMIN_V2_I]] return vmin_s16(v1, v2); } @@ -2950,7 +2950,7 @@ int32x2_t test_vmin_s32(int32x2_t v1, int32x2_t v2) { // LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[V2]] to <8 x i8> // LLVM: [[VMIN_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> // LLVM: [[VMIN_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> - // LLVM: [[VMIN_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.smin.v2i32(<2 x i32> [[VMIN_V_I]], <2 x i32> [[VMIN_V1_I]]) + // LLVM: [[VMIN_V2_I:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[VMIN_V_I]], <2 x i32> [[VMIN_V1_I]]) // LLVM: ret <2 x i32> [[VMIN_V2_I]] return vmin_s32(v1, v2); } @@ -2961,7 +2961,7 @@ uint8x8_t test_vmin_u8(uint8x8_t v1, uint8x8_t v2) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.umin" %{{.*}}, %{{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>) -> !cir.vector<8 x !u8i> // LLVM-SAME: <8 x i8> {{.*}} [[V1:%.*]], <8 x i8> noundef [[V2:%.*]]) {{.*}} { - // LLVM: [[VMIN_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.umin.v8i8(<8 x i8> [[V1]], <8 x i8> [[V2]]) + // LLVM: [[VMIN_V_I:%.*]] = call <8 x i8> @llvm.umin.v8i8(<8 x i8> [[V1]], <8 x i8> [[V2]]) // LLVM: ret <8 x i8> [[VMIN_V_I]] return vmin_u8(v1, v2); } @@ -2976,7 +2976,7 @@ uint16x4_t test_vmin_u16(uint16x4_t v1, uint16x4_t v2) { // LLVM: [[TMP1:%.*]] = bitcast <4 x i16> [[V2]] to <8 x i8> // LLVM: [[VMIN_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> // LLVM: [[VMIN_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> - // LLVM: [[VMIN_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.umin.v4i16(<4 x i16> [[VMIN_V_I]], <4 x i16> [[VMIN_V1_I]]) + // LLVM: [[VMIN_V2_I:%.*]] = call <4 x i16> @llvm.umin.v4i16(<4 x i16> [[VMIN_V_I]], <4 x i16> [[VMIN_V1_I]]) // LLVM: ret <4 x i16> [[VMIN_V2_I]] return vmin_u16(v1, v2); } @@ -2991,7 +2991,7 @@ uint32x2_t test_vmin_u32(uint32x2_t v1, uint32x2_t v2) { // LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[V2]] to <8 x i8> // LLVM: [[VMIN_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> // LLVM: [[VMIN_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> - // LLVM: [[VMIN_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32> [[VMIN_V_I]], <2 x i32> [[VMIN_V1_I]]) + // LLVM: [[VMIN_V2_I:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[VMIN_V_I]], <2 x i32> [[VMIN_V1_I]]) // LLVM: ret <2 x i32> [[VMIN_V2_I]] return vmin_u32(v1, v2); } @@ -3002,7 +3002,7 @@ int8x16_t test_vminq_s8(int8x16_t v1, int8x16_t v2) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.smin" %{{.*}}, %{{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>) -> !cir.vector<16 x !s8i> // LLVM-SAME: <16 x i8> {{.*}} [[V1:%.*]], <16 x i8> noundef [[V2:%.*]]) {{.*}} { - // LLVM: [[VMINQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.smin.v16i8(<16 x i8> [[V1]], <16 x i8> [[V2]]) + // LLVM: [[VMINQ_V_I:%.*]] = call <16 x i8> @llvm.smin.v16i8(<16 x i8> [[V1]], <16 x i8> [[V2]]) // LLVM: ret <16 x i8> [[VMINQ_V_I]] return vminq_s8(v1, v2); } @@ -3017,7 +3017,7 @@ int16x8_t test_vminq_s16(int16x8_t v1, int16x8_t v2) { // LLVM: [[TMP1:%.*]] = bitcast <8 x i16> [[V2]] to <16 x i8> // LLVM: [[VMINQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> // LLVM: [[VMINQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> - // LLVM: [[VMINQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.smin.v8i16(<8 x i16> [[VMINQ_V_I]], <8 x i16> [[VMINQ_V1_I]]) + // LLVM: [[VMINQ_V2_I:%.*]] = call <8 x i16> @llvm.smin.v8i16(<8 x i16> [[VMINQ_V_I]], <8 x i16> [[VMINQ_V1_I]]) // LLVM: ret <8 x i16> [[VMINQ_V2_I]] return vminq_s16(v1, v2); } @@ -3032,7 +3032,7 @@ int32x4_t test_vminq_s32(int32x4_t v1, int32x4_t v2) { // LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[V2]] to <16 x i8> // LLVM: [[VMINQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> // LLVM: [[VMINQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> - // LLVM: [[VMINQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32> [[VMINQ_V_I]], <4 x i32> [[VMINQ_V1_I]]) + // LLVM: [[VMINQ_V2_I:%.*]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[VMINQ_V_I]], <4 x i32> [[VMINQ_V1_I]]) // LLVM: ret <4 x i32> [[VMINQ_V2_I]] return vminq_s32(v1, v2); } @@ -3043,7 +3043,7 @@ uint8x16_t test_vminq_u8(uint8x16_t v1, uint8x16_t v2) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.umin" %{{.*}}, %{{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>) -> !cir.vector<16 x !u8i> // LLVM-SAME: <16 x i8> {{.*}} [[V1:%.*]], <16 x i8> noundef [[V2:%.*]]) {{.*}} { - // LLVM: [[VMINQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.umin.v16i8(<16 x i8> [[V1]], <16 x i8> [[V2]]) + // LLVM: [[VMINQ_V_I:%.*]] = call <16 x i8> @llvm.umin.v16i8(<16 x i8> [[V1]], <16 x i8> [[V2]]) // LLVM: ret <16 x i8> [[VMINQ_V_I]] return vminq_u8(v1, v2); } @@ -3058,7 +3058,7 @@ uint16x8_t test_vminq_u16(uint16x8_t v1, uint16x8_t v2) { // LLVM: [[TMP1:%.*]] = bitcast <8 x i16> [[V2]] to <16 x i8> // LLVM: [[VMINQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> // LLVM: [[VMINQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> - // LLVM: [[VMINQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.umin.v8i16(<8 x i16> [[VMINQ_V_I]], <8 x i16> [[VMINQ_V1_I]]) + // LLVM: [[VMINQ_V2_I:%.*]] = call <8 x i16> @llvm.umin.v8i16(<8 x i16> [[VMINQ_V_I]], <8 x i16> [[VMINQ_V1_I]]) // LLVM: ret <8 x i16> [[VMINQ_V2_I]] return vminq_u16(v1, v2); @@ -3074,7 +3074,7 @@ uint32x4_t test_vminq_u32(uint32x4_t v1, uint32x4_t v2) { // LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[V2]] to <16 x i8> // LLVM: [[VMINQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> // LLVM: [[VMINQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> - // LLVM: [[VMINQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32> [[VMINQ_V_I]], <4 x i32> [[VMINQ_V1_I]]) + // LLVM: [[VMINQ_V2_I:%.*]] = call <4 x i32> @llvm.umin.v4i32(<4 x i32> [[VMINQ_V_I]], <4 x i32> [[VMINQ_V1_I]]) // LLVM: ret <4 x i32> [[VMINQ_V2_I]] return vminq_u32(v1, v2); } diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp index 16ff20a3d9946..ead8897c19097 100644 --- a/llvm/lib/IR/AutoUpgrade.cpp +++ b/llvm/lib/IR/AutoUpgrade.cpp @@ -988,6 +988,22 @@ static bool upgradeArmOrAarch64IntrinsicFunction(bool IsArm, Function *F, return true; } + // Check for the trailing '.' to avoid matching sminv, sminp, etc. + if (Name.starts_with("smax.") || Name.starts_with("smin.") || + Name.starts_with("umax.") || Name.starts_with("umin.")) { + if (F->arg_size() != 2 || !F->getReturnType()->isIntOrIntVectorTy()) + return false; // Invalid IR. + Intrinsic::ID ID = StringSwitch<Intrinsic::ID>(Name.take_front(4)) + .Case("smax", Intrinsic::smax) + .Case("smin", Intrinsic::smin) + .Case("umax", Intrinsic::umax) + .Case("umin", Intrinsic::umin) + .Default(Intrinsic::not_intrinsic); + NewFn = Intrinsic::getOrInsertDeclaration(F->getParent(), ID, + F->getReturnType()); + return true; + } + if (Name.starts_with("addp")) { // 'aarch64.neon.addp*'. if (F->arg_size() != 2) diff --git a/llvm/test/Bitcode/aarch64-neon-minmax-upgrade.ll b/llvm/test/Bitcode/aarch64-neon-minmax-upgrade.ll new file mode 100644 index 0000000000000..a8327aa3cdcfb --- /dev/null +++ b/llvm/test/Bitcode/aarch64-neon-minmax-upgrade.ll @@ -0,0 +1,58 @@ +; RUN: llvm-as < %s | llvm-dis | FileCheck %s + +define <4 x i32> @smin(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: @smin +; CHECK: call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> %b) + %r = call <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %r +} + +define <8 x i16> @smax(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: @smax +; CHECK: call <8 x i16> @llvm.smax.v8i16(<8 x i16> %a, <8 x i16> %b) + %r = call <8 x i16> @llvm.aarch64.neon.smax.v8i16(<8 x i16> %a, <8 x i16> %b) + ret <8 x i16> %r +} + +define <16 x i8> @umin(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: @umin +; CHECK: call <16 x i8> @llvm.umin.v16i8(<16 x i8> %a, <16 x i8> %b) + %r = call <16 x i8> @llvm.aarch64.neon.umin.v16i8(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %r +} + +define <2 x i32> @umax(<2 x i32> %a, <2 x i32> %b) { +; CHECK-LABEL: @umax +; CHECK: call <2 x i32> @llvm.umax.v2i32(<2 x i32> %a, <2 x i32> %b) + %r = call <2 x i32> @llvm.aarch64.neon.umax.v2i32(<2 x i32> %a, <2 x i32> %b) + ret <2 x i32> %r +} + +define i32 @sminv_not_upgraded(<4 x i32> %a) { +; CHECK-LABEL: @sminv_not_upgraded +; CHECK: call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a) + %r = call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a) + ret i32 %r +} + +define <4 x i32> @sminp_not_upgraded(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: @sminp_not_upgraded +; CHECK: call <4 x i32> @llvm.aarch64.neon.sminp.v4i32(<4 x i32> %a, <4 x i32> %b) + %r = call <4 x i32> @llvm.aarch64.neon.sminp.v4i32(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %r +} + +define <4 x i32> @umaxp_not_upgraded(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: @umaxp_not_upgraded +; CHECK: call <4 x i32> @llvm.aarch64.neon.umaxp.v4i32(<4 x i32> %a, <4 x i32> %b) + %r = call <4 x i32> @llvm.aarch64.neon.umaxp.v4i32(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %r +} + +declare <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32>, <4 x i32>) +declare <8 x i16> @llvm.aarch64.neon.smax.v8i16(<8 x i16>, <8 x i16>) +declare <16 x i8> @llvm.aarch64.neon.umin.v16i8(<16 x i8>, <16 x i8>) +declare <2 x i32> @llvm.aarch64.neon.umax.v2i32(<2 x i32>, <2 x i32>) +declare i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32>) +declare <4 x i32> @llvm.aarch64.neon.sminp.v4i32(<4 x i32>, <4 x i32>) +declare <4 x i32> @llvm.aarch64.neon.umaxp.v4i32(<4 x i32>, <4 x i32>) diff --git a/llvm/test/CodeGen/AArch64/abd-combine.ll b/llvm/test/CodeGen/AArch64/abd-combine.ll index 2d146d956ceea..8ceac6b69865a 100644 --- a/llvm/test/CodeGen/AArch64/abd-combine.ll +++ b/llvm/test/CodeGen/AArch64/abd-combine.ll @@ -504,10 +504,9 @@ define <8 x i16> @abds_i_reassoc(<8 x i16> %src1) { define <1 x i64> @recursive() { ; CHECK-LABEL: recursive: ; CHECK: // %bb.0: -; CHECK-NEXT: movi v0.8b, #254 -; CHECK-NEXT: ushll v1.8h, v0.8b, #0 -; CHECK-NEXT: dup v0.8b, v0.b[0] -; CHECK-NEXT: saddlp v1.1d, v1.2s +; CHECK-NEXT: movi v0.4h, #254 +; CHECK-NEXT: movi v1.8b, #254 +; CHECK-NEXT: saddlp v0.1d, v0.2s ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b ; CHECK-NEXT: ret %1 = tail call <8 x i8> @llvm.aarch64.neon.umax.v8i8(<8 x i8> zeroinitializer, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>) diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmax.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmax.ll index d6d88956a4f68..60ccce34bf32c 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmax.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmax.ll @@ -34,7 +34,7 @@ define <8 x i8> @smax_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1:![0-9]+]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3:[0-9]+]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 8 @@ -45,7 +45,7 @@ define <8 x i8> @smax_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 8 @@ -54,7 +54,7 @@ define <8 x i8> @smax_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 8 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i8> @llvm.aarch64.neon.smax.v8i8(<8 x i8> [[TMPVAR1]], <8 x i8> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i8> @llvm.smax.v8i8(<8 x i8> [[TMPVAR1]], <8 x i8> [[TMPVAR2]]) ; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i8> [[TMPVAR3]] ; @@ -73,7 +73,7 @@ define <16 x i8> @smax_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 16 @@ -84,7 +84,7 @@ define <16 x i8> @smax_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 16 @@ -93,7 +93,7 @@ define <16 x i8> @smax_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 16 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <16 x i8> @llvm.aarch64.neon.smax.v16i8(<16 x i8> [[TMPVAR1]], <16 x i8> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <16 x i8> @llvm.smax.v16i8(<16 x i8> [[TMPVAR1]], <16 x i8> [[TMPVAR2]]) ; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i8> [[TMPVAR3]] ; @@ -112,7 +112,7 @@ define <4 x i16> @smax_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 8 @@ -123,7 +123,7 @@ define <4 x i16> @smax_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 8 @@ -132,7 +132,7 @@ define <4 x i16> @smax_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 8 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i16> @llvm.aarch64.neon.smax.v4i16(<4 x i16> [[TMPVAR1]], <4 x i16> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i16> @llvm.smax.v4i16(<4 x i16> [[TMPVAR1]], <4 x i16> [[TMPVAR2]]) ; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i16> [[TMPVAR3]] ; @@ -151,7 +151,7 @@ define <8 x i16> @smax_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 16 @@ -162,7 +162,7 @@ define <8 x i16> @smax_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 16 @@ -171,7 +171,7 @@ define <8 x i16> @smax_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 16 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i16> @llvm.aarch64.neon.smax.v8i16(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i16> @llvm.smax.v8i16(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]]) ; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[TMPVAR3]] ; @@ -190,7 +190,7 @@ define <2 x i32> @smax_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 8 @@ -201,7 +201,7 @@ define <2 x i32> @smax_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 8 @@ -210,7 +210,7 @@ define <2 x i32> @smax_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.smax.v2i32(<2 x i32> [[TMPVAR1]], <2 x i32> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[TMPVAR1]], <2 x i32> [[TMPVAR2]]) ; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]] ; @@ -229,7 +229,7 @@ define <4 x i32> @smax_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 16 @@ -240,7 +240,7 @@ define <4 x i32> @smax_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 16 @@ -249,7 +249,7 @@ define <4 x i32> @smax_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 16 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]]) ; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]] ; @@ -275,7 +275,7 @@ define <8 x i8> @umax_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 8 @@ -286,7 +286,7 @@ define <8 x i8> @umax_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 8 @@ -295,7 +295,7 @@ define <8 x i8> @umax_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 8 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i8> @llvm.aarch64.neon.umax.v8i8(<8 x i8> [[TMPVAR1]], <8 x i8> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i8> @llvm.umax.v8i8(<8 x i8> [[TMPVAR1]], <8 x i8> [[TMPVAR2]]) ; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i8> [[TMPVAR3]] ; @@ -314,7 +314,7 @@ define <16 x i8> @umax_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 16 @@ -325,7 +325,7 @@ define <16 x i8> @umax_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 16 @@ -334,7 +334,7 @@ define <16 x i8> @umax_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 16 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <16 x i8> @llvm.aarch64.neon.umax.v16i8(<16 x i8> [[TMPVAR1]], <16 x i8> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <16 x i8> @llvm.umax.v16i8(<16 x i8> [[TMPVAR1]], <16 x i8> [[TMPVAR2]]) ; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i8> [[TMPVAR3]] ; @@ -353,7 +353,7 @@ define <4 x i16> @umax_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 8 @@ -364,7 +364,7 @@ define <4 x i16> @umax_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 8 @@ -373,7 +373,7 @@ define <4 x i16> @umax_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 8 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i16> @llvm.aarch64.neon.umax.v4i16(<4 x i16> [[TMPVAR1]], <4 x i16> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i16> @llvm.umax.v4i16(<4 x i16> [[TMPVAR1]], <4 x i16> [[TMPVAR2]]) ; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i16> [[TMPVAR3]] ; @@ -392,7 +392,7 @@ define <8 x i16> @umax_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 16 @@ -403,7 +403,7 @@ define <8 x i16> @umax_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 16 @@ -412,7 +412,7 @@ define <8 x i16> @umax_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 16 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i16> @llvm.aarch64.neon.umax.v8i16(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i16> @llvm.umax.v8i16(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]]) ; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[TMPVAR3]] ; @@ -431,7 +431,7 @@ define <2 x i32> @umax_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 8 @@ -442,7 +442,7 @@ define <2 x i32> @umax_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 8 @@ -451,7 +451,7 @@ define <2 x i32> @umax_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.umax.v2i32(<2 x i32> [[TMPVAR1]], <2 x i32> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[TMPVAR1]], <2 x i32> [[TMPVAR2]]) ; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]] ; @@ -470,7 +470,7 @@ define <4 x i32> @umax_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 16 @@ -481,7 +481,7 @@ define <4 x i32> @umax_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 16 @@ -490,7 +490,7 @@ define <4 x i32> @umax_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 16 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]]) ; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]] ; @@ -516,7 +516,7 @@ define <8 x i8> @smin_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 8 @@ -527,7 +527,7 @@ define <8 x i8> @smin_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 8 @@ -536,7 +536,7 @@ define <8 x i8> @smin_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 8 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i8> @llvm.aarch64.neon.smin.v8i8(<8 x i8> [[TMPVAR1]], <8 x i8> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i8> @llvm.smin.v8i8(<8 x i8> [[TMPVAR1]], <8 x i8> [[TMPVAR2]]) ; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i8> [[TMPVAR3]] ; @@ -555,7 +555,7 @@ define <16 x i8> @smin_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 16 @@ -566,7 +566,7 @@ define <16 x i8> @smin_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 16 @@ -575,7 +575,7 @@ define <16 x i8> @smin_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 16 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <16 x i8> @llvm.aarch64.neon.smin.v16i8(<16 x i8> [[TMPVAR1]], <16 x i8> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <16 x i8> @llvm.smin.v16i8(<16 x i8> [[TMPVAR1]], <16 x i8> [[TMPVAR2]]) ; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i8> [[TMPVAR3]] ; @@ -594,7 +594,7 @@ define <4 x i16> @smin_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 8 @@ -605,7 +605,7 @@ define <4 x i16> @smin_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 8 @@ -614,7 +614,7 @@ define <4 x i16> @smin_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 8 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i16> @llvm.aarch64.neon.smin.v4i16(<4 x i16> [[TMPVAR1]], <4 x i16> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i16> @llvm.smin.v4i16(<4 x i16> [[TMPVAR1]], <4 x i16> [[TMPVAR2]]) ; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i16> [[TMPVAR3]] ; @@ -633,7 +633,7 @@ define <8 x i16> @smin_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 16 @@ -644,7 +644,7 @@ define <8 x i16> @smin_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 16 @@ -653,7 +653,7 @@ define <8 x i16> @smin_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 16 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i16> @llvm.aarch64.neon.smin.v8i16(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i16> @llvm.smin.v8i16(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]]) ; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[TMPVAR3]] ; @@ -672,7 +672,7 @@ define <2 x i32> @smin_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 8 @@ -683,7 +683,7 @@ define <2 x i32> @smin_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 8 @@ -692,7 +692,7 @@ define <2 x i32> @smin_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.smin.v2i32(<2 x i32> [[TMPVAR1]], <2 x i32> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[TMPVAR1]], <2 x i32> [[TMPVAR2]]) ; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]] ; @@ -711,7 +711,7 @@ define <4 x i32> @smin_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 16 @@ -722,7 +722,7 @@ define <4 x i32> @smin_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 16 @@ -731,7 +731,7 @@ define <4 x i32> @smin_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 16 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]]) ; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]] ; @@ -757,7 +757,7 @@ define <8 x i8> @umin_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 8 @@ -768,7 +768,7 @@ define <8 x i8> @umin_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 8 @@ -777,7 +777,7 @@ define <8 x i8> @umin_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 8 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i8> @llvm.aarch64.neon.umin.v8i8(<8 x i8> [[TMPVAR1]], <8 x i8> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i8> @llvm.umin.v8i8(<8 x i8> [[TMPVAR1]], <8 x i8> [[TMPVAR2]]) ; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i8> [[TMPVAR3]] ; @@ -796,7 +796,7 @@ define <16 x i8> @umin_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 16 @@ -807,7 +807,7 @@ define <16 x i8> @umin_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 16 @@ -816,7 +816,7 @@ define <16 x i8> @umin_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 16 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <16 x i8> @llvm.aarch64.neon.umin.v16i8(<16 x i8> [[TMPVAR1]], <16 x i8> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <16 x i8> @llvm.umin.v16i8(<16 x i8> [[TMPVAR1]], <16 x i8> [[TMPVAR2]]) ; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i8> [[TMPVAR3]] ; @@ -835,7 +835,7 @@ define <4 x i16> @umin_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 8 @@ -846,7 +846,7 @@ define <4 x i16> @umin_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 8 @@ -855,7 +855,7 @@ define <4 x i16> @umin_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 8 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i16> @llvm.aarch64.neon.umin.v4i16(<4 x i16> [[TMPVAR1]], <4 x i16> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i16> @llvm.umin.v4i16(<4 x i16> [[TMPVAR1]], <4 x i16> [[TMPVAR2]]) ; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i16> [[TMPVAR3]] ; @@ -874,7 +874,7 @@ define <8 x i16> @umin_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 16 @@ -885,7 +885,7 @@ define <8 x i16> @umin_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 16 @@ -894,7 +894,7 @@ define <8 x i16> @umin_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 16 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i16> @llvm.aarch64.neon.umin.v8i16(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i16> @llvm.umin.v8i16(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]]) ; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[TMPVAR3]] ; @@ -913,7 +913,7 @@ define <2 x i32> @umin_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 8 @@ -924,7 +924,7 @@ define <2 x i32> @umin_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 8 @@ -933,7 +933,7 @@ define <2 x i32> @umin_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32> [[TMPVAR1]], <2 x i32> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[TMPVAR1]], <2 x i32> [[TMPVAR2]]) ; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]] ; @@ -952,7 +952,7 @@ define <4 x i32> @umin_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 16 @@ -963,7 +963,7 @@ define <4 x i32> @umin_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 16 @@ -972,7 +972,7 @@ define <4 x i32> @umin_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr ; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 16 ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]] -; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]]) +; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.umin.v4i32(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]]) ; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]] ; @@ -999,7 +999,7 @@ define <8 x i8> @smaxp_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 8 @@ -1010,7 +1010,7 @@ define <8 x i8> @smaxp_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 8 @@ -1040,7 +1040,7 @@ define <16 x i8> @smaxp_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 16 @@ -1051,7 +1051,7 @@ define <16 x i8> @smaxp_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 16 @@ -1081,7 +1081,7 @@ define <4 x i16> @smaxp_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 8 @@ -1092,7 +1092,7 @@ define <4 x i16> @smaxp_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 8 @@ -1122,7 +1122,7 @@ define <8 x i16> @smaxp_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 16 @@ -1133,7 +1133,7 @@ define <8 x i16> @smaxp_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 16 @@ -1163,7 +1163,7 @@ define <2 x i32> @smaxp_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 8 @@ -1174,7 +1174,7 @@ define <2 x i32> @smaxp_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 8 @@ -1204,7 +1204,7 @@ define <4 x i32> @smaxp_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 16 @@ -1215,7 +1215,7 @@ define <4 x i32> @smaxp_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 16 @@ -1252,7 +1252,7 @@ define <8 x i8> @umaxp_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 8 @@ -1263,7 +1263,7 @@ define <8 x i8> @umaxp_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 8 @@ -1293,7 +1293,7 @@ define <16 x i8> @umaxp_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 16 @@ -1304,7 +1304,7 @@ define <16 x i8> @umaxp_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 16 @@ -1334,7 +1334,7 @@ define <4 x i16> @umaxp_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 8 @@ -1345,7 +1345,7 @@ define <4 x i16> @umaxp_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 8 @@ -1375,7 +1375,7 @@ define <8 x i16> @umaxp_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 16 @@ -1386,7 +1386,7 @@ define <8 x i16> @umaxp_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 16 @@ -1416,7 +1416,7 @@ define <2 x i32> @umaxp_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 8 @@ -1427,7 +1427,7 @@ define <2 x i32> @umaxp_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 8 @@ -1457,7 +1457,7 @@ define <4 x i32> @umaxp_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 16 @@ -1468,7 +1468,7 @@ define <4 x i32> @umaxp_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 16 @@ -1506,7 +1506,7 @@ define <8 x i8> @sminp_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 8 @@ -1517,7 +1517,7 @@ define <8 x i8> @sminp_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 8 @@ -1547,7 +1547,7 @@ define <16 x i8> @sminp_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 16 @@ -1558,7 +1558,7 @@ define <16 x i8> @sminp_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 16 @@ -1588,7 +1588,7 @@ define <4 x i16> @sminp_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 8 @@ -1599,7 +1599,7 @@ define <4 x i16> @sminp_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 8 @@ -1629,7 +1629,7 @@ define <8 x i16> @sminp_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 16 @@ -1640,7 +1640,7 @@ define <8 x i16> @sminp_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 16 @@ -1670,7 +1670,7 @@ define <2 x i32> @sminp_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 8 @@ -1681,7 +1681,7 @@ define <2 x i32> @sminp_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 8 @@ -1711,7 +1711,7 @@ define <4 x i32> @sminp_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 16 @@ -1722,7 +1722,7 @@ define <4 x i32> @sminp_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 16 @@ -1759,7 +1759,7 @@ define <8 x i8> @uminp_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 8 @@ -1770,7 +1770,7 @@ define <8 x i8> @uminp_8b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 8 @@ -1800,7 +1800,7 @@ define <16 x i8> @uminp_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 16 @@ -1811,7 +1811,7 @@ define <16 x i8> @uminp_16b(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 16 @@ -1841,7 +1841,7 @@ define <4 x i16> @uminp_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 8 @@ -1852,7 +1852,7 @@ define <4 x i16> @uminp_4h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 8 @@ -1882,7 +1882,7 @@ define <8 x i16> @uminp_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 16 @@ -1893,7 +1893,7 @@ define <8 x i16> @uminp_8h(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 16 @@ -1923,7 +1923,7 @@ define <2 x i32> @uminp_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 8 @@ -1934,7 +1934,7 @@ define <2 x i32> @uminp_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 8 @@ -1964,7 +1964,7 @@ define <4 x i32> @uminp_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 16 @@ -1975,7 +1975,7 @@ define <4 x i32> @uminp_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 16 @@ -2012,7 +2012,7 @@ define <2 x float> @fmax_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x float>, ptr [[A]], align 8 @@ -2023,7 +2023,7 @@ define <2 x float> @fmax_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x float>, ptr [[B]], align 8 @@ -2051,7 +2051,7 @@ define <4 x float> @fmax_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x float>, ptr [[A]], align 16 @@ -2062,7 +2062,7 @@ define <4 x float> @fmax_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x float>, ptr [[B]], align 16 @@ -2090,7 +2090,7 @@ define <2 x double> @fmax_2d(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x double>, ptr [[A]], align 16 @@ -2101,7 +2101,7 @@ define <2 x double> @fmax_2d(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x double>, ptr [[B]], align 16 @@ -2133,7 +2133,7 @@ define <2 x float> @fmaxp_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x float>, ptr [[A]], align 8 @@ -2144,7 +2144,7 @@ define <2 x float> @fmaxp_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x float>, ptr [[B]], align 8 @@ -2174,7 +2174,7 @@ define <4 x float> @fmaxp_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x float>, ptr [[A]], align 16 @@ -2185,7 +2185,7 @@ define <4 x float> @fmaxp_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x float>, ptr [[B]], align 16 @@ -2215,7 +2215,7 @@ define <2 x double> @fmaxp_2d(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x double>, ptr [[A]], align 16 @@ -2226,7 +2226,7 @@ define <2 x double> @fmaxp_2d(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x double>, ptr [[B]], align 16 @@ -2260,7 +2260,7 @@ define <2 x float> @fmin_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x float>, ptr [[A]], align 8 @@ -2271,7 +2271,7 @@ define <2 x float> @fmin_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x float>, ptr [[B]], align 8 @@ -2299,7 +2299,7 @@ define <4 x float> @fmin_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x float>, ptr [[A]], align 16 @@ -2310,7 +2310,7 @@ define <4 x float> @fmin_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x float>, ptr [[B]], align 16 @@ -2338,7 +2338,7 @@ define <2 x double> @fmin_2d(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x double>, ptr [[A]], align 16 @@ -2349,7 +2349,7 @@ define <2 x double> @fmin_2d(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x double>, ptr [[B]], align 16 @@ -2381,7 +2381,7 @@ define <2 x float> @fminp_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x float>, ptr [[A]], align 8 @@ -2392,7 +2392,7 @@ define <2 x float> @fminp_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x float>, ptr [[B]], align 8 @@ -2422,7 +2422,7 @@ define <4 x float> @fminp_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x float>, ptr [[A]], align 16 @@ -2433,7 +2433,7 @@ define <4 x float> @fminp_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x float>, ptr [[B]], align 16 @@ -2463,7 +2463,7 @@ define <2 x double> @fminp_2d(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x double>, ptr [[A]], align 16 @@ -2474,7 +2474,7 @@ define <2 x double> @fminp_2d(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x double>, ptr [[B]], align 16 @@ -2508,7 +2508,7 @@ define <2 x float> @fminnmp_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x float>, ptr [[A]], align 8 @@ -2519,7 +2519,7 @@ define <2 x float> @fminnmp_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x float>, ptr [[B]], align 8 @@ -2549,7 +2549,7 @@ define <4 x float> @fminnmp_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x float>, ptr [[A]], align 16 @@ -2560,7 +2560,7 @@ define <4 x float> @fminnmp_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x float>, ptr [[B]], align 16 @@ -2590,7 +2590,7 @@ define <2 x double> @fminnmp_2d(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x double>, ptr [[A]], align 16 @@ -2601,7 +2601,7 @@ define <2 x double> @fminnmp_2d(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x double>, ptr [[B]], align 16 @@ -2635,7 +2635,7 @@ define <2 x float> @fmaxnmp_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x float>, ptr [[A]], align 8 @@ -2646,7 +2646,7 @@ define <2 x float> @fmaxnmp_2s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x float>, ptr [[B]], align 8 @@ -2676,7 +2676,7 @@ define <4 x float> @fmaxnmp_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x float>, ptr [[A]], align 16 @@ -2687,7 +2687,7 @@ define <4 x float> @fmaxnmp_4s(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x float>, ptr [[B]], align 16 @@ -2717,7 +2717,7 @@ define <2 x double> @fmaxnmp_2d(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] ; CHECK: [[BB3]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB4]]: ; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x double>, ptr [[A]], align 16 @@ -2728,7 +2728,7 @@ define <2 x double> @fmaxnmp_2d(ptr %A, ptr %B) nounwind #0 { ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] ; CHECK: [[BB8]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: [[BB9]]: ; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x double>, ptr [[B]], align 16 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
