================ @@ -5855,6 +5855,10 @@ def mzilsd_word_align : Flag<["-"], "mzilsd-word-align">, Group<m_Group>, HelpText<"Allow Zilsd/Zclsd memory accesses to be 4-byte aligned (RISC-V only)">; def mzilsd_strict_align : Flag<["-"], "mzilsd-strict-align">, Group<m_Group>, HelpText<"Force all Zilsd/Zclsd memory accesses to be 8-byte aligned (RISC-V only)">; +def mvector_index_load_overlap : Flag<["-"], "mvector-index-load-overlap">, Group<m_Group>, ---------------- topperc wrote:
We need to give this option to our customers. I would prefer it was not a complex `-Xclang` option. AArch64 has at least 5 workaround options in clang so this isn't unprecedented. https://github.com/llvm/llvm-project/pull/224739 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
