llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Chibuoyim (Wilson) Ogbonna (bruteforceboy) <details> <summary>Changes</summary> This adds CIR tests for `svaddv` intrinsics following the task description in [223963](https://github.com/llvm/llvm-project/issues/223963). Moves and adapts `sve-intrinsics/acle_sve_addv.c` to `sve/addv.c`. --- Patch is 21.32 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/225648.diff 2 Files Affected: - (removed) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_addv.c (-206) - (added) clang/test/CodeGen/AArch64/sve/addv.c (+192) ``````````diff diff --git a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_addv.c b/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_addv.c deleted file mode 100644 index efd00469989578..00000000000000 --- a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_addv.c +++ /dev/null @@ -1,206 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s -// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s - -#include <arm_sve.h> - -#if defined __ARM_FEATURE_SME -#define MODE_ATTR __arm_streaming -#else -#define MODE_ATTR -#endif - -#ifdef SVE_OVERLOADED_FORMS -// A simple used,unused... macro, long enough to represent any SVE builtin. -#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 -#else -#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 -#endif - -// CHECK-LABEL: @test_svaddv_s8( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.saddv.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]]) -// CHECK-NEXT: ret i64 [[TMP0]] -// -// CPP-CHECK-LABEL: @_Z14test_svaddv_s8u10__SVBool_tu10__SVInt8_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.saddv.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret i64 [[TMP0]] -// -int64_t test_svaddv_s8(svbool_t pg, svint8_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(svaddv,_s8,,)(pg, op); -} - -// CHECK-LABEL: @test_svaddv_s16( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.saddv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]]) -// CHECK-NEXT: ret i64 [[TMP1]] -// -// CPP-CHECK-LABEL: @_Z15test_svaddv_s16u10__SVBool_tu11__SVInt16_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.saddv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret i64 [[TMP1]] -// -int64_t test_svaddv_s16(svbool_t pg, svint16_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(svaddv,_s16,,)(pg, op); -} - -// CHECK-LABEL: @test_svaddv_s32( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.saddv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]]) -// CHECK-NEXT: ret i64 [[TMP1]] -// -// CPP-CHECK-LABEL: @_Z15test_svaddv_s32u10__SVBool_tu11__SVInt32_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.saddv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret i64 [[TMP1]] -// -int64_t test_svaddv_s32(svbool_t pg, svint32_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(svaddv,_s32,,)(pg, op); -} - -// CHECK-LABEL: @test_svaddv_s64( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.saddv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]]) -// CHECK-NEXT: ret i64 [[TMP1]] -// -// CPP-CHECK-LABEL: @_Z15test_svaddv_s64u10__SVBool_tu11__SVInt64_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.saddv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret i64 [[TMP1]] -// -int64_t test_svaddv_s64(svbool_t pg, svint64_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(svaddv,_s64,,)(pg, op); -} - -// CHECK-LABEL: @test_svaddv_u8( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.uaddv.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]]) -// CHECK-NEXT: ret i64 [[TMP0]] -// -// CPP-CHECK-LABEL: @_Z14test_svaddv_u8u10__SVBool_tu11__SVUint8_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.uaddv.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret i64 [[TMP0]] -// -uint64_t test_svaddv_u8(svbool_t pg, svuint8_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(svaddv,_u8,,)(pg, op); -} - -// CHECK-LABEL: @test_svaddv_u16( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.uaddv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]]) -// CHECK-NEXT: ret i64 [[TMP1]] -// -// CPP-CHECK-LABEL: @_Z15test_svaddv_u16u10__SVBool_tu12__SVUint16_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.uaddv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret i64 [[TMP1]] -// -uint64_t test_svaddv_u16(svbool_t pg, svuint16_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(svaddv,_u16,,)(pg, op); -} - -// CHECK-LABEL: @test_svaddv_u32( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.uaddv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]]) -// CHECK-NEXT: ret i64 [[TMP1]] -// -// CPP-CHECK-LABEL: @_Z15test_svaddv_u32u10__SVBool_tu12__SVUint32_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.uaddv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret i64 [[TMP1]] -// -uint64_t test_svaddv_u32(svbool_t pg, svuint32_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(svaddv,_u32,,)(pg, op); -} - -// CHECK-LABEL: @test_svaddv_u64( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.uaddv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]]) -// CHECK-NEXT: ret i64 [[TMP1]] -// -// CPP-CHECK-LABEL: @_Z15test_svaddv_u64u10__SVBool_tu12__SVUint64_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.uaddv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret i64 [[TMP1]] -// -uint64_t test_svaddv_u64(svbool_t pg, svuint64_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(svaddv,_u64,,)(pg, op); -} - -// CHECK-LABEL: @test_svaddv_f16( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) -// CHECK-NEXT: ret half [[TMP1]] -// -// CPP-CHECK-LABEL: @_Z15test_svaddv_f16u10__SVBool_tu13__SVFloat16_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret half [[TMP1]] -// -float16_t test_svaddv_f16(svbool_t pg, svfloat16_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(svaddv,_f16,,)(pg, op); -} - -// CHECK-LABEL: @test_svaddv_f32( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) -// CHECK-NEXT: ret float [[TMP1]] -// -// CPP-CHECK-LABEL: @_Z15test_svaddv_f32u10__SVBool_tu13__SVFloat32_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret float [[TMP1]] -// -float32_t test_svaddv_f32(svbool_t pg, svfloat32_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(svaddv,_f32,,)(pg, op); -} - -// CHECK-LABEL: @test_svaddv_f64( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) -// CHECK-NEXT: ret double [[TMP1]] -// -// CPP-CHECK-LABEL: @_Z15test_svaddv_f64u10__SVBool_tu13__SVFloat64_t( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) -// CPP-CHECK-NEXT: ret double [[TMP1]] -// -float64_t test_svaddv_f64(svbool_t pg, svfloat64_t op) MODE_ATTR -{ - return SVE_ACLE_FUNC(svaddv,_f64,,)(pg, op); -} diff --git a/clang/test/CodeGen/AArch64/sve/addv.c b/clang/test/CodeGen/AArch64/sve/addv.c new file mode 100644 index 00000000000000..6495a90a667531 --- /dev/null +++ b/clang/test/CodeGen/AArch64/sve/addv.c @@ -0,0 +1,192 @@ +// REQUIRES: aarch64-registered-target + +// DEFINE: %{optimize} = opt -passes=mem2reg,instcombine,tailcallelim -S + +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -fclangir -emit-cir -disable-O0-optnone -o - %s | FileCheck %s --check-prefixes=ALL,CIR %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-cir -disable-O0-optnone -o - %s | FileCheck %s --check-prefixes=ALL,CIR %} + +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -fclangir -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=ALL,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=ALL,LLVM %} + +// RUN: %clang_cc1_cg_arm64_sve -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=ALL,LLVM +// RUN: %clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=ALL,LLVM + +//============================================================================= +// NOTES +// +// Tests for SVE ADDV intrinsics +//============================================================================= + +#include <arm_sve.h> + +#if defined __ARM_FEATURE_SME +#define MODE_ATTR __arm_streaming +#else +#define MODE_ATTR +#endif + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 +#endif + +// ALL-LABEL: @test_svaddv_s8 +int64_t test_svaddv_s8(svbool_t pg, svint8_t op) MODE_ATTR +{ +// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.saddv" %{{.*}}, %{{.*}} : +// CIR-SAME: -> !s64i + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.saddv.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[OP]]) +// LLVM: ret i64 [[TMP0]] + return SVE_ACLE_FUNC(svaddv,_s8,,)(pg, op); +} + +// ALL-LABEL: @test_svaddv_s16 +int64_t test_svaddv_s16(svbool_t pg, svint16_t op) MODE_ATTR +{ +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} : +// CIR-SAME: -> !cir.vector<[8] x !cir.int<u, 1>> +// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.saddv" %[[CONVERT_PG]], %{{.*}} : +// CIR-SAME: -> !s64i + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 8 x i16> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.saddv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP]]) +// LLVM: ret i64 [[TMP1]] + return SVE_ACLE_FUNC(svaddv,_s16,,)(pg, op); +} + +// ALL-LABEL: @test_svaddv_s32 +int64_t test_svaddv_s32(svbool_t pg, svint32_t op) MODE_ATTR +{ +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} : +// CIR-SAME: -> !cir.vector<[4] x !cir.int<u, 1>> +// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.saddv" %[[CONVERT_PG]], %{{.*}} : +// CIR-SAME: -> !s64i + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 4 x i32> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.saddv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP]]) +// LLVM: ret i64 [[TMP1]] + return SVE_ACLE_FUNC(svaddv,_s32,,)(pg, op); +} + +// ALL-LABEL: @test_svaddv_s64 +int64_t test_svaddv_s64(svbool_t pg, svint64_t op) MODE_ATTR +{ +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} : +// CIR-SAME: -> !cir.vector<[2] x !cir.int<u, 1>> +// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.saddv" %[[CONVERT_PG]], %{{.*}} : +// CIR-SAME: -> !s64i + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 2 x i64> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.saddv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP]]) +// LLVM: ret i64 [[TMP1]] + return SVE_ACLE_FUNC(svaddv,_s64,,)(pg, op); +} + +// ALL-LABEL: @test_svaddv_u8 +uint64_t test_svaddv_u8(svbool_t pg, svuint8_t op) MODE_ATTR +{ +// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.uaddv" %{{.*}}, %{{.*}} : +// CIR-SAME: -> !u64i + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.uaddv.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[OP]]) +// LLVM: ret i64 [[TMP0]] + return SVE_ACLE_FUNC(svaddv,_u8,,)(pg, op); +} + +// ALL-LABEL: @test_svaddv_u16 +uint64_t test_svaddv_u16(svbool_t pg, svuint16_t op) MODE_ATTR +{ +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} : +// CIR-SAME: -> !cir.vector<[8] x !cir.int<u, 1>> +// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.uaddv" %[[CONVERT_PG]], %{{.*}} : +// CIR-SAME: -> !u64i + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 8 x i16> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.uaddv.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP]]) +// LLVM: ret i64 [[TMP1]] + return SVE_ACLE_FUNC(svaddv,_u16,,)(pg, op); +} + +// ALL-LABEL: @test_svaddv_u32 +uint64_t test_svaddv_u32(svbool_t pg, svuint32_t op) MODE_ATTR +{ +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} : +// CIR-SAME: -> !cir.vector<[4] x !cir.int<u, 1>> +// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.uaddv" %[[CONVERT_PG]], %{{.*}} : +// CIR-SAME: -> !u64i + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 4 x i32> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.uaddv.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP]]) +// LLVM: ret i64 [[TMP1]] + return SVE_ACLE_FUNC(svaddv,_u32,,)(pg, op); +} + +// ALL-LABEL: @test_svaddv_u64 +uint64_t test_svaddv_u64(svbool_t pg, svuint64_t op) MODE_ATTR +{ +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} : +// CIR-SAME: -> !cir.vector<[2] x !cir.int<u, 1>> +// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.uaddv" %[[CONVERT_PG]], %{{.*}} : +// CIR-SAME: -> !u64i + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 2 x i64> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = tail call i64 @llvm.aarch64.sve.uaddv.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP]]) +// LLVM: ret i64 [[TMP1]] + return SVE_ACLE_FUNC(svaddv,_u64,,)(pg, op); +} + +// ALL-LABEL: @test_svaddv_f16 +float16_t test_svaddv_f16(svbool_t pg, svfloat16_t op) MODE_ATTR +{ +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} : +// CIR-SAME: -> !cir.vector<[8] x !cir.int<u, 1>> +// CIR: %[[RES:.*]] = cir.call_llvm_intrinsic "aarch64.sve.faddv" %[[CONVERT_PG]], %{{.*}} : +// CIR-SAME: -> !cir.f16 + +// LLVM-SAME: <vscale x 16 x i1> [[PG:%.*]], <vscale x 8 x half> [[OP:%.*]]) +// LLVM: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]]) +// LLVM: [[TMP1:%.*]] = tail call half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP]]) +// LLVM: ret half [[TMP1]] + return SVE_ACLE_FUNC(svaddv,_f16,,)(pg, op); +} + +// ALL-LABEL: @test_svaddv_f32 +float32_t test_svaddv_f32(svbool_t pg, svfloat32_t op) MODE_ATTR +{ +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %{{.*}} : +// CIR-SAME: -> !cir.vector<[4] x !cir.int<u, 1>> +// CIR: %[[RES:.*]] = cir.call_llvm_intri... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/225648 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
