https://github.com/doac updated https://github.com/llvm/llvm-project/pull/225638
>From 8bbb112fe891e0db656875c8f4923ff79ee9ff4d Mon Sep 17 00:00:00 2001 From: Daniel Cederman <[email protected]> Date: Thu, 20 Aug 2026 13:15:53 +0200 Subject: [PATCH 1/3] [RISCV] Add processor definition and scheduling information for GR765 Add support for the GR765 processor from Frontgrade Gaisler. https://www.gaisler.com/products/gr765 Assisted-by: Codex --- .../print-enabled-extensions/riscv-gr765.c | 52 +++ clang/test/Driver/riscv-cpus.c | 5 + .../test/Misc/target-invalid-cpu-note/riscv.c | 2 + llvm/docs/ReleaseNotes.md | 1 + llvm/lib/Target/RISCV/RISCV.td | 1 + llvm/lib/Target/RISCV/RISCVProcessors.td | 53 +++ llvm/lib/Target/RISCV/RISCVSchedGR765.td | 324 ++++++++++++++++++ 7 files changed, 438 insertions(+) create mode 100644 clang/test/Driver/print-enabled-extensions/riscv-gr765.c create mode 100644 llvm/lib/Target/RISCV/RISCVSchedGR765.td diff --git a/clang/test/Driver/print-enabled-extensions/riscv-gr765.c b/clang/test/Driver/print-enabled-extensions/riscv-gr765.c new file mode 100644 index 00000000000000..1ed292e12d6d8a --- /dev/null +++ b/clang/test/Driver/print-enabled-extensions/riscv-gr765.c @@ -0,0 +1,52 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang --target=riscv64 -mcpu=gr765 --print-enabled-extensions | FileCheck %s + +// CHECK: Extensions enabled for the given RISC-V target +// CHECK: Name{{ *}}Version{{ *}}Description +// CHECK-DAG: i{{ *}}2.1{{ *}}'I' (Base Integer Instruction Set) +// CHECK-DAG: m{{ *}}2.0{{ *}}'M' (Integer Multiplication and Division) +// CHECK-DAG: a{{ *}}2.1{{ *}}'A' (Atomic Instructions) +// CHECK-DAG: f{{ *}}2.2{{ *}}'F' (Single-Precision Floating-Point) +// CHECK-DAG: d{{ *}}2.2{{ *}}'D' (Double-Precision Floating-Point) +// CHECK-DAG: c{{ *}}2.0{{ *}}'C' (Compressed Instructions) +// CHECK-DAG: h{{ *}}1.0{{ *}}'H' (Hypervisor) +// CHECK-DAG: zic64b{{ *}}1.0{{ *}}'Zic64b' (Cache Block Size Is 64 Bytes) +// CHECK-DAG: zicbom{{ *}}1.0{{ *}}'Zicbom' (Cache-Block Management Instructions) +// CHECK-DAG: zicntr{{ *}}2.0{{ *}}'Zicntr' (Base Counters and Timers) +// CHECK-DAG: zicsr{{ *}}2.0{{ *}}'Zicsr' (CSRs) +// CHECK-DAG: zifencei{{ *}}2.0{{ *}}'Zifencei' (fence.i) +// CHECK-DAG: zihpm{{ *}}2.0{{ *}}'Zihpm' (Hardware Performance Counters) +// CHECK-DAG: zba{{ *}}1.0{{ *}}'Zba' (Address Generation Instructions) +// CHECK-DAG: zbb{{ *}}1.0{{ *}}'Zbb' (Basic Bit-Manipulation) +// CHECK-DAG: zbc{{ *}}1.0{{ *}}'Zbc' (Carry-Less Multiplication) +// CHECK-DAG: zbs{{ *}}1.0{{ *}}'Zbs' (Single-Bit Instructions) +// CHECK-DAG: zcb{{ *}}1.0{{ *}}'Zcb' (Compressed basic bit manipulation instructions) +// CHECK-DAG: zcmop{{ *}}1.0{{ *}}'Zcmop' (Compressed May-Be-Operations) +// CHECK-DAG: zfa{{ *}}1.0{{ *}}'Zfa' (Additional Floating-Point) +// CHECK-DAG: zfbfmin{{ *}}1.0{{ *}}'Zfbfmin' (Scalar BF16 Converts) +// CHECK-DAG: zfh{{ *}}1.0{{ *}}'Zfh' (Half-Precision Floating-Point) +// CHECK-DAG: zfhmin{{ *}}1.0{{ *}}'Zfhmin' (Half-Precision Floating-Point Minimal) +// CHECK-DAG: zicfiss{{ *}}1.0{{ *}}'Zicfiss' (Shadow stack) +// CHECK-DAG: zicond{{ *}}1.0{{ *}}'Zicond' (Integer Conditional Operations) +// CHECK-DAG: zimop{{ *}}1.0{{ *}}'Zimop' (May-Be-Operations) +// CHECK-DAG: zkn{{ *}}1.0{{ *}}'Zkn' (NIST Algorithm Suite) +// CHECK-DAG: zkt{{ *}}1.0{{ *}}'Zkt' (Data Independent Execution Latency) +// CHECK-DAG: shlcofideleg{{ *}}1.0{{ *}}'Shlcofideleg' (Delegating LCOFI Interrupts to VS-mode) +// CHECK-DAG: smaia{{ *}}1.0{{ *}}'Smaia' (Advanced Interrupt Architecture Machine Level) +// CHECK-DAG: smcdeleg{{ *}}1.0{{ *}}'Smcdeleg' (Counter Delegation Machine Level) +// CHECK-DAG: smcntrpmf{{ *}}1.0{{ *}}'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering) +// CHECK-DAG: smcsrind{{ *}}1.0{{ *}}'Smcsrind' (Indirect CSR Access Machine Level) +// CHECK-DAG: ssaia{{ *}}1.0{{ *}}'Ssaia' (Advanced Interrupt Architecture Supervisor Level) +// CHECK-DAG: smdbltrp{{ *}}1.0{{ *}}'Smdbltrp' (Double Trap Machine Level) +// CHECK-DAG: smepmp{{ *}}1.0{{ *}}'Smepmp' (Enhanced Physical Memory Protection) +// CHECK-DAG: smrnmi{{ *}}1.0{{ *}}'Smrnmi' (Resumable Non-Maskable Interrupts) +// CHECK-DAG: smstateen{{ *}}1.0{{ *}}'Smstateen' (Machine-mode view of the state-enable extension) +// CHECK-DAG: sscofpmf{{ *}}1.0{{ *}}'Sscofpmf' (Count Overflow and Mode-Based Filtering) +// CHECK-DAG: sscsrind{{ *}}1.0{{ *}}'Sscsrind' (Indirect CSR Access Supervisor Level) +// CHECK-DAG: ssdbltrp{{ *}}1.0{{ *}}'Ssdbltrp' (Double Trap Supervisor Level) +// CHECK-DAG: sstc{{ *}}1.0{{ *}}'Sstc' (Supervisor-mode timer interrupts) +// CHECK-DAG: svadu{{ *}}1.0{{ *}}'Svadu' (Hardware A/D updates) +// CHECK-DAG: svinval{{ *}}1.0{{ *}}'Svinval' (Fine-Grained Address-Translation Cache Invalidation) +// CHECK-DAG: svnapot{{ *}}1.0{{ *}}'Svnapot' (NAPOT Translation Contiguity) +// CHECK-DAG: svpbmt{{ *}}1.0{{ *}}'Svpbmt' (Page-Based Memory Types) +// CHECK-DAG: svrsw60t59b{{ *}}1.0{{ *}}'Svrsw60t59b' (PTE Reserved-for-Software Bits 60-59) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 50d7ab7ab51b90..4fca57da88d333 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -761,3 +761,8 @@ // COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-xt-c920v2.c` // MCPU-XT-C920V2: "-target-cpu" "xt-c920v2" // MCPU-XT-C920V2-SAME: "-target-abi" "lp64d" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=gr765 | FileCheck -check-prefix=MCPU-GR765 %s +// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-gr765.c` +// MCPU-GR765: "-target-cpu" "gr765" +// MCPU-GR765-SAME: "-target-abi" "lp64d" diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c index 546dbbdb7e0434..9eb07b49e72bc8 100644 --- a/clang/test/Misc/target-invalid-cpu-note/riscv.c +++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c @@ -34,6 +34,7 @@ // RISCV64-SAME: {{^}}, andes-ax45mpv // RISCV64-SAME: {{^}}, andes-nx45 // RISCV64-SAME: {{^}}, et-soc1 +// RISCV64-SAME: {{^}}, gr765 // RISCV64-SAME: {{^}}, generic-rv64 // RISCV64-SAME: {{^}}, mips-p8700 // RISCV64-SAME: {{^}}, rocket-rv64 @@ -102,6 +103,7 @@ // TUNE-RISCV64-SAME: {{^}}, andes-ax45mpv // TUNE-RISCV64-SAME: {{^}}, andes-nx45 // TUNE-RISCV64-SAME: {{^}}, et-soc1 +// TUNE-RISCV64-SAME: {{^}}, gr765 // TUNE-RISCV64-SAME: {{^}}, generic-rv64 // TUNE-RISCV64-SAME: {{^}}, mips-p8700 // TUNE-RISCV64-SAME: {{^}}, rocket-rv64 diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index caa8dd6fe43577..952c7269690261 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -256,6 +256,7 @@ Makes programs 10x faster by doing Special New Thing. * Added experimental MC support for the ACLIC v0.20 extensions: `Smidctrl`, `Ssidctrl`, `Smnip`, `Ssnip`, `Smijt`, `Ssijt`, `Smehv`, `Ssehv`, `Smcsps`, `Sscsps`, `Smip`, and `Ssip`. +* Added `-mcpu=gr765` for the 64-bit GR765 processor. * Adds experimental assembler/CodeGen support for the `Zilx` (Indexed Integer Load) extension. * Bump Svukte extension to 1.0. diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 945a1e69359fc8..865f36313d52c0 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -53,6 +53,7 @@ include "RISCVMacroFusion.td" //===----------------------------------------------------------------------===// include "RISCVSchedAndes45.td" include "RISCVSchedGenericOOO.td" +include "RISCVSchedGR765.td" include "RISCVSchedMIPSP8700.td" include "RISCVSchedRocket.td" include "RISCVSchedSiFive7.td" diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 48150f7d4dddfb..7c14e4ca6e3992 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -1106,4 +1106,57 @@ def XUANTIE_C920V2 : RISCVProcessorModel<"xt-c920v2", FeatureUnalignedScalarMem]), [TuneVXRMPipelineFlush, TunePostRAScheduler]>; + +def GAISLER_GR765 : RISCVProcessorModel<"gr765", + GR765Model, + [Feature64Bit, + FeatureStdExtI, + FeatureStdExtZifencei, + FeatureStdExtZicsr, + FeatureStdExtZicntr, + FeatureStdExtZihpm, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtH, + FeatureStdExtShlcofideleg, + FeatureStdExtSmaia, + FeatureStdExtSmcdeleg, + FeatureStdExtSmcntrpmf, + FeatureStdExtSmcsrind, + FeatureStdExtSsaia, + FeatureStdExtSmdbltrp, + FeatureStdExtSmepmp, + FeatureStdExtSmrnmi, + FeatureStdExtSmstateen, + FeatureStdExtSscofpmf, + FeatureStdExtSscsrind, + FeatureStdExtSsdbltrp, + FeatureStdExtSstc, + FeatureStdExtSvadu, + FeatureStdExtSvinval, + FeatureStdExtSvnapot, + FeatureStdExtSvpbmt, + FeatureStdExtSvrsw60t59b, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbc, + FeatureStdExtZbs, + FeatureStdExtZcb, + FeatureStdExtZcmop, + FeatureStdExtZfa, + FeatureStdExtZfbfmin, + FeatureStdExtZfh, + FeatureStdExtZfhmin, + FeatureStdExtZic64b, + FeatureStdExtZicbom, + FeatureStdExtZicfiss, + FeatureStdExtZicond, + FeatureStdExtZimop, + FeatureStdExtZkn, + FeatureStdExtZkt], + [TunePostRAScheduler]>; + // clang-format on diff --git a/llvm/lib/Target/RISCV/RISCVSchedGR765.td b/llvm/lib/Target/RISCV/RISCVSchedGR765.td new file mode 100644 index 00000000000000..f1ec1ef2605b58 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVSchedGR765.td @@ -0,0 +1,324 @@ +//===-- RISCVSchedGR765.td - GR765 Scheduling Definitions -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Scheduling model for the GR765 RISCV-V configuration. +// +// Timing is taken from the GR765 Data Sheet User's Manual. +// +//===----------------------------------------------------------------------===// + +def GR765Model : SchedMachineModel { + // In-order dual-issue pipeline + let MicroOpBufferSize = 0; + let IssueWidth = 2; + let LoadLatency = 2; + let MispredictPenalty = 3; + let CompleteModel = false; + let UnsupportedFeatures = [HasStdExtZcmt, HasStdExtZksed, HasStdExtZksh, + HasVInstructions, HasVInstructionsI64, + HasStdExtZkr]; +} + +//===----------------------------------------------------------------------===// +// Processor resources +//===----------------------------------------------------------------------===// + +let BufferSize = 0 in { +def GR765UnitALU : ProcResource<2>; // Int ALUs +def GR765UnitIMul : ProcResource<1>; // Int Multiply +def GR765UnitMem : ProcResource<1>; // Load/Store +def GR765UnitB : ProcResource<1>; // Branch +def GR765UnitIssue0 : ProcResource<1>; // Lane 0 issue slot +def GR765UnitIssue1 : ProcResource<1>; // Lane 1 issue slot +def GR765UnitCLMUL : ProcResource<1>; // Carry-less multiply +def GR765UnitCrypto : ProcResource<1>; // AES / SHA unit + +def GR765UnitFPALU : ProcResource<1>; // FP FPR-result path +def GR765UnitFPTransfer : ProcResource<1>; // FP binary data transfer +def GR765UnitFPToInt : ProcResource<1>; // FP result to integer pipeline +} + +let BufferSize = 1 in { +def GR765UnitIDiv : ProcResource<1>; // Int Division +def GR765UnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt +} + +//===----------------------------------------------------------------------===// + +let SchedModel = GR765Model in { + +// Instructions may use either issue lane unless their class restricts it. +def GR765UnitIssue : ProcResGroup<[GR765UnitIssue0, GR765UnitIssue1]>; + +// Map scheduling writes with identical resource requirements. +multiclass GR765WriteRes<list<SchedWrite> Writes, + list<ProcResourceKind> Resources> { + foreach W = Writes in + def : WriteRes<W, Resources>; +} + +// Conditional branches issue in lane 1. JAL/JALR are single-issue. +let Latency = 2 in { +def : WriteRes<WriteJmp, [GR765UnitB, GR765UnitIssue1]>; +def : WriteRes<WriteJal, [GR765UnitB]> { let SingleIssue = true; } +def : WriteRes<WriteJalr, [GR765UnitB]> { let SingleIssue = true; } +} + +// Integer ALU results take two cycles except through the bypasses below. +let Latency = 2 in { +defm : GR765WriteRes<[WriteIALU32, WriteIALU, WriteShiftImm32, + WriteShiftImm, WriteShiftReg32, WriteShiftReg, + WriteSHXADD, WriteSHXADD32, WriteRotateImm, + WriteRotateImm32, WriteRotateReg, WriteRotateReg32, + WriteCLZ, WriteCLZ32, WriteCTZ, WriteCTZ32, WriteCPOP, + WriteCPOP32, WriteREV8, WriteORCB, WriteIMinMax, + WriteSingleBit, WriteSingleBitImm, WriteBEXT, + WriteBEXTI, WriteBREV8, WritePACK, WritePACK32, WriteZIP, + WriteXPERM], [GR765UnitALU, GR765UnitIssue]>; +} + +// Integer multiply uses one shared unit and has two-cycle result latency. +let Latency = 2 in { +defm : GR765WriteRes<[WriteIMul, WriteIMul32], + [GR765UnitIMul, GR765UnitIssue]>; +} + +// CLMUL is a two-cycle operation restricted to lane 0. +let Latency = 2, SingleIssue = true in { +def : WriteRes<WriteCLMUL, [GR765UnitCLMUL, GR765UnitIssue0]>; +} + +// AES/SHA has a two-cycle result latency. +def GR765WriteCrypto : SchedWriteRes<[GR765UnitCrypto, GR765UnitIssue]> { + let Latency = 2; +} +def : InstRW<[GR765WriteCrypto], (instregex "^AES(32|64)", "^SHA(256|512)")>; + +// Integer divide/remainder take 35 cycles. 32-bit forms take 19 cycles. +let Latency = 35, ReleaseAtCycles = [35], SingleIssue = true in { +defm : GR765WriteRes<[WriteIDiv, WriteIRem], [GR765UnitIDiv]>; +} +let Latency = 19, ReleaseAtCycles = [19], SingleIssue = true in { +defm : GR765WriteRes<[WriteIDiv32, WriteIRem32], [GR765UnitIDiv]>; +} + +// Integer stores issue through lane 0 with one-cycle latency. +let Latency = 1 in { +defm : GR765WriteRes<[WriteSTB, WriteSTH, WriteSTW, WriteSTD], + [GR765UnitMem, GR765UnitIssue0]>; +} + +// FP stores transfer register data at two-cycle throughput. +let Latency = 1, ReleaseAtCycles = [1, 2, 1], SingleIssue = true in { +defm : GR765WriteRes<[WriteFST16, WriteFST32, WriteFST64], + [GR765UnitMem, GR765UnitFPTransfer, + GR765UnitIssue0]>; +} + +// Integer loads have two-cycle result latency. +let Latency = 2 in { +defm : GR765WriteRes<[WriteLDB, WriteLDH, WriteLDW, WriteLDD], + [GR765UnitMem, GR765UnitIssue0]>; +} + +// The seven-cycle latency for a dependent fld-to-fsd pair. +let Latency = 7, SingleIssue = true in { +defm : GR765WriteRes<[WriteFLD16, WriteFLD32, WriteFLD64], + [GR765UnitMem, GR765UnitIssue0]>; +} + +// Atomic loads and stores have two-cycle latency. +let Latency = 2 in { +defm : GR765WriteRes<[WriteAtomicW, WriteAtomicD, WriteAtomicLDW, + WriteAtomicLDD, WriteAtomicSTW, WriteAtomicSTD], + [GR765UnitMem, GR765UnitIssue0]>; +} + +// Dependent fadd chains take 4 cycles; independent throughput is 1/cycle. +let Latency = 4, SingleIssue = true in { +defm : GR765WriteRes<[WriteFAdd16, WriteFAdd32, WriteFAdd64, + WriteFMinMax16, WriteFMinMax32, WriteFMinMax64], + [GR765UnitFPALU, GR765UnitIssue0]>; + +// FP-result conversions and moves share the four-cycle FP ALU path. +defm : GR765WriteRes<[WriteFCvtI32ToF16, WriteFCvtI32ToF32, + WriteFCvtI32ToF64, WriteFCvtI64ToF16, + WriteFCvtI64ToF32, WriteFCvtI64ToF64, + WriteFCvtF32ToF64, WriteFCvtF64ToF32, + WriteFMovI16ToF16, WriteFMovI32ToF32, + WriteFMovI64ToF64], + [GR765UnitFPALU, GR765UnitIssue0]>; + +// FP rounding and immediate loads share the four-cycle FP ALU path. +defm : GR765WriteRes<[WriteFRoundF16, WriteFRoundF32, WriteFRoundF64, + WriteFLI16, WriteFLI32, WriteFLI64], + [GR765UnitFPALU, GR765UnitIssue0]>; + +// Half/single/double FP conversions share the four-cycle FP ALU path. +defm : GR765WriteRes<[WriteFCvtF16ToF32, WriteFCvtF32ToF16, + WriteFCvtF16ToF64, WriteFCvtF64ToF16], + [GR765UnitFPALU, GR765UnitIssue0]>; +} + +// FP-to-integer operations have 4-cycle latency. +let Latency = 4, ReleaseAtCycles = [1, 4, 1], SingleIssue = true in { +defm : GR765WriteRes<[WriteFCvtF16ToI32, WriteFCvtF16ToI64, + WriteFCvtF32ToI32, WriteFCvtF32ToI64, + WriteFCvtF64ToI32, WriteFCvtF64ToI64, WriteFClass16, + WriteFClass32, WriteFClass64, WriteFCmp16, WriteFCmp32, + WriteFCmp64], + [GR765UnitFPALU, GR765UnitFPToInt, GR765UnitIssue0]>; +} + +// FP sign-injection chains have two-cycle latency. +let Latency = 2, SingleIssue = true in { +defm : GR765WriteRes<[WriteFSGNJ16, WriteFSGNJ32, WriteFSGNJ64], + [GR765UnitFPALU, GR765UnitIssue0]>; +} + +// FP-to-integer bit transfers use the two-cycle transfer path. +let Latency = 2, ReleaseAtCycles = [2, 1], SingleIssue = true in { +defm : GR765WriteRes<[WriteFMovF16ToI16, WriteFMovF32ToI32, + WriteFMovF64ToI64], + [GR765UnitFPTransfer, GR765UnitIssue0]>; +} + +// Dependent FP multiply chains take three cycles. +let Latency = 3, SingleIssue = true in { +defm : GR765WriteRes<[WriteFMul16, WriteFMul32, WriteFMul64], + [GR765UnitFPALU, GR765UnitIssue0]>; +} + +// Dependent fused multiply-add chains take five cycles. +let Latency = 5, SingleIssue = true in { +defm : GR765WriteRes<[WriteFMA16, WriteFMA32, WriteFMA64], + [GR765UnitFPALU, GR765UnitIssue0]>; +} + +let Latency = 17, ReleaseAtCycles = [18, 1], SingleIssue = true in { +defm : GR765WriteRes<[WriteFDiv16, WriteFDiv32, WriteFDiv64], + [GR765UnitFPDivSqrt, GR765UnitIssue0]>; +} +let Latency = 25, ReleaseAtCycles = [26, 1], SingleIssue = true in { +defm : GR765WriteRes<[WriteFSqrt16, WriteFSqrt32, WriteFSqrt64], + [GR765UnitFPDivSqrt, GR765UnitIssue0]>; +} + +def : WriteRes<WriteCSR, [GR765UnitIssue0]>; +def : WriteRes<WriteNop, [GR765UnitIssue]>; + +def : InstRW<[WriteIALU], (instrs COPY)>; + +//===----------------------------------------------------------------------===// +// Bypass and advance +//===----------------------------------------------------------------------===// + +// Late ALU/branch consumers can use results from multi-cycle operations. +defvar GR765LateBypassWrites = [WriteIALU, WriteIALU32, + WriteShiftImm, WriteShiftImm32, + WriteShiftReg, WriteShiftReg32, + WriteSHXADD, WriteSHXADD32, + WriteRotateImm, WriteRotateImm32, + WriteRotateReg, WriteRotateReg32, + WriteCLZ, WriteCLZ32, WriteCTZ, WriteCTZ32, + WriteCPOP, WriteCPOP32, + WriteREV8, WriteORCB, WriteIMinMax, + WriteSingleBit, WriteSingleBitImm, + WriteBEXT, WriteBEXTI, + WriteBREV8, WritePACK, WritePACK32, WriteZIP, + WriteXPERM, + WriteIMul, WriteIMul32, + WriteLDB, WriteLDH, WriteLDW, WriteLDD, + GR765WriteCrypto, + WriteFCvtF16ToI32, WriteFCvtF16ToI64, + WriteFCvtF32ToI32, WriteFCvtF32ToI64, + WriteFCvtF64ToI32, WriteFCvtF64ToI64, + WriteFClass16, WriteFClass32, WriteFClass64, + WriteFCmp16, WriteFCmp32, WriteFCmp64, + WriteFMovF16ToI16, WriteFMovF32ToI32, + WriteFMovF64ToI64]; + +defvar GR765LateBypassReads = [ + ReadJmp, + ReadIALU, ReadIALU32, ReadShiftImm, ReadShiftImm32, + ReadShiftReg, ReadShiftReg32, + ReadSHXADD, ReadSHXADD32, + ReadRotateImm, ReadRotateImm32, ReadRotateReg, ReadRotateReg32, + ReadCLZ, ReadCLZ32, ReadCTZ, ReadCTZ32, ReadCPOP, ReadCPOP32, + ReadREV8, ReadORCB, ReadIMinMax, ReadSingleBit, ReadSingleBitImm, + ReadBREV8, ReadPACK, ReadPACK32, ReadZIP, ReadXPERM +]; + +foreach Read = GR765LateBypassReads in + def : ReadAdvance<Read, 1, GR765LateBypassWrites>; + +// Address generation bypasses ALU results, but not loads or multiplies. +defvar GR765AddrBypassWrites = [ + WriteIALU, WriteIALU32, WriteShiftImm, WriteShiftImm32, + WriteShiftReg, WriteShiftReg32, + WriteSHXADD, WriteSHXADD32, + WriteRotateImm, WriteRotateImm32, WriteRotateReg, WriteRotateReg32, + WriteCLZ, WriteCLZ32, WriteCTZ, WriteCTZ32, WriteCPOP, WriteCPOP32, + WriteREV8, WriteORCB, WriteIMinMax, WriteSingleBit, WriteSingleBitImm, + WriteBEXT, WriteBEXTI, WriteBREV8, WritePACK, WritePACK32, WriteZIP, + WriteXPERM +]; +def : ReadAdvance<ReadMemBase, 1, GR765AddrBypassWrites>; + +// 4 cycles for fld -> fop +defvar GR765FPRConsumerReads = [ + ReadFAdd16, ReadFAdd32, ReadFAdd64, + ReadFMul16, ReadFMul32, ReadFMul64, + ReadFMA16, ReadFMA16Addend, ReadFMA32, ReadFMA32Addend, + ReadFMA64, ReadFMA64Addend, + ReadFDiv16, ReadFDiv32, ReadFDiv64, + ReadFSqrt16, ReadFSqrt32, ReadFSqrt64, + ReadFCmp16, ReadFCmp32, ReadFCmp64, + ReadFSGNJ16, ReadFSGNJ32, ReadFSGNJ64, + ReadFMinMax16, ReadFMinMax32, ReadFMinMax64, + ReadFCvtF16ToI32, ReadFCvtF16ToI64, + ReadFCvtF32ToI32, ReadFCvtF32ToI64, + ReadFCvtF64ToI32, ReadFCvtF64ToI64, + ReadFRoundF16, ReadFRoundF32, ReadFRoundF64, + ReadFCvtF32ToF64, ReadFCvtF64ToF32, + ReadFMovF32ToI32, ReadFMovF64ToI64, + ReadFClass32, ReadFClass64, + ReadFMovF16ToI16, ReadFClass16, + ReadFCvtF16ToF32, ReadFCvtF32ToF16, + ReadFCvtF16ToF64, ReadFCvtF64ToF16 +]; +foreach Read = GR765FPRConsumerReads in + def : ReadAdvance<Read, 3, [WriteFLD16, WriteFLD32, WriteFLD64]>; + +// These operand classes have no modeled bypass or load advance. +defvar GR765NoBypassReads = [ + ReadJalr, ReadCSR, ReadStoreData, + ReadIDiv, ReadIDiv32, ReadIRem, ReadIRem32, ReadIMul, ReadIMul32, + ReadAtomicWA, ReadAtomicWD, ReadAtomicDA, ReadAtomicDD, + ReadAtomicLDW, ReadAtomicLDD, ReadAtomicSTW, ReadAtomicSTD, + ReadFStoreData, ReadFMemBase, + ReadFCvtI32ToF32, ReadFCvtI32ToF64, ReadFCvtI32ToF16, + ReadFCvtI64ToF32, ReadFCvtI64ToF64, ReadFCvtI64ToF16, + ReadFMovI32ToF32, ReadFMovI64ToF64, + ReadCLMUL, + ReadFMovI16ToF16 +]; + +foreach Read = GR765NoBypassReads in + def : ReadAdvance<Read, 0>; + +//===----------------------------------------------------------------------===// +// Unsupported extensions +defm : UnsupportedSchedQ; +defm : UnsupportedSchedV; +defm : UnsupportedSchedZabha; +defm : UnsupportedSchedZfaWithQ; +defm : UnsupportedSchedSFB; +defm : UnsupportedSchedZvk; +defm : UnsupportedSchedXsf; +} >From 3f5c83ce2e449423f42d168016c8a9d12574df9f Mon Sep 17 00:00:00 2001 From: Daniel Cederman <[email protected]> Date: Thu, 24 Sep 2026 17:40:26 +0200 Subject: [PATCH 2/3] [RISCV] Update GR765 processor definition Added gaisler- vendor prefix. Removed scheduling info. Removed privileged extensions. Replaced Zba, Zbb, and Zbs with B. Rewrote extension print test to match other targets. Moved release note to end. Fixed TunePostRAScheduler indention. --- .../riscv-gaisler-gr765.c | 49 +++ .../print-enabled-extensions/riscv-gr765.c | 52 --- clang/test/Driver/riscv-cpus.c | 8 +- .../test/Misc/target-invalid-cpu-note/riscv.c | 4 +- llvm/docs/ReleaseNotes.md | 2 +- llvm/lib/Target/RISCV/RISCV.td | 1 - llvm/lib/Target/RISCV/RISCVProcessors.td | 29 +- llvm/lib/Target/RISCV/RISCVSchedGR765.td | 324 ------------------ 8 files changed, 60 insertions(+), 409 deletions(-) create mode 100644 clang/test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c delete mode 100644 clang/test/Driver/print-enabled-extensions/riscv-gr765.c delete mode 100644 llvm/lib/Target/RISCV/RISCVSchedGR765.td diff --git a/clang/test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c b/clang/test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c new file mode 100644 index 00000000000000..1a191ac677a723 --- /dev/null +++ b/clang/test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c @@ -0,0 +1,49 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang --target=riscv64 -mcpu=gaisler-gr765 --print-enabled-extensions | FileCheck %s +// CHECK: Extensions enabled for the given RISC-V target +// CHECK-EMPTY: +// CHECK-NEXT: Name Version Description +// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set) +// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division) +// CHECK-NEXT: a 2.1 'A' (Atomic Instructions) +// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) +// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) +// CHECK-NEXT: c 2.0 'C' (Compressed Instructions) +// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) +// CHECK-NEXT: h 1.0 'H' (Hypervisor) +// CHECK-NEXT: zic64b 1.0 'Zic64b' (Cache Block Size Is 64 Bytes) +// CHECK-NEXT: zicbom 1.0 'Zicbom' (Cache-Block Management Instructions) +// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) +// CHECK-NEXT: zicntr 2.0 'Zicntr' (Base Counters and Timers) +// CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations) +// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) +// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) +// CHECK-NEXT: zihpm 2.0 'Zihpm' (Hardware Performance Counters) +// CHECK-NEXT: zimop 1.0 'Zimop' (May-Be-Operations) +// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) +// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations) +// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional) +// CHECK-NEXT: zfa 1.0 'Zfa' (Additional Floating-Point) +// CHECK-NEXT: zfbfmin 1.0 'Zfbfmin' (Scalar BF16 Converts) +// CHECK-NEXT: zfh 1.0 'Zfh' (Half-Precision Floating-Point) +// CHECK-NEXT: zfhmin 1.0 'Zfhmin' (Half-Precision Floating-Point Minimal) +// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) +// CHECK-NEXT: zcb 1.0 'Zcb' (Compressed basic bit manipulation instructions) +// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) +// CHECK-NEXT: zcmop 1.0 'Zcmop' (Compressed May-Be-Operations) +// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) +// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) +// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication) +// CHECK-NEXT: zbkb 1.0 'Zbkb' (Bitmanip instructions for Cryptography) +// CHECK-NEXT: zbkc 1.0 'Zbkc' (Carry-less multiply instructions for Cryptography) +// CHECK-NEXT: zbkx 1.0 'Zbkx' (Crossbar permutation instructions) +// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) +// CHECK-NEXT: zkn 1.0 'Zkn' (NIST Algorithm Suite) +// CHECK-NEXT: zknd 1.0 'Zknd' (NIST Suite: AES Decryption) +// CHECK-NEXT: zkne 1.0 'Zkne' (NIST Suite: AES Encryption) +// CHECK-NEXT: zknh 1.0 'Zknh' (NIST Suite: Hash Function Instructions) +// CHECK-NEXT: zkt 1.0 'Zkt' (Data Independent Execution Latency) +// CHECK-EMPTY: +// CHECK-NEXT: Experimental extensions +// CHECK-EMPTY: +// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_h1p0_zic64b1p0_zicbom1p0_zicfiss1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihpm2p0_zimop1p0_zmmul1p0_zaamo1p0_zalrsc1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbc1p0_zbkb1p0_zbkc1p0_zbkx1p0_zbs1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkt1p0 diff --git a/clang/test/Driver/print-enabled-extensions/riscv-gr765.c b/clang/test/Driver/print-enabled-extensions/riscv-gr765.c deleted file mode 100644 index 1ed292e12d6d8a..00000000000000 --- a/clang/test/Driver/print-enabled-extensions/riscv-gr765.c +++ /dev/null @@ -1,52 +0,0 @@ -// REQUIRES: riscv-registered-target -// RUN: %clang --target=riscv64 -mcpu=gr765 --print-enabled-extensions | FileCheck %s - -// CHECK: Extensions enabled for the given RISC-V target -// CHECK: Name{{ *}}Version{{ *}}Description -// CHECK-DAG: i{{ *}}2.1{{ *}}'I' (Base Integer Instruction Set) -// CHECK-DAG: m{{ *}}2.0{{ *}}'M' (Integer Multiplication and Division) -// CHECK-DAG: a{{ *}}2.1{{ *}}'A' (Atomic Instructions) -// CHECK-DAG: f{{ *}}2.2{{ *}}'F' (Single-Precision Floating-Point) -// CHECK-DAG: d{{ *}}2.2{{ *}}'D' (Double-Precision Floating-Point) -// CHECK-DAG: c{{ *}}2.0{{ *}}'C' (Compressed Instructions) -// CHECK-DAG: h{{ *}}1.0{{ *}}'H' (Hypervisor) -// CHECK-DAG: zic64b{{ *}}1.0{{ *}}'Zic64b' (Cache Block Size Is 64 Bytes) -// CHECK-DAG: zicbom{{ *}}1.0{{ *}}'Zicbom' (Cache-Block Management Instructions) -// CHECK-DAG: zicntr{{ *}}2.0{{ *}}'Zicntr' (Base Counters and Timers) -// CHECK-DAG: zicsr{{ *}}2.0{{ *}}'Zicsr' (CSRs) -// CHECK-DAG: zifencei{{ *}}2.0{{ *}}'Zifencei' (fence.i) -// CHECK-DAG: zihpm{{ *}}2.0{{ *}}'Zihpm' (Hardware Performance Counters) -// CHECK-DAG: zba{{ *}}1.0{{ *}}'Zba' (Address Generation Instructions) -// CHECK-DAG: zbb{{ *}}1.0{{ *}}'Zbb' (Basic Bit-Manipulation) -// CHECK-DAG: zbc{{ *}}1.0{{ *}}'Zbc' (Carry-Less Multiplication) -// CHECK-DAG: zbs{{ *}}1.0{{ *}}'Zbs' (Single-Bit Instructions) -// CHECK-DAG: zcb{{ *}}1.0{{ *}}'Zcb' (Compressed basic bit manipulation instructions) -// CHECK-DAG: zcmop{{ *}}1.0{{ *}}'Zcmop' (Compressed May-Be-Operations) -// CHECK-DAG: zfa{{ *}}1.0{{ *}}'Zfa' (Additional Floating-Point) -// CHECK-DAG: zfbfmin{{ *}}1.0{{ *}}'Zfbfmin' (Scalar BF16 Converts) -// CHECK-DAG: zfh{{ *}}1.0{{ *}}'Zfh' (Half-Precision Floating-Point) -// CHECK-DAG: zfhmin{{ *}}1.0{{ *}}'Zfhmin' (Half-Precision Floating-Point Minimal) -// CHECK-DAG: zicfiss{{ *}}1.0{{ *}}'Zicfiss' (Shadow stack) -// CHECK-DAG: zicond{{ *}}1.0{{ *}}'Zicond' (Integer Conditional Operations) -// CHECK-DAG: zimop{{ *}}1.0{{ *}}'Zimop' (May-Be-Operations) -// CHECK-DAG: zkn{{ *}}1.0{{ *}}'Zkn' (NIST Algorithm Suite) -// CHECK-DAG: zkt{{ *}}1.0{{ *}}'Zkt' (Data Independent Execution Latency) -// CHECK-DAG: shlcofideleg{{ *}}1.0{{ *}}'Shlcofideleg' (Delegating LCOFI Interrupts to VS-mode) -// CHECK-DAG: smaia{{ *}}1.0{{ *}}'Smaia' (Advanced Interrupt Architecture Machine Level) -// CHECK-DAG: smcdeleg{{ *}}1.0{{ *}}'Smcdeleg' (Counter Delegation Machine Level) -// CHECK-DAG: smcntrpmf{{ *}}1.0{{ *}}'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering) -// CHECK-DAG: smcsrind{{ *}}1.0{{ *}}'Smcsrind' (Indirect CSR Access Machine Level) -// CHECK-DAG: ssaia{{ *}}1.0{{ *}}'Ssaia' (Advanced Interrupt Architecture Supervisor Level) -// CHECK-DAG: smdbltrp{{ *}}1.0{{ *}}'Smdbltrp' (Double Trap Machine Level) -// CHECK-DAG: smepmp{{ *}}1.0{{ *}}'Smepmp' (Enhanced Physical Memory Protection) -// CHECK-DAG: smrnmi{{ *}}1.0{{ *}}'Smrnmi' (Resumable Non-Maskable Interrupts) -// CHECK-DAG: smstateen{{ *}}1.0{{ *}}'Smstateen' (Machine-mode view of the state-enable extension) -// CHECK-DAG: sscofpmf{{ *}}1.0{{ *}}'Sscofpmf' (Count Overflow and Mode-Based Filtering) -// CHECK-DAG: sscsrind{{ *}}1.0{{ *}}'Sscsrind' (Indirect CSR Access Supervisor Level) -// CHECK-DAG: ssdbltrp{{ *}}1.0{{ *}}'Ssdbltrp' (Double Trap Supervisor Level) -// CHECK-DAG: sstc{{ *}}1.0{{ *}}'Sstc' (Supervisor-mode timer interrupts) -// CHECK-DAG: svadu{{ *}}1.0{{ *}}'Svadu' (Hardware A/D updates) -// CHECK-DAG: svinval{{ *}}1.0{{ *}}'Svinval' (Fine-Grained Address-Translation Cache Invalidation) -// CHECK-DAG: svnapot{{ *}}1.0{{ *}}'Svnapot' (NAPOT Translation Contiguity) -// CHECK-DAG: svpbmt{{ *}}1.0{{ *}}'Svpbmt' (Page-Based Memory Types) -// CHECK-DAG: svrsw60t59b{{ *}}1.0{{ *}}'Svrsw60t59b' (PTE Reserved-for-Software Bits 60-59) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 4fca57da88d333..9cfe399ca71a7a 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -762,7 +762,7 @@ // MCPU-XT-C920V2: "-target-cpu" "xt-c920v2" // MCPU-XT-C920V2-SAME: "-target-abi" "lp64d" -// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=gr765 | FileCheck -check-prefix=MCPU-GR765 %s -// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-gr765.c` -// MCPU-GR765: "-target-cpu" "gr765" -// MCPU-GR765-SAME: "-target-abi" "lp64d" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=gaisler-gr765 | FileCheck -check-prefix=MCPU-GAISLER-GR765 %s +// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c` +// MCPU-GAISLER-GR765: "-target-cpu" "gaisler-gr765" +// MCPU-GAISLER-GR765-SAME: "-target-abi" "lp64d" diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c index 9eb07b49e72bc8..86fdf400ac4611 100644 --- a/clang/test/Misc/target-invalid-cpu-note/riscv.c +++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c @@ -34,7 +34,7 @@ // RISCV64-SAME: {{^}}, andes-ax45mpv // RISCV64-SAME: {{^}}, andes-nx45 // RISCV64-SAME: {{^}}, et-soc1 -// RISCV64-SAME: {{^}}, gr765 +// RISCV64-SAME: {{^}}, gaisler-gr765 // RISCV64-SAME: {{^}}, generic-rv64 // RISCV64-SAME: {{^}}, mips-p8700 // RISCV64-SAME: {{^}}, rocket-rv64 @@ -103,7 +103,7 @@ // TUNE-RISCV64-SAME: {{^}}, andes-ax45mpv // TUNE-RISCV64-SAME: {{^}}, andes-nx45 // TUNE-RISCV64-SAME: {{^}}, et-soc1 -// TUNE-RISCV64-SAME: {{^}}, gr765 +// TUNE-RISCV64-SAME: {{^}}, gaisler-gr765 // TUNE-RISCV64-SAME: {{^}}, generic-rv64 // TUNE-RISCV64-SAME: {{^}}, mips-p8700 // TUNE-RISCV64-SAME: {{^}}, rocket-rv64 diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 952c7269690261..2436928450f4f5 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -256,7 +256,6 @@ Makes programs 10x faster by doing Special New Thing. * Added experimental MC support for the ACLIC v0.20 extensions: `Smidctrl`, `Ssidctrl`, `Smnip`, `Ssnip`, `Smijt`, `Ssijt`, `Smehv`, `Ssehv`, `Smcsps`, `Sscsps`, `Smip`, and `Ssip`. -* Added `-mcpu=gr765` for the 64-bit GR765 processor. * Adds experimental assembler/CodeGen support for the `Zilx` (Indexed Integer Load) extension. * Bump Svukte extension to 1.0. @@ -271,6 +270,7 @@ Makes programs 10x faster by doing Special New Thing. * Updated the canonical order of one-letter RISC-V extensions to match the latest specification, placing ``p`` after ``v`` and removing unused ``n``. * Adds experimental assembler support for the `Xqccmi` (Qualcomm 16-bit Instruction Lookup Table) vendor extension. +* Added `-mcpu=gaisler-gr765` for the 64-bit GR765 processor. ### Changes to the WebAssembly Backend diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 865f36313d52c0..945a1e69359fc8 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -53,7 +53,6 @@ include "RISCVMacroFusion.td" //===----------------------------------------------------------------------===// include "RISCVSchedAndes45.td" include "RISCVSchedGenericOOO.td" -include "RISCVSchedGR765.td" include "RISCVSchedMIPSP8700.td" include "RISCVSchedRocket.td" include "RISCVSchedSiFive7.td" diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 7c14e4ca6e3992..24388790b2ff00 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -1107,8 +1107,8 @@ def XUANTIE_C920V2 : RISCVProcessorModel<"xt-c920v2", [TuneVXRMPipelineFlush, TunePostRAScheduler]>; -def GAISLER_GR765 : RISCVProcessorModel<"gr765", - GR765Model, +def GAISLER_GR765 : RISCVProcessorModel<"gaisler-gr765", + NoSchedModel, [Feature64Bit, FeatureStdExtI, FeatureStdExtZifencei, @@ -1120,30 +1120,9 @@ def GAISLER_GR765 : RISCVProcessorModel<"gr765", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, + FeatureStdExtB, FeatureStdExtH, - FeatureStdExtShlcofideleg, - FeatureStdExtSmaia, - FeatureStdExtSmcdeleg, - FeatureStdExtSmcntrpmf, - FeatureStdExtSmcsrind, - FeatureStdExtSsaia, - FeatureStdExtSmdbltrp, - FeatureStdExtSmepmp, - FeatureStdExtSmrnmi, - FeatureStdExtSmstateen, - FeatureStdExtSscofpmf, - FeatureStdExtSscsrind, - FeatureStdExtSsdbltrp, - FeatureStdExtSstc, - FeatureStdExtSvadu, - FeatureStdExtSvinval, - FeatureStdExtSvnapot, - FeatureStdExtSvpbmt, - FeatureStdExtSvrsw60t59b, - FeatureStdExtZba, - FeatureStdExtZbb, FeatureStdExtZbc, - FeatureStdExtZbs, FeatureStdExtZcb, FeatureStdExtZcmop, FeatureStdExtZfa, @@ -1157,6 +1136,6 @@ def GAISLER_GR765 : RISCVProcessorModel<"gr765", FeatureStdExtZimop, FeatureStdExtZkn, FeatureStdExtZkt], - [TunePostRAScheduler]>; + [TunePostRAScheduler]>; // clang-format on diff --git a/llvm/lib/Target/RISCV/RISCVSchedGR765.td b/llvm/lib/Target/RISCV/RISCVSchedGR765.td deleted file mode 100644 index f1ec1ef2605b58..00000000000000 --- a/llvm/lib/Target/RISCV/RISCVSchedGR765.td +++ /dev/null @@ -1,324 +0,0 @@ -//===-- RISCVSchedGR765.td - GR765 Scheduling Definitions -*- tablegen -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// Scheduling model for the GR765 RISCV-V configuration. -// -// Timing is taken from the GR765 Data Sheet User's Manual. -// -//===----------------------------------------------------------------------===// - -def GR765Model : SchedMachineModel { - // In-order dual-issue pipeline - let MicroOpBufferSize = 0; - let IssueWidth = 2; - let LoadLatency = 2; - let MispredictPenalty = 3; - let CompleteModel = false; - let UnsupportedFeatures = [HasStdExtZcmt, HasStdExtZksed, HasStdExtZksh, - HasVInstructions, HasVInstructionsI64, - HasStdExtZkr]; -} - -//===----------------------------------------------------------------------===// -// Processor resources -//===----------------------------------------------------------------------===// - -let BufferSize = 0 in { -def GR765UnitALU : ProcResource<2>; // Int ALUs -def GR765UnitIMul : ProcResource<1>; // Int Multiply -def GR765UnitMem : ProcResource<1>; // Load/Store -def GR765UnitB : ProcResource<1>; // Branch -def GR765UnitIssue0 : ProcResource<1>; // Lane 0 issue slot -def GR765UnitIssue1 : ProcResource<1>; // Lane 1 issue slot -def GR765UnitCLMUL : ProcResource<1>; // Carry-less multiply -def GR765UnitCrypto : ProcResource<1>; // AES / SHA unit - -def GR765UnitFPALU : ProcResource<1>; // FP FPR-result path -def GR765UnitFPTransfer : ProcResource<1>; // FP binary data transfer -def GR765UnitFPToInt : ProcResource<1>; // FP result to integer pipeline -} - -let BufferSize = 1 in { -def GR765UnitIDiv : ProcResource<1>; // Int Division -def GR765UnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt -} - -//===----------------------------------------------------------------------===// - -let SchedModel = GR765Model in { - -// Instructions may use either issue lane unless their class restricts it. -def GR765UnitIssue : ProcResGroup<[GR765UnitIssue0, GR765UnitIssue1]>; - -// Map scheduling writes with identical resource requirements. -multiclass GR765WriteRes<list<SchedWrite> Writes, - list<ProcResourceKind> Resources> { - foreach W = Writes in - def : WriteRes<W, Resources>; -} - -// Conditional branches issue in lane 1. JAL/JALR are single-issue. -let Latency = 2 in { -def : WriteRes<WriteJmp, [GR765UnitB, GR765UnitIssue1]>; -def : WriteRes<WriteJal, [GR765UnitB]> { let SingleIssue = true; } -def : WriteRes<WriteJalr, [GR765UnitB]> { let SingleIssue = true; } -} - -// Integer ALU results take two cycles except through the bypasses below. -let Latency = 2 in { -defm : GR765WriteRes<[WriteIALU32, WriteIALU, WriteShiftImm32, - WriteShiftImm, WriteShiftReg32, WriteShiftReg, - WriteSHXADD, WriteSHXADD32, WriteRotateImm, - WriteRotateImm32, WriteRotateReg, WriteRotateReg32, - WriteCLZ, WriteCLZ32, WriteCTZ, WriteCTZ32, WriteCPOP, - WriteCPOP32, WriteREV8, WriteORCB, WriteIMinMax, - WriteSingleBit, WriteSingleBitImm, WriteBEXT, - WriteBEXTI, WriteBREV8, WritePACK, WritePACK32, WriteZIP, - WriteXPERM], [GR765UnitALU, GR765UnitIssue]>; -} - -// Integer multiply uses one shared unit and has two-cycle result latency. -let Latency = 2 in { -defm : GR765WriteRes<[WriteIMul, WriteIMul32], - [GR765UnitIMul, GR765UnitIssue]>; -} - -// CLMUL is a two-cycle operation restricted to lane 0. -let Latency = 2, SingleIssue = true in { -def : WriteRes<WriteCLMUL, [GR765UnitCLMUL, GR765UnitIssue0]>; -} - -// AES/SHA has a two-cycle result latency. -def GR765WriteCrypto : SchedWriteRes<[GR765UnitCrypto, GR765UnitIssue]> { - let Latency = 2; -} -def : InstRW<[GR765WriteCrypto], (instregex "^AES(32|64)", "^SHA(256|512)")>; - -// Integer divide/remainder take 35 cycles. 32-bit forms take 19 cycles. -let Latency = 35, ReleaseAtCycles = [35], SingleIssue = true in { -defm : GR765WriteRes<[WriteIDiv, WriteIRem], [GR765UnitIDiv]>; -} -let Latency = 19, ReleaseAtCycles = [19], SingleIssue = true in { -defm : GR765WriteRes<[WriteIDiv32, WriteIRem32], [GR765UnitIDiv]>; -} - -// Integer stores issue through lane 0 with one-cycle latency. -let Latency = 1 in { -defm : GR765WriteRes<[WriteSTB, WriteSTH, WriteSTW, WriteSTD], - [GR765UnitMem, GR765UnitIssue0]>; -} - -// FP stores transfer register data at two-cycle throughput. -let Latency = 1, ReleaseAtCycles = [1, 2, 1], SingleIssue = true in { -defm : GR765WriteRes<[WriteFST16, WriteFST32, WriteFST64], - [GR765UnitMem, GR765UnitFPTransfer, - GR765UnitIssue0]>; -} - -// Integer loads have two-cycle result latency. -let Latency = 2 in { -defm : GR765WriteRes<[WriteLDB, WriteLDH, WriteLDW, WriteLDD], - [GR765UnitMem, GR765UnitIssue0]>; -} - -// The seven-cycle latency for a dependent fld-to-fsd pair. -let Latency = 7, SingleIssue = true in { -defm : GR765WriteRes<[WriteFLD16, WriteFLD32, WriteFLD64], - [GR765UnitMem, GR765UnitIssue0]>; -} - -// Atomic loads and stores have two-cycle latency. -let Latency = 2 in { -defm : GR765WriteRes<[WriteAtomicW, WriteAtomicD, WriteAtomicLDW, - WriteAtomicLDD, WriteAtomicSTW, WriteAtomicSTD], - [GR765UnitMem, GR765UnitIssue0]>; -} - -// Dependent fadd chains take 4 cycles; independent throughput is 1/cycle. -let Latency = 4, SingleIssue = true in { -defm : GR765WriteRes<[WriteFAdd16, WriteFAdd32, WriteFAdd64, - WriteFMinMax16, WriteFMinMax32, WriteFMinMax64], - [GR765UnitFPALU, GR765UnitIssue0]>; - -// FP-result conversions and moves share the four-cycle FP ALU path. -defm : GR765WriteRes<[WriteFCvtI32ToF16, WriteFCvtI32ToF32, - WriteFCvtI32ToF64, WriteFCvtI64ToF16, - WriteFCvtI64ToF32, WriteFCvtI64ToF64, - WriteFCvtF32ToF64, WriteFCvtF64ToF32, - WriteFMovI16ToF16, WriteFMovI32ToF32, - WriteFMovI64ToF64], - [GR765UnitFPALU, GR765UnitIssue0]>; - -// FP rounding and immediate loads share the four-cycle FP ALU path. -defm : GR765WriteRes<[WriteFRoundF16, WriteFRoundF32, WriteFRoundF64, - WriteFLI16, WriteFLI32, WriteFLI64], - [GR765UnitFPALU, GR765UnitIssue0]>; - -// Half/single/double FP conversions share the four-cycle FP ALU path. -defm : GR765WriteRes<[WriteFCvtF16ToF32, WriteFCvtF32ToF16, - WriteFCvtF16ToF64, WriteFCvtF64ToF16], - [GR765UnitFPALU, GR765UnitIssue0]>; -} - -// FP-to-integer operations have 4-cycle latency. -let Latency = 4, ReleaseAtCycles = [1, 4, 1], SingleIssue = true in { -defm : GR765WriteRes<[WriteFCvtF16ToI32, WriteFCvtF16ToI64, - WriteFCvtF32ToI32, WriteFCvtF32ToI64, - WriteFCvtF64ToI32, WriteFCvtF64ToI64, WriteFClass16, - WriteFClass32, WriteFClass64, WriteFCmp16, WriteFCmp32, - WriteFCmp64], - [GR765UnitFPALU, GR765UnitFPToInt, GR765UnitIssue0]>; -} - -// FP sign-injection chains have two-cycle latency. -let Latency = 2, SingleIssue = true in { -defm : GR765WriteRes<[WriteFSGNJ16, WriteFSGNJ32, WriteFSGNJ64], - [GR765UnitFPALU, GR765UnitIssue0]>; -} - -// FP-to-integer bit transfers use the two-cycle transfer path. -let Latency = 2, ReleaseAtCycles = [2, 1], SingleIssue = true in { -defm : GR765WriteRes<[WriteFMovF16ToI16, WriteFMovF32ToI32, - WriteFMovF64ToI64], - [GR765UnitFPTransfer, GR765UnitIssue0]>; -} - -// Dependent FP multiply chains take three cycles. -let Latency = 3, SingleIssue = true in { -defm : GR765WriteRes<[WriteFMul16, WriteFMul32, WriteFMul64], - [GR765UnitFPALU, GR765UnitIssue0]>; -} - -// Dependent fused multiply-add chains take five cycles. -let Latency = 5, SingleIssue = true in { -defm : GR765WriteRes<[WriteFMA16, WriteFMA32, WriteFMA64], - [GR765UnitFPALU, GR765UnitIssue0]>; -} - -let Latency = 17, ReleaseAtCycles = [18, 1], SingleIssue = true in { -defm : GR765WriteRes<[WriteFDiv16, WriteFDiv32, WriteFDiv64], - [GR765UnitFPDivSqrt, GR765UnitIssue0]>; -} -let Latency = 25, ReleaseAtCycles = [26, 1], SingleIssue = true in { -defm : GR765WriteRes<[WriteFSqrt16, WriteFSqrt32, WriteFSqrt64], - [GR765UnitFPDivSqrt, GR765UnitIssue0]>; -} - -def : WriteRes<WriteCSR, [GR765UnitIssue0]>; -def : WriteRes<WriteNop, [GR765UnitIssue]>; - -def : InstRW<[WriteIALU], (instrs COPY)>; - -//===----------------------------------------------------------------------===// -// Bypass and advance -//===----------------------------------------------------------------------===// - -// Late ALU/branch consumers can use results from multi-cycle operations. -defvar GR765LateBypassWrites = [WriteIALU, WriteIALU32, - WriteShiftImm, WriteShiftImm32, - WriteShiftReg, WriteShiftReg32, - WriteSHXADD, WriteSHXADD32, - WriteRotateImm, WriteRotateImm32, - WriteRotateReg, WriteRotateReg32, - WriteCLZ, WriteCLZ32, WriteCTZ, WriteCTZ32, - WriteCPOP, WriteCPOP32, - WriteREV8, WriteORCB, WriteIMinMax, - WriteSingleBit, WriteSingleBitImm, - WriteBEXT, WriteBEXTI, - WriteBREV8, WritePACK, WritePACK32, WriteZIP, - WriteXPERM, - WriteIMul, WriteIMul32, - WriteLDB, WriteLDH, WriteLDW, WriteLDD, - GR765WriteCrypto, - WriteFCvtF16ToI32, WriteFCvtF16ToI64, - WriteFCvtF32ToI32, WriteFCvtF32ToI64, - WriteFCvtF64ToI32, WriteFCvtF64ToI64, - WriteFClass16, WriteFClass32, WriteFClass64, - WriteFCmp16, WriteFCmp32, WriteFCmp64, - WriteFMovF16ToI16, WriteFMovF32ToI32, - WriteFMovF64ToI64]; - -defvar GR765LateBypassReads = [ - ReadJmp, - ReadIALU, ReadIALU32, ReadShiftImm, ReadShiftImm32, - ReadShiftReg, ReadShiftReg32, - ReadSHXADD, ReadSHXADD32, - ReadRotateImm, ReadRotateImm32, ReadRotateReg, ReadRotateReg32, - ReadCLZ, ReadCLZ32, ReadCTZ, ReadCTZ32, ReadCPOP, ReadCPOP32, - ReadREV8, ReadORCB, ReadIMinMax, ReadSingleBit, ReadSingleBitImm, - ReadBREV8, ReadPACK, ReadPACK32, ReadZIP, ReadXPERM -]; - -foreach Read = GR765LateBypassReads in - def : ReadAdvance<Read, 1, GR765LateBypassWrites>; - -// Address generation bypasses ALU results, but not loads or multiplies. -defvar GR765AddrBypassWrites = [ - WriteIALU, WriteIALU32, WriteShiftImm, WriteShiftImm32, - WriteShiftReg, WriteShiftReg32, - WriteSHXADD, WriteSHXADD32, - WriteRotateImm, WriteRotateImm32, WriteRotateReg, WriteRotateReg32, - WriteCLZ, WriteCLZ32, WriteCTZ, WriteCTZ32, WriteCPOP, WriteCPOP32, - WriteREV8, WriteORCB, WriteIMinMax, WriteSingleBit, WriteSingleBitImm, - WriteBEXT, WriteBEXTI, WriteBREV8, WritePACK, WritePACK32, WriteZIP, - WriteXPERM -]; -def : ReadAdvance<ReadMemBase, 1, GR765AddrBypassWrites>; - -// 4 cycles for fld -> fop -defvar GR765FPRConsumerReads = [ - ReadFAdd16, ReadFAdd32, ReadFAdd64, - ReadFMul16, ReadFMul32, ReadFMul64, - ReadFMA16, ReadFMA16Addend, ReadFMA32, ReadFMA32Addend, - ReadFMA64, ReadFMA64Addend, - ReadFDiv16, ReadFDiv32, ReadFDiv64, - ReadFSqrt16, ReadFSqrt32, ReadFSqrt64, - ReadFCmp16, ReadFCmp32, ReadFCmp64, - ReadFSGNJ16, ReadFSGNJ32, ReadFSGNJ64, - ReadFMinMax16, ReadFMinMax32, ReadFMinMax64, - ReadFCvtF16ToI32, ReadFCvtF16ToI64, - ReadFCvtF32ToI32, ReadFCvtF32ToI64, - ReadFCvtF64ToI32, ReadFCvtF64ToI64, - ReadFRoundF16, ReadFRoundF32, ReadFRoundF64, - ReadFCvtF32ToF64, ReadFCvtF64ToF32, - ReadFMovF32ToI32, ReadFMovF64ToI64, - ReadFClass32, ReadFClass64, - ReadFMovF16ToI16, ReadFClass16, - ReadFCvtF16ToF32, ReadFCvtF32ToF16, - ReadFCvtF16ToF64, ReadFCvtF64ToF16 -]; -foreach Read = GR765FPRConsumerReads in - def : ReadAdvance<Read, 3, [WriteFLD16, WriteFLD32, WriteFLD64]>; - -// These operand classes have no modeled bypass or load advance. -defvar GR765NoBypassReads = [ - ReadJalr, ReadCSR, ReadStoreData, - ReadIDiv, ReadIDiv32, ReadIRem, ReadIRem32, ReadIMul, ReadIMul32, - ReadAtomicWA, ReadAtomicWD, ReadAtomicDA, ReadAtomicDD, - ReadAtomicLDW, ReadAtomicLDD, ReadAtomicSTW, ReadAtomicSTD, - ReadFStoreData, ReadFMemBase, - ReadFCvtI32ToF32, ReadFCvtI32ToF64, ReadFCvtI32ToF16, - ReadFCvtI64ToF32, ReadFCvtI64ToF64, ReadFCvtI64ToF16, - ReadFMovI32ToF32, ReadFMovI64ToF64, - ReadCLMUL, - ReadFMovI16ToF16 -]; - -foreach Read = GR765NoBypassReads in - def : ReadAdvance<Read, 0>; - -//===----------------------------------------------------------------------===// -// Unsupported extensions -defm : UnsupportedSchedQ; -defm : UnsupportedSchedV; -defm : UnsupportedSchedZabha; -defm : UnsupportedSchedZfaWithQ; -defm : UnsupportedSchedSFB; -defm : UnsupportedSchedZvk; -defm : UnsupportedSchedXsf; -} >From e4e4bd9fc5c2dde7c5a50c2563f45bc29ea7f01e Mon Sep 17 00:00:00 2001 From: Daniel Cederman <[email protected]> Date: Fri, 25 Sep 2026 09:03:01 +0200 Subject: [PATCH 3/3] [RISCV] Remove H extension from GR765 --- .../test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c | 3 +-- llvm/lib/Target/RISCV/RISCVProcessors.td | 1 - 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/clang/test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c b/clang/test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c index 1a191ac677a723..fac9d18808f9eb 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c @@ -10,7 +10,6 @@ // CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) // CHECK-NEXT: c 2.0 'C' (Compressed Instructions) // CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) -// CHECK-NEXT: h 1.0 'H' (Hypervisor) // CHECK-NEXT: zic64b 1.0 'Zic64b' (Cache Block Size Is 64 Bytes) // CHECK-NEXT: zicbom 1.0 'Zicbom' (Cache-Block Management Instructions) // CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) @@ -46,4 +45,4 @@ // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions // CHECK-EMPTY: -// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_h1p0_zic64b1p0_zicbom1p0_zicfiss1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihpm2p0_zimop1p0_zmmul1p0_zaamo1p0_zalrsc1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbc1p0_zbkb1p0_zbkc1p0_zbkx1p0_zbs1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkt1p0 +// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicfiss1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihpm2p0_zimop1p0_zmmul1p0_zaamo1p0_zalrsc1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbc1p0_zbkb1p0_zbkc1p0_zbkx1p0_zbs1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkt1p0 diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 24388790b2ff00..50b48ce244d75f 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -1121,7 +1121,6 @@ def GAISLER_GR765 : RISCVProcessorModel<"gaisler-gr765", FeatureStdExtD, FeatureStdExtC, FeatureStdExtB, - FeatureStdExtH, FeatureStdExtZbc, FeatureStdExtZcb, FeatureStdExtZcmop, _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
