Author: Daniel Cederman Date: 2026-09-25T08:10:05Z New Revision: fe1f8494628afdd4252fc607d7bccafa2fb64b35
URL: https://github.com/llvm/llvm-project/commit/fe1f8494628afdd4252fc607d7bccafa2fb64b35 DIFF: https://github.com/llvm/llvm-project/commit/fe1f8494628afdd4252fc607d7bccafa2fb64b35.diff LOG: [RISCV] Add processor definition for GR765 (#225638) Add support for the GR765 processor from Frontgrade Gaisler. https://www.gaisler.com/products/gr765 Assisted-by: Codex Added: clang/test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c Modified: clang/test/Driver/riscv-cpus.c clang/test/Misc/target-invalid-cpu-note/riscv.c llvm/docs/ReleaseNotes.md llvm/lib/Target/RISCV/RISCVProcessors.td Removed: ################################################################################ diff --git a/clang/test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c b/clang/test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c new file mode 100644 index 00000000000000..fac9d18808f9eb --- /dev/null +++ b/clang/test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c @@ -0,0 +1,48 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang --target=riscv64 -mcpu=gaisler-gr765 --print-enabled-extensions | FileCheck %s +// CHECK: Extensions enabled for the given RISC-V target +// CHECK-EMPTY: +// CHECK-NEXT: Name Version Description +// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set) +// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division) +// CHECK-NEXT: a 2.1 'A' (Atomic Instructions) +// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) +// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) +// CHECK-NEXT: c 2.0 'C' (Compressed Instructions) +// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) +// CHECK-NEXT: zic64b 1.0 'Zic64b' (Cache Block Size Is 64 Bytes) +// CHECK-NEXT: zicbom 1.0 'Zicbom' (Cache-Block Management Instructions) +// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) +// CHECK-NEXT: zicntr 2.0 'Zicntr' (Base Counters and Timers) +// CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations) +// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) +// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) +// CHECK-NEXT: zihpm 2.0 'Zihpm' (Hardware Performance Counters) +// CHECK-NEXT: zimop 1.0 'Zimop' (May-Be-Operations) +// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) +// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations) +// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional) +// CHECK-NEXT: zfa 1.0 'Zfa' (Additional Floating-Point) +// CHECK-NEXT: zfbfmin 1.0 'Zfbfmin' (Scalar BF16 Converts) +// CHECK-NEXT: zfh 1.0 'Zfh' (Half-Precision Floating-Point) +// CHECK-NEXT: zfhmin 1.0 'Zfhmin' (Half-Precision Floating-Point Minimal) +// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) +// CHECK-NEXT: zcb 1.0 'Zcb' (Compressed basic bit manipulation instructions) +// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) +// CHECK-NEXT: zcmop 1.0 'Zcmop' (Compressed May-Be-Operations) +// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) +// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) +// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication) +// CHECK-NEXT: zbkb 1.0 'Zbkb' (Bitmanip instructions for Cryptography) +// CHECK-NEXT: zbkc 1.0 'Zbkc' (Carry-less multiply instructions for Cryptography) +// CHECK-NEXT: zbkx 1.0 'Zbkx' (Crossbar permutation instructions) +// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) +// CHECK-NEXT: zkn 1.0 'Zkn' (NIST Algorithm Suite) +// CHECK-NEXT: zknd 1.0 'Zknd' (NIST Suite: AES Decryption) +// CHECK-NEXT: zkne 1.0 'Zkne' (NIST Suite: AES Encryption) +// CHECK-NEXT: zknh 1.0 'Zknh' (NIST Suite: Hash Function Instructions) +// CHECK-NEXT: zkt 1.0 'Zkt' (Data Independent Execution Latency) +// CHECK-EMPTY: +// CHECK-NEXT: Experimental extensions +// CHECK-EMPTY: +// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicfiss1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihpm2p0_zimop1p0_zmmul1p0_zaamo1p0_zalrsc1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbc1p0_zbkb1p0_zbkc1p0_zbkx1p0_zbs1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkt1p0 diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 50d7ab7ab51b90..9cfe399ca71a7a 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -761,3 +761,8 @@ // COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-xt-c920v2.c` // MCPU-XT-C920V2: "-target-cpu" "xt-c920v2" // MCPU-XT-C920V2-SAME: "-target-abi" "lp64d" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=gaisler-gr765 | FileCheck -check-prefix=MCPU-GAISLER-GR765 %s +// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c` +// MCPU-GAISLER-GR765: "-target-cpu" "gaisler-gr765" +// MCPU-GAISLER-GR765-SAME: "-target-abi" "lp64d" diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c index 546dbbdb7e0434..86fdf400ac4611 100644 --- a/clang/test/Misc/target-invalid-cpu-note/riscv.c +++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c @@ -34,6 +34,7 @@ // RISCV64-SAME: {{^}}, andes-ax45mpv // RISCV64-SAME: {{^}}, andes-nx45 // RISCV64-SAME: {{^}}, et-soc1 +// RISCV64-SAME: {{^}}, gaisler-gr765 // RISCV64-SAME: {{^}}, generic-rv64 // RISCV64-SAME: {{^}}, mips-p8700 // RISCV64-SAME: {{^}}, rocket-rv64 @@ -102,6 +103,7 @@ // TUNE-RISCV64-SAME: {{^}}, andes-ax45mpv // TUNE-RISCV64-SAME: {{^}}, andes-nx45 // TUNE-RISCV64-SAME: {{^}}, et-soc1 +// TUNE-RISCV64-SAME: {{^}}, gaisler-gr765 // TUNE-RISCV64-SAME: {{^}}, generic-rv64 // TUNE-RISCV64-SAME: {{^}}, mips-p8700 // TUNE-RISCV64-SAME: {{^}}, rocket-rv64 diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 316ca56adb01b2..76dc3e44c6edd1 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -284,6 +284,7 @@ Makes programs 10x faster by doing Special New Thing. * Updated the canonical order of one-letter RISC-V extensions to match the latest specification, placing ``p`` after ``v`` and removing unused ``n``. * Adds experimental assembler support for the `Xqccmi` (Qualcomm 16-bit Instruction Lookup Table) vendor extension. +* Added `-mcpu=gaisler-gr765` for the 64-bit GR765 processor. ### Changes to the WebAssembly Backend diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 48150f7d4dddfb..50b48ce244d75f 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -1106,4 +1106,35 @@ def XUANTIE_C920V2 : RISCVProcessorModel<"xt-c920v2", FeatureUnalignedScalarMem]), [TuneVXRMPipelineFlush, TunePostRAScheduler]>; + +def GAISLER_GR765 : RISCVProcessorModel<"gaisler-gr765", + NoSchedModel, + [Feature64Bit, + FeatureStdExtI, + FeatureStdExtZifencei, + FeatureStdExtZicsr, + FeatureStdExtZicntr, + FeatureStdExtZihpm, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtB, + FeatureStdExtZbc, + FeatureStdExtZcb, + FeatureStdExtZcmop, + FeatureStdExtZfa, + FeatureStdExtZfbfmin, + FeatureStdExtZfh, + FeatureStdExtZfhmin, + FeatureStdExtZic64b, + FeatureStdExtZicbom, + FeatureStdExtZicfiss, + FeatureStdExtZicond, + FeatureStdExtZimop, + FeatureStdExtZkn, + FeatureStdExtZkt], + [TunePostRAScheduler]>; + // clang-format on _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
