https://github.com/Fznamznon updated https://github.com/llvm/llvm-project/pull/226972
>From 0eab6ffbf10bfc8f5a9cdabe1dd2853d35ae0a42 Mon Sep 17 00:00:00 2001 From: Mariya Podchishchaeva <[email protected]> Date: Mon, 28 Sep 2026 07:27:21 -0500 Subject: [PATCH] [CIR][NFC][AMDGPU] Use new triple in CIR tests --- clang/test/CIR/CodeGen/builtin-memcpy.c | 6 +++--- .../CIR/CodeGenCUDA/uniform-work-group-size.cu | 18 +++++++++--------- clang/test/CIR/CodeGenHIP/atomic-classify.hip | 4 ++-- .../CIR/CodeGenHIP/builtin-bool-result.hip | 6 +++--- .../CIR/CodeGenHIP/builtins-amdgcn-wave32.hip | 12 ++++++------ .../CIR/CodeGenHIP/builtins-amdgcn-wave64.hip | 12 ++++++------ .../CodeGenHIP/cleanup-alloca-addrspace.hip | 4 ++-- .../CodeGenHIP/ternary-struct-addrspace.hip | 2 +- 8 files changed, 32 insertions(+), 32 deletions(-) diff --git a/clang/test/CIR/CodeGen/builtin-memcpy.c b/clang/test/CIR/CodeGen/builtin-memcpy.c index 4e3853a8f711a..b3c94703b1f75 100644 --- a/clang/test/CIR/CodeGen/builtin-memcpy.c +++ b/clang/test/CIR/CodeGen/builtin-memcpy.c @@ -1,9 +1,9 @@ // RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir -o - %s | FileCheck %s --check-prefix=CIR // RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm -o - %s | FileCheck %s --check-prefix=LLVM // RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s --check-prefix=LLVM -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -fclangir -emit-cir -o - %s | FileCheck %s --check-prefix=CIR -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -fclangir -emit-llvm -o - %s | FileCheck %s --check-prefix=LLVM -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -emit-llvm -o - %s | FileCheck %s --check-prefix=LLVM +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -fclangir -emit-cir -o - %s | FileCheck %s --check-prefix=CIR +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -fclangir -emit-llvm -o - %s | FileCheck %s --check-prefix=LLVM +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -emit-llvm -o - %s | FileCheck %s --check-prefix=LLVM typedef unsigned long size_t; diff --git a/clang/test/CIR/CodeGenCUDA/uniform-work-group-size.cu b/clang/test/CIR/CodeGenCUDA/uniform-work-group-size.cu index 86e47e52dfc7c..6d2ac3cde8dd4 100644 --- a/clang/test/CIR/CodeGenCUDA/uniform-work-group-size.cu +++ b/clang/test/CIR/CodeGenCUDA/uniform-work-group-size.cu @@ -6,34 +6,34 @@ // attribute, so it lands on every function and every call site. It defaults to // on for CUDA/HIP. -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -fcuda-is-device \ +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -x hip -fcuda-is-device \ // RUN: -fclangir -emit-cir %s -o %t.cir // RUN: FileCheck --input-file=%t.cir %s --check-prefix=CIR -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -fcuda-is-device \ +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -x hip -fcuda-is-device \ // RUN: -foffload-uniform-block -fclangir -emit-cir %s -o %t.cir // RUN: FileCheck --input-file=%t.cir %s --check-prefix=CIR -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -fcuda-is-device \ +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -x hip -fcuda-is-device \ // RUN: -fclangir -emit-llvm %s -o %t-cir.ll // RUN: FileCheck --input-file=%t-cir.ll %s --check-prefix=LLVM -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -fcuda-is-device \ +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -x hip -fcuda-is-device \ // RUN: -foffload-uniform-block -fclangir -emit-llvm %s -o %t-cir.ll // RUN: FileCheck --input-file=%t-cir.ll %s --check-prefix=LLVM -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -fcuda-is-device \ +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -x hip -fcuda-is-device \ // RUN: -emit-llvm %s -o %t.ll // RUN: FileCheck --input-file=%t.ll %s --check-prefix=OGCG -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -fcuda-is-device \ +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -x hip -fcuda-is-device \ // RUN: -foffload-uniform-block -emit-llvm %s -o %t.ll // RUN: FileCheck --input-file=%t.ll %s --check-prefix=OGCG -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -fcuda-is-device \ +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -x hip -fcuda-is-device \ // RUN: -fno-offload-uniform-block -fclangir -emit-cir %s -o %t-noub.cir // RUN: FileCheck --input-file=%t-noub.cir %s --check-prefix=CIR-NOUB -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -fcuda-is-device \ +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -x hip -fcuda-is-device \ // RUN: -fno-offload-uniform-block -fclangir -emit-llvm %s -o %t-noub-cir.ll // RUN: FileCheck --input-file=%t-noub-cir.ll %s --check-prefix=NOUB -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -fcuda-is-device \ +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -x hip -fcuda-is-device \ // RUN: -fno-offload-uniform-block -emit-llvm %s -o %t-noub.ll // RUN: FileCheck --input-file=%t-noub.ll %s --check-prefix=NOUB diff --git a/clang/test/CIR/CodeGenHIP/atomic-classify.hip b/clang/test/CIR/CodeGenHIP/atomic-classify.hip index ad3ad771e6fbe..206f4dbcd65cf 100644 --- a/clang/test/CIR/CodeGenHIP/atomic-classify.hip +++ b/clang/test/CIR/CodeGenHIP/atomic-classify.hip @@ -1,7 +1,7 @@ // REQUIRES: amdgpu-registered-target -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -fclangir -fcuda-is-device \ +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -fclangir -fcuda-is-device \ // RUN: -emit-cir %s -o - | FileCheck --check-prefix=CIR %s -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -fclangir -fcuda-is-device \ +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -fclangir -fcuda-is-device \ // RUN: -emit-llvm %s -o - | FileCheck --check-prefix=LLVM %s #define __device__ __attribute__((device)) diff --git a/clang/test/CIR/CodeGenHIP/builtin-bool-result.hip b/clang/test/CIR/CodeGenHIP/builtin-bool-result.hip index 28efe28e4489f..3382d7f4fe497 100644 --- a/clang/test/CIR/CodeGenHIP/builtin-bool-result.hip +++ b/clang/test/CIR/CodeGenHIP/builtin-bool-result.hip @@ -1,10 +1,10 @@ // REQUIRES: amdgpu-registered-target -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -fclangir -fcuda-is-device \ +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -fclangir -fcuda-is-device \ // RUN: -emit-cir %s -o - | FileCheck --check-prefix=CIR %s -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -fclangir -fcuda-is-device \ +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -fclangir -fcuda-is-device \ // RUN: -emit-llvm %s -o - | FileCheck --check-prefix=LLVM %s // -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -fcuda-is-device -emit-llvm %s \ +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -fcuda-is-device -emit-llvm %s \ // RUN: -o - | FileCheck --check-prefix=LLVM %s // Checks that builtins returning an i1 can be used as bool results implicitly. diff --git a/clang/test/CIR/CodeGenHIP/builtins-amdgcn-wave32.hip b/clang/test/CIR/CodeGenHIP/builtins-amdgcn-wave32.hip index 34a930ca3f44c..caf43f4161bf6 100644 --- a/clang/test/CIR/CodeGenHIP/builtins-amdgcn-wave32.hip +++ b/clang/test/CIR/CodeGenHIP/builtins-amdgcn-wave32.hip @@ -1,14 +1,14 @@ // REQUIRES: amdgpu-registered-target -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -std=c++11 -fclangir \ -// RUN: -target-cpu gfx1100 -fcuda-is-device -emit-cir %s -o %t.cir +// RUN: %clang_cc1 -triple amdgpu11.00-amd-amdhsa -x hip -std=c++11 -fclangir \ +// RUN: -fcuda-is-device -emit-cir %s -o %t.cir // RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -std=c++11 -fclangir \ -// RUN: -target-cpu gfx1100 -fcuda-is-device -emit-llvm %s -o %t-cir.ll +// RUN: %clang_cc1 -triple amdgpu11.00-amd-amdhsa -x hip -std=c++11 -fclangir \ +// RUN: -fcuda-is-device -emit-llvm %s -o %t-cir.ll // RUN: FileCheck --check-prefix=LLVM --input-file=%t-cir.ll %s -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -std=c++11 \ -// RUN: -target-cpu gfx1100 -fcuda-is-device -emit-llvm %s -o %t.ll +// RUN: %clang_cc1 -triple amdgpu11.00-amd-amdhsa -x hip -std=c++11 \ +// RUN: -fcuda-is-device -emit-llvm %s -o %t.ll // RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s #define __device__ __attribute__((device)) diff --git a/clang/test/CIR/CodeGenHIP/builtins-amdgcn-wave64.hip b/clang/test/CIR/CodeGenHIP/builtins-amdgcn-wave64.hip index afe43f0cc6271..8cb7a7c0e3254 100644 --- a/clang/test/CIR/CodeGenHIP/builtins-amdgcn-wave64.hip +++ b/clang/test/CIR/CodeGenHIP/builtins-amdgcn-wave64.hip @@ -1,14 +1,14 @@ // REQUIRES: amdgpu-registered-target -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -std=c++11 -fclangir \ -// RUN: -target-cpu tahiti -fcuda-is-device -emit-cir %s -o %t.cir +// RUN: %clang_cc1 -triple amdgpu6.00-amd-amdhsa -x hip -std=c++11 -fclangir \ +// RUN: -fcuda-is-device -emit-cir %s -o %t.cir // RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -std=c++11 -fclangir \ -// RUN: -target-cpu tahiti -fcuda-is-device -emit-llvm %s -o %t-cir.ll +// RUN: %clang_cc1 -triple amdgpu6.00-amd-amdhsa -x hip -std=c++11 -fclangir \ +// RUN: -fcuda-is-device -emit-llvm %s -o %t-cir.ll // RUN: FileCheck --check-prefix=LLVM --input-file=%t-cir.ll %s -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -std=c++11 \ -// RUN: -target-cpu tahiti -fcuda-is-device -emit-llvm %s -o %t.ll +// RUN: %clang_cc1 -triple amdgpu6.00-amd-amdhsa -x hip -std=c++11 \ +// RUN: -fcuda-is-device -emit-llvm %s -o %t.ll // RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s #define __device__ __attribute__((device)) diff --git a/clang/test/CIR/CodeGenHIP/cleanup-alloca-addrspace.hip b/clang/test/CIR/CodeGenHIP/cleanup-alloca-addrspace.hip index 83b05227f0845..c55cd55a98d67 100644 --- a/clang/test/CIR/CodeGenHIP/cleanup-alloca-addrspace.hip +++ b/clang/test/CIR/CodeGenHIP/cleanup-alloca-addrspace.hip @@ -1,7 +1,7 @@ -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -fclangir -fcuda-is-device -emit-cir %s -o %t.cir +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -x hip -fclangir -fcuda-is-device -emit-cir %s -o %t.cir // RUN: cir-opt --cir-flatten-cfg %t.cir -o %t-flat.cir // RUN: FileCheck --input-file=%t-flat.cir %s --check-prefix=CIR-FLAT -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -fclangir -fcuda-is-device -emit-llvm %s -o - | FileCheck %s --check-prefix=LLVM +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -x hip -fclangir -fcuda-is-device -emit-llvm %s -o - | FileCheck %s --check-prefix=LLVM // Check that alloca created for cleanup destination slot for a function has // correct address space after flatten cfg. This is important for address-space diff --git a/clang/test/CIR/CodeGenHIP/ternary-struct-addrspace.hip b/clang/test/CIR/CodeGenHIP/ternary-struct-addrspace.hip index 6714c2bef0890..42ab9f4d6afce 100644 --- a/clang/test/CIR/CodeGenHIP/ternary-struct-addrspace.hip +++ b/clang/test/CIR/CodeGenHIP/ternary-struct-addrspace.hip @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -fclangir -fcuda-is-device -emit-cir %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple amdgpu7.00-amd-amdhsa -x hip -fclangir -fcuda-is-device -emit-cir %s -o - | FileCheck %s // Verify that a ternary expression returning a struct parameter from a // __device__ function produces a well-typed cir.ternary: both branch yields _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
