https://github.com/iamvickynguyen created https://github.com/llvm/llvm-project/pull/228789
Add CIR lowering and tests for plain SVE `svpfalse_b` (https://developer.arm.com/architectures/instruction-sets/intrinsics/#q=svpfalse). Port: `clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfalse.c` to `clang/test/CodeGen/AArch64/sve/pfalse.c` Part of https://github.com/llvm/llvm-project/issues/223963. >From 61308e3f742615ebbaaebe81cc46be3c78ab3784 Mon Sep 17 00:00:00 2001 From: Vicky Nguyen <[email protected]> Date: Sat, 3 Oct 2026 14:04:30 -0700 Subject: [PATCH] [clang][CIR] Lower SVE svpfalse_b and add tests --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 8 ++++ .../AArch64/sve-intrinsics/acle_sve_pfalse.c | 36 --------------- clang/test/CodeGen/AArch64/sve/pfalse.c | 45 +++++++++++++++++++ 3 files changed, 53 insertions(+), 36 deletions(-) delete mode 100644 clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfalse.c create mode 100644 clang/test/CodeGen/AArch64/sve/pfalse.c diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index 70253221c7b7d..c69f50385a8ed 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -1860,7 +1860,15 @@ CIRGenFunction::emitAArch64SVEBuiltinExpr(unsigned builtinID, case SVE::BI__builtin_sve_svdupq_n_u32: case SVE::BI__builtin_sve_svdupq_n_f32: case SVE::BI__builtin_sve_svdupq_n_s32: + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AArch64 builtin call: ") + + getContext().BuiltinInfo.getName(builtinID)); + return mlir::Value{}; + case SVE::BI__builtin_sve_svpfalse_b: + return builder.getNullValue(convertType(expr->getType()), + getLoc(expr->getExprLoc())); + case SVE::BI__builtin_sve_svpfalse_c: cgm.errorNYI(expr->getSourceRange(), std::string("unimplemented AArch64 builtin call: ") + diff --git a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfalse.c b/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfalse.c deleted file mode 100644 index 375ed4ed96044..0000000000000 --- a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfalse.c +++ /dev/null @@ -1,36 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s -// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s - -#include <arm_sve.h> - -#if defined __ARM_FEATURE_SME -#define MODE_ATTR __arm_streaming -#else -#define MODE_ATTR -#endif - -#ifdef SVE_OVERLOADED_FORMS -// A simple used,unused... macro, long enough to represent any SVE builtin. -#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 -#else -#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 -#endif - -// CHECK-LABEL: @test_svpfalse_b( -// CHECK-NEXT: entry: -// CHECK-NEXT: ret <vscale x 16 x i1> zeroinitializer -// -// CPP-CHECK-LABEL: @_Z15test_svpfalse_bv( -// CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: ret <vscale x 16 x i1> zeroinitializer -// -svbool_t test_svpfalse_b(void) MODE_ATTR -{ - return SVE_ACLE_FUNC(svpfalse,_b,,)(); -} diff --git a/clang/test/CodeGen/AArch64/sve/pfalse.c b/clang/test/CodeGen/AArch64/sve/pfalse.c new file mode 100644 index 0000000000000..2b557abdf71a2 --- /dev/null +++ b/clang/test/CodeGen/AArch64/sve/pfalse.c @@ -0,0 +1,45 @@ +// REQUIRES: aarch64-registered-target + +// DEFINE: %{optimize} = opt -passes=mem2reg -S + +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -fclangir -emit-cir -disable-O0-optnone -o - %s | FileCheck %s --check-prefixes=C,CIR %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-cir -disable-O0-optnone -o - %s | FileCheck %s --check-prefixes=C,CIR %} + +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -fclangir -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -fclangir -emit-llvm -disable-O0-optnone -o - -x c++ %s | %{optimize} | FileCheck %s --check-prefixes=CPP,LLVM %} + +// RUN: %clang_cc1_cg_arm64_sve -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM +// RUN: %clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -emit-llvm -disable-O0-optnone -o - %s | %{optimize} | FileCheck %s --check-prefixes=C,LLVM +// RUN: %clang_cc1_cg_arm64_sve -DSVE_OVERLOADED_FORMS -emit-llvm -disable-O0-optnone -o - -x c++ %s | %{optimize} | FileCheck %s --check-prefixes=CPP,LLVM + +//============================================================================= +// NOTES +// +// Tests for SVE PFALSE intrinsics (svpfalse_b only; svpfalse_c is SVE2.1) +//============================================================================= + +#include <arm_sve.h> + +#if defined __ARM_FEATURE_SME +#define MODE_ATTR __arm_streaming +#else +#define MODE_ATTR +#endif + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 +#endif + +// C-LABEL: @test_svpfalse_b( +// CPP-LABEL: @_Z15test_svpfalse_bv( +svbool_t test_svpfalse_b(void) MODE_ATTR +{ +// CIR: cir.const #cir.zero : !cir.vector<[16] x !cir.int<u, 1>> + +// LLVM: ret <vscale x 16 x i1> zeroinitializer + return SVE_ACLE_FUNC(svpfalse,_b,,)(); +} _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
